A VPX power interface control board

Abstract

The utility model discloses a VPX power interface control board belongs to electronic equipment power management and interface control technical field. The control board is integrated on VPX standard board card, including system interface unit, FPGA system unit, power conversion unit, drive isolation unit, voltage current detection unit and temperature detection unit. The power conversion unit adopts the topology structure of DCDC and LDO combination, and the external input +12V power conversion is the required multichannel power supply of module inside, FPGA system unit passes drive isolation unit and radio frequency module connection, is used for generating and isolating control signal, voltage current detection unit and temperature detection unit real -time monitoring module's power supply state and working temperature respectively. The utility model discloses through the highly integrated circuit design, has realized multichannel high accuracy power conversion, strong anti -interference control signal isolation and comprehensive state monitoring function, has improved VPX module's reliability, controllability and maintainability significantly.

Description

Technical Field

[0001] This utility model relates to the field of power management and interface control technology for electronic devices, and in particular to a VPX power interface control board. Background Technology

[0002] The VPX bus standard is a modular standard widely adopted in next-generation military / civilian electronic equipment. Its core modules (such as multi-channel broadband receivers) typically require complex, stable, multi-channel power supplies and precise digital control. The RF circuits inside these modules (such as amplifiers, mixers, filters, and attenuators) have extremely high requirements for power supply ripple, noise, and stability. At the same time, a large number of digital control signals (such as SPI and LVTTL) need to be isolated from sensitive analog RF circuits to prevent digital noise from interfering with RF performance.

[0003] Existing VPX module power supply and control solutions have the following shortcomings: First, the power management section is usually composed of multiple scattered power modules, resulting in low board area utilization, low power density, and difficulty in achieving unified protection and management; second, there is often a lack of effective electrical isolation between digital control signals and RF modules, and digital noise can easily crosstalk to the RF link through the control lines, degrading the receiver's noise figure and dynamic range; third, there is a lack of integrated real-time monitoring functions for voltage, current, and temperature, or the monitoring accuracy and real-time performance are insufficient, making it difficult to provide effective data support for system health management (PHM) and fault diagnosis.

[0004] Therefore, there is an urgent need for a highly integrated, fully functional, and interference-resistant dedicated power interface control board to solve the power supply, control, and status monitoring problems of VPX high-performance modules, especially multi-channel RF modules. Utility Model Content

[0005] The purpose of this invention is to overcome the problems existing in the prior art and to provide a VPX power interface control board.

[0006] The objective of this utility model is achieved through the following technical solution: A VPX power interface control board, integrated on a VPX standard board, includes a system interface unit and an FPGA system unit, wherein an SPI communication unit, a power module and a level conversion unit are respectively connected between the system interface unit and the FPGA system unit; The FPGA system unit is connected to a status monitoring module, which includes a voltage and current detection unit, a temperature detection unit, a BIT status detection unit, and a frequency synthesizer lockout indication detection unit. The FPGA system includes a main control chip and peripheral circuits. The peripheral circuits include a clock circuit, a configuration circuit, and a reset circuit. The main control chip is also connected to an external radio frequency module through a drive isolation unit.

[0007] In some embodiments, the main control chip is model XC6SLX25-2CSG324I.

[0008] In some embodiments, the clock circuit includes a clock chip, the model of which is BT0503BH3I106BN40; the configuration circuit includes a configuration FLASH chip, the model of which is M25P16-VMN6; and the reset circuit includes a pull-up resistor.

[0009] In some embodiments, the drive isolation unit includes a drive isolation chip, wherein the drive isolation chip is of model number SN74LVCH16T245DGGR.

[0010] In some embodiments, the voltage and current detection unit includes a voltage and current detection chip, the model of which is ISL28022.

[0011] In some embodiments, the temperature detection unit includes a temperature sensor, the temperature sensor being of model DS18B20.

[0012] In some embodiments, the level conversion unit includes a level conversion chip, wherein the level conversion chip is model 74VHC245MTC.

[0013] In some embodiments, the BIT state detection unit includes an amplifier and a comparator connected in sequence, wherein the amplifier is an AD8313 and the comparator is a TL331IDBVR.

[0014] In some embodiments, the power module includes a surge protection circuit, an EMI filter circuit, a first-stage DC / DC converter, a second-stage DC / DC converter, and at least one LDO linear regulator connected in sequence.

[0015] In some embodiments, the system interface unit includes a VITA-compliant VPX hybrid connector.

[0016] It should be further noted that the technical features corresponding to the above-mentioned options and embodiments can be combined or substituted to form new technical solutions.

[0017] Compared with the prior art, the beneficial effects of this utility model are: 1. High integration and modularity: Multiple functions such as multi-channel power conversion, FPGA core control, signal drive isolation, and status monitoring are highly integrated onto a single standard VPX board. This modular design replaces the traditional distributed solution, greatly improving the board's space utilization, simplifying the internal system design of the VPX module, and facilitating mass production and maintenance replacement.

[0018] 2. High-efficiency, clean multi-channel power output: Employing a hybrid power topology of "DC / DC + LDO". The front-end DC / DC converter achieves high-efficiency voltage conversion (e.g., 12V to 5.5V), while the rear-end LDO linear regulator provides low-noise, high-precision stable voltages (e.g., +5V, +3.3V) for noise-sensitive RF and digital circuits. This design balances conversion efficiency and power quality, effectively ensuring the performance specifications of the RF link.

[0019] 3. Strong anti-interference capability: An electrical isolation barrier is established between the FPGA control terminal and the RF load terminal through a dedicated driver isolation unit (such as SN74LVCH16T245DGGR). This effectively blocks digital circuit switching noise from crosstalking to sensitive RF circuits through the control lines, significantly improving the receiver's noise performance and signal integrity.

[0020] 4. Comprehensive status monitoring and high reliability: It integrates a high-precision voltage and current detection chip (ISL28022) and a temperature sensor (DS18B20), which can monitor the power consumption and temperature rise of the module in real time and accurately. This provides key information for system health management, overload protection, thermal management and fault diagnosis, thereby greatly improving the working reliability and service life of the entire VPX module. Attached Figure Description

[0021] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the present application. The same reference numerals are used in these drawings to denote the same or similar parts. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application.

[0022] Figure 1 This is a schematic diagram of the structure of a VPX power interface control board according to the present invention; Figure 2 This is a schematic diagram of the FPGA system unit of this utility model; Figure 3 This is a schematic diagram of the LDO voltage regulator circuit of this utility model; Figure 4 This is the clock schematic diagram of the FPGA system of this utility model; Figure 5This is a schematic diagram of the Spartan-6 FPGA SPI configuration circuit of this utility model; Figure 6 This is a schematic diagram of the reset circuit of this utility model; Figure 7 This is a schematic diagram of the drive isolation unit of this utility model; Figure 8 This is a schematic diagram of the voltage and current detection circuit of this utility model; Figure 9 This is a schematic diagram of the temperature detection circuit of this utility model; Figure 10 This is a schematic diagram of the level conversion circuit of this utility model; Figure 11 This is a schematic diagram of the BIT status detection circuit of this utility model; Figure 12 This is a topology diagram of the power module of this utility model; Figure 13 This is a schematic diagram of the surge protection and EMI filtering circuit of this utility model; Figure 14 This is a schematic diagram of the conversion circuits at each stage of this utility model. Detailed Implementation

[0023] The technical solution of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0024] In the description of this utility model, it should be noted that the directions or positional relationships indicated by terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this utility model. Furthermore, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0025] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0026] Furthermore, the technical features involved in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.

[0027] In one exemplary embodiment, such as Figure 1 As shown, a VPX power interface control board is provided, which is integrated on a VPX standard board. It includes a system interface unit and an FPGA system unit. An SPI communication unit, a power module, and a level conversion unit are respectively connected between the system interface unit and the FPGA system unit. The FPGA system unit is connected to a status monitoring module, which includes a voltage and current detection unit, a temperature detection unit, a BIT status detection unit, and a frequency synthesizer lockout indication detection unit. like Figure 2 As shown, the FPGA system includes a main control chip and peripheral circuits. The peripheral circuits include a clock circuit, a configuration circuit, and a reset circuit. The main control chip is also connected to an external radio frequency module through a drive isolation unit.

[0028] In this embodiment, the main control chip is model XC6SLX25-2CSG324I. The chip requires a core voltage of 1.2V and a port voltage of 3.3V to operate. The operating voltage of the FPGA main control chip and the FLASH configuration chip can be generated by using a +5V input voltage regulated by an LDO and then further regulated by an LT1963AMPS8 regulator. The LDO regulator circuit design is as follows... Figure 3 As shown.

[0029] The clock circuit includes a clock chip, model BT0503BH3I106BN40, which introduces a 40MHz clock to the global clock pin of the FPGA. The FPGA system clock schematic is shown below. Figure 4 As shown.

[0030] The configuration circuit includes a configuration FLASH chip, model M25P16-VMN6; the FPGA chip XC6SLX25-2CSG324I is connected to the FLASH chip M25P16-VMN6 via Master Serial / SPI mode. The Spartan-6 FPGA SPI configuration circuit is as follows: Figure 5 As shown.

[0031] The reset circuit includes a pull-up resistor. The FPGA system reset uses a 4.7K pull-up resistor connected to the FPGA's PROGRAM_B_2 pin, such as... Figure 6 As shown.

[0032] The driver isolation unit primarily serves to isolate and enhance the driving capability between the FPGA chip and the RF module interface. The switching control signals and attenuation control signals required by the RF module are generated by the FPGA and sent to the RF module after passing through this unit to complete the corresponding control functions. The driver isolation unit includes a driver isolation chip, specifically the SN74LVCH16T245DGGR. The schematic design of the driver isolation unit is shown below. Figure 7 As shown.

[0033] In this embodiment, the voltage and current detection unit is implemented through an MCU coprocessor unit. This MCU coprocessor unit acts as a "coprocessor" for the FPGA, focusing on analog data acquisition, freeing up FPGA resources. It packages and sends the acquired data to the FPGA via a UART serial port (115200 baud rate). Specifically, the voltage and current detection unit includes a voltage and current detection chip, model ISL28022, which uses I2C for data communication with the MCU. The voltage and current acquisition circuit is as follows... Figure 8 As shown.

[0034] The temperature detection unit includes a temperature sensor, model DS18B20. The temperature resolution is selectable from 9 to 12 bits; at the highest 12-bit accuracy, the temperature conversion speed is less than 400ms, and the measurement range is -55℃ to +125℃. Data exchange is performed via a single bus. The temperature detection circuit is as follows: Figure 9 As shown.

[0035] The level conversion unit includes a level conversion chip, specifically a 74VHC245MTC. The single-ended SPI is converted to LVTTL level by the 74VHC245MTC before being connected to the FPGA. The typical transmission delay of the 74VHC245MTC is 4ns. The level conversion circuit for the single-ended SPI is as follows: Figure 10 As shown.

[0036] The BIT status detection unit includes an amplifier and a comparator connected in sequence. The amplifier is an AD8313, and the comparator is a TL331IDBVR. The BIT self-test function is implemented by detecting the output signal. The detection point is placed at the last stage of the RF link, enabling detection of the entire RF link. The detected level of the output signal is compared and then fed into the FPGA. The system is fed back via serial port after detecting all bits in the channel. The BIT status detection circuit is as follows: Figure 11 As shown.

[0037] Furthermore, such as Figure 12 As shown, the power supply module includes a surge protection circuit, an EMI filter circuit, a first-stage DC / DC converter, a second-stage DC / DC converter, and at least one LDO linear regulator connected in sequence. The +12V supplied by the system is converted to +5.5V by the first-stage DC / DC converter, then to a negative voltage by the second-stage DC / DC converter, and finally converted to the operating voltage required by each functional circuit by the LDO linear regulator, thus powering each functional circuit unit. The surge protection and EMI filtering circuits are as follows... Figure 13 As shown in the diagram above, the power supplies for the electrical modules are all designed with enable functionality. When the power enable is floating, the module's internal pull-up switch keeps the power supply module on; when the power enable is low, the module's EN switch is pulled low, and the module's power supply is off. The conversion circuits at each stage are as follows: Figure 14 As shown.

[0038] Furthermore, the system interface unit includes a VITA-compliant VPX hybrid connector. The frequency synthesizer lockout indication detection unit is used to detect the LVTTL level of each phase-locked loop lockout indication in the RF module.

[0039] The above detailed embodiments are a detailed description of the present utility model. It should not be considered that the specific embodiments of the present utility model are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present utility model, and all of these should be considered to fall within the protection scope of the present utility model.

Claims

1. A VPX power interface control board, characterized in that, Integrated on the VPX standard board, it includes a system interface unit and an FPGA system unit, and the system interface unit and the FPGA system unit are respectively connected to an SPI communication unit, a power supply module and a level conversion unit; The FPGA system unit is connected to a status monitoring module, which includes a voltage and current detection unit, a temperature detection unit, a BIT status detection unit, and a frequency synthesizer lockout indication detection unit. The FPGA system includes a main control chip and peripheral circuits. The peripheral circuits include a clock circuit, a configuration circuit, and a reset circuit. The main control chip is also connected to an external radio frequency module through a drive isolation unit.

2. The VPX power interface control board according to claim 1, characterized in that, The main control chip is model XC6SLX25-2CSG324I.

3. The VPX power interface control board according to claim 1, characterized in that, The clock circuit includes a clock chip, model number BT0503BH3I106BN40; the configuration circuit includes a configuration FLASH chip, model number M25P16-VMN6; and the reset circuit includes a pull-up resistor.

4. The VPX power interface control board according to claim 1, characterized in that, The drive isolation unit includes a drive isolation chip, the model of which is SN74LVCH16T245DGGR.

5. A VPX power interface control board according to claim 1, characterized in that, The voltage and current detection unit includes a voltage and current detection chip, the model of which is ISL28022.

6. The VPX power interface control board according to claim 1, characterized in that, The temperature detection unit includes a temperature sensor, which is a DS18B20.

7. A VPX power interface control board according to claim 1, characterized in that, The level conversion unit includes a level conversion chip, the model of which is 74VHC245MTC.

8. A VPX power interface control board according to claim 1, characterized in that, The BIT status detection unit includes an amplifier and a comparator connected in sequence. The amplifier is model AD8313 and the comparator is model TL331IDBVR.

9. A VPX power interface control board according to claim 1, characterized in that, The power module includes a surge protection circuit, an EMI filter circuit, a first-stage DC / DC converter, a second-stage DC / DC converter, and at least one LDO linear regulator connected in sequence.

10. A VPX power interface control board according to claim 1, characterized in that, The system interface unit includes a VITA-compliant VPX hybrid connector.

Images