A power-on reset circuit and central processing unit

Abstract

The application relates to the technical field of power-on reset, and discloses a power-on reset circuit and a central processing unit. The power-on reset circuit comprises a key input module, a first reset module, a reset monitoring module, a first logic output module and a second logic output module. The key input module is used for providing a target key input signal after signal processing. The first reset module is used for outputting a first reset signal. The reset monitoring module is used for outputting a level signal indicating that the central processing unit is not powered on. The first logic output module is used for outputting a first logic signal. The second logic output module is used for outputting a second logic signal to a timing control circuit and outputting a third logic signal to a power supply circuit. According to the application, the key input signal is processed, interference signals are prevented from affecting the power-on reset, the CPU power-on reset can be realized while avoiding power-on mis-triggering, and the reliability of the CPU power-on reset is improved.

Description

Technical Field

[0001] This application relates to the field of power-on reset technology, and more particularly to a power-on reset circuit and a central processing unit. Background Technology

[0002] The power-on reset circuit is crucial for the startup and stable operation of a computer system. Its core function is to generate a reset signal through an RC delay circuit or voltage monitoring chip when the power is turned on, forcing critical units such as the registers and program counter of the Central Processing Unit (CPU) to return to zero, ensuring that instruction execution begins from a known state. However, existing RC reset circuits are affected by the tolerances of resistors and capacitors, and the reset time is easily affected by temperature changes and component aging, which may lead to reset failure. Power supply glitches or high-frequency noise may interfere with the reset signal, resulting in false resets or incomplete resets. Utility Model Content

[0003] In view of this, embodiments of this application provide a power-on reset circuit and a central processing unit, which can effectively solve the problem of easy reset failure upon power-on.

[0004] In a first aspect, embodiments of this application provide a power-on reset circuit, including: a key input module, a first reset module, a reset monitoring module, a first logic output module, and a second logic output module; The key input module is connected to the first reset module and the reset monitoring module respectively. The first reset module and the reset monitoring module are connected to the first logic output module respectively. The first logic output module is connected to the second logic output module. The second logic output module is connected to the timing control circuit and the power supply circuit of the central processing unit respectively. The key input module is used to provide the target key input signal after signal processing; The first reset module is used to output a first reset signal when the target key input signal is received; The reset monitoring module is used to output a level signal indicating that the central processing unit is not powered on when the target key input signal is received. The first logic output module is used to output a first logic signal upon receiving the first reset signal and the level signal; The second logic output module is used to output a second logic signal to the timing control circuit and a third logic signal to the power supply circuit when the first logic signal is received, so as to power on the central processing unit.

[0005] In a first possible embodiment of the first aspect, it further includes: a central processing unit wake-up module; The central processing unit wake-up module is connected to the key input module; The central processing unit wake-up module is used to wake up the central processing unit in a dormant state upon receiving the target key input signal. In a second possible embodiment of the first aspect, the key input module includes a key, a key debouncing unit, and a Schmitt trigger unit connected in sequence. The button is used to output an initial button input signal; The key debouncing unit is used to filter out interference pulses in the initial key input signal and generate the initial key input signal after debouncing. The Schmitt trigger unit is used to perform hysteresis comparison processing on the initial key input signal after debouncing processing, and output the target key input signal.

[0006] In a third possible embodiment of the first aspect, the key debouncing unit includes a bidirectional diode, a first filter capacitor and a first pull-up resistor, and the Schmitt trigger unit includes a Schmitt trigger. The button connects to the parallel node of the bidirectional diode and the first filter capacitor. The parallel node of the bidirectional diode and the first filter capacitor is also used to connect the first pull-up resistor and the Schmitt trigger, respectively. The output terminal of the Schmitt trigger is used to connect the first reset module and the reset monitoring module, respectively. Both the bidirectional diode and the first filter capacitor are grounded, and the first pull-up resistor is connected to the power supply.

[0007] In a fourth possible embodiment of the first aspect, the central processing unit wake-up module includes a driver and a second pull-up resistor; The input terminal of the driver is connected to the key input module, and the output terminal of the driver is connected to the second pull-up resistor and the central processing unit respectively. The second pull-up resistor is connected to the power supply.

[0008] In a fifth possible embodiment of the first aspect, the first reset module includes a first reset chip; The input terminal of the first reset chip is connected to the key input module, and the output terminal of the first reset chip is connected to the first logic output module. In a sixth possible embodiment of the first aspect, the reset monitoring module includes a second reset chip and a multi-input logic device; The input terminal of the second reset chip is connected to the key input module, and the output terminal of the second reset chip is connected to the input terminal of the multi-input logic device. The input terminals of the multi-input logic device are also used to connect to the central processing unit to receive control signals indicating that the central processing unit is in a power-off state; The second reset chip is used to output a second reset signal when the target key input signal is received; The output terminal of the multi-input logic device is connected to the first logic output module; The multi-input logic device is used to output the level signal when it receives the second reset signal and the control signal.

[0009] In a seventh possible embodiment of the first aspect, the first logic output module includes a dual D flip-flop, a first AND gate, a second pull-up resistor, and a third pull-up resistor; The dual D flip-flop is connected to the first reset module and the reset monitoring module. The first input terminal of the first AND gate is connected to the dual D flip-flop and the second pull-up resistor, respectively. The second input terminal of the first AND gate is connected to the third pull-up resistor. The second pull-up resistor and the third pull-up resistor are connected to the power supply. The dual D flip-flop is used to output an intermediate logic signal when it receives the first reset signal and a level signal indicating that the central processing unit is not powered on. The first AND gate outputs the first logic signal upon receiving the intermediate logic signal.

[0010] In an eighth possible embodiment of the first aspect, the second logic output module includes a second AND gate and an OR gate; The input terminals of the second AND gate are respectively connected to the power chip and the first logic output module to receive a first level signal indicating that the power chip is not in a working state and the first logic signal; The input terminals of the OR gate are respectively connected to the power management chip and the first logic output module to receive a second level signal indicating that the power management chip is not in a working state and the second logic signal; The second AND gate is used to output the second logic signal to the timing control circuit when the first level signal and the first logic signal are received, so as to enable the central processing unit to power on in a timing manner; The OR gate is used to output the third logic signal to the power supply circuit when the second level signal and the first logic signal are received, so as to power on the power supply terminal of the central processing unit.

[0011] Secondly, embodiments of this application provide a central processing unit, including: a timing control circuit, a power supply circuit, and the aforementioned power-on reset circuit, wherein the power-on reset circuit is connected to the timing control circuit and the power supply circuit respectively.

[0012] The embodiments of this application have the following beneficial effects: This embodiment of a power-on reset circuit includes: a key input module, a first reset module, a reset monitoring module, a first logic output module, and a second logic output module. The key input module is connected to the first reset module and the reset monitoring module; the first reset module and the reset monitoring module are connected to the first logic output module; the first logic output module is connected to the second logic output module; and the second logic output module is connected to a timing control circuit and a power supply circuit. The key input module provides a target key input signal after signal processing. The first reset module outputs a first reset signal. The reset monitoring module outputs a level signal indicating that the central processing unit (CPU) is not powered on. The first logic output module outputs a first logic signal. The second logic output module outputs a second logic signal to the timing control circuit and a third logic signal to the power supply circuit to power on the CPU. This application processes the key input signal to avoid interference signals affecting the power-on reset, ensuring that the CPU power-on reset is triggered only when the CPU is not powered on, thus avoiding false triggering upon power-on. The power-on reset circuit can control the CPU's timing control circuit and power supply circuit, achieving complete CPU reset and improving the reliability of CPU power-on reset. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This paper shows a schematic diagram of a first structure of the power-on reset circuit according to an embodiment of this application; Figure 2 A schematic diagram of a second structure of the power-on reset circuit according to an embodiment of this application is shown; Figure 3 This paper shows a schematic diagram of a key input module according to an embodiment of the present application; Figure 4 A circuit diagram of a key input module according to an embodiment of this application is shown; Figure 5 This paper shows a circuit diagram of a central processing unit wake-up module according to an embodiment of the present application; Figure 6 A circuit diagram of a first reset module according to an embodiment of this application is shown; Figure 7 A circuit diagram of a reset monitoring module according to an embodiment of this application is shown; Figure 8 This paper shows a circuit diagram of a first logic output module according to an embodiment of the present application; Figure 9 A circuit diagram of a second logic output module according to an embodiment of this application is shown.

[0015] Explanation of key component symbols: 100 - Power-on reset circuit; 110 - Key input module; 120 - First reset module; 130 - Reset monitoring module; 140 - First logic output module; 150 - Second logic output module; 160 - Central processing unit wake-up module. Detailed Implementation

[0016] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0017] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0018] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0019] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0020] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0021] The power-on reset circuit 100 can handle abnormal situations such as voltage fluctuations and program crashes, restoring the system to a controllable state through hardware-level reset. The design must match the CPU's logic level and reset time requirements to avoid startup failure due to insufficient or excessive reset. Furthermore, some circuits also support manual reset or automatic reset due to watchdog timeout, further improving system reliability. However, the existing power-on reset circuit 100 suffers from problems such as power supply glitches potentially leading to false resets or incomplete resets, resulting in power-on failures. Moreover, some chips with watchdog functionality have high power consumption, requiring continuous watchdog feeding. The reset signal generated by the reset chip needs to be triggered at the clock edge; if the clock is unstable (e.g., in a gated clock scenario), reset failure may occur. The reset signal is susceptible to electromagnetic interference, sensitive to power supply fluctuations, and has a high false trigger rate.

[0022] To address the aforementioned issues, this application provides a power-on reset circuit 100 and a central processing unit (CPU), which can provide a stable power-on reset for the CPU under various CPU circuit conditions, thereby resolving the problem of unstable CPU power-on reset, reducing the false reset rate, and improving reset reliability.

[0023] The power-on reset circuit 100 will be described below with reference to some specific embodiments.

[0024] Figure 1 A schematic diagram of a power-on reset circuit 100 according to an embodiment of this application is shown. Exemplarily, the power-on reset circuit 100 includes a key input module 110, a first reset module 120, a reset monitoring module 130, a first logic output module 140, and a second logic output module 150. The key input module 110 is connected to both the first reset module 120 and the reset monitoring module 130. The first reset module 120 and the reset monitoring module 130 are connected to both the first logic output module 140. The first logic output module 140 is connected to the second logic output module 150. The second logic output module 150 is connected to both the timing control circuit and the power supply circuit of the central processing unit.

[0025] In this embodiment, the key input module 110 provides a target key input signal after signal processing; the first reset module 120 outputs a first reset signal upon receiving the target key input signal; the reset monitoring module 130 outputs a level signal indicating that the central processing unit is not powered on upon receiving the target key input signal; and the first logic output module 140 outputs a first logic signal upon receiving both the first reset signal and the level signal. This application, by introducing a dual conditional logic judgment of the CPU not being powered on level signal and the reset signal, ensures that the main power supply is only turned on when the CPU truly needs to start, thereby avoiding misoperation, improving the reliability of power-on reset, and preventing accidental triggering.

[0026] The second logic output module 150 is used to output a second logic signal to the timing control circuit upon receiving the first logic signal, thereby triggering the sequential startup process of the multi-stage power supply. The second logic output module 150 is also used to output a third logic signal to the power supply circuit to power on the central processing unit and activate the core voltage source.

[0027] In one embodiment, such as Figure 2 As shown, the power-on reset circuit 100 also includes a central processing unit (CPU) wake-up module 160, which is exemplary connected to the key input module 110. The CPU wake-up module 160 is used to wake up the CPU from its dormant state upon receiving a target key input signal. The power-on reset circuit 100 can wake up the CPU and reset the CPU in parallel, achieving a balance between low power consumption and high-performance response compared to a cold start after a complete power failure.

[0028] To better understand the power-on reset circuit 100, the components of the power-on reset circuit 100 will be described in detail below.

[0029] In one embodiment, such as Figure 3 As shown, the key input module 110 includes a key 111, a key debouncing unit 112, and a Schmitt trigger unit 113 connected in sequence; the key 111 is used to output an initial key input signal; the key debouncing unit 112 is used to filter out interference pulses in the initial key input signal and generate an initial key input signal after debouncing processing; the Schmitt trigger unit 113 is used to perform hysteresis comparison processing on the initial key input signal after debouncing processing and output a target key input signal.

[0030] In one implementation, such as Figure 4 As shown, the button debouncing unit 112 includes a bidirectional diode D1, a first filter capacitor C1, and a first pull-up resistor R1, and the Schmitt trigger unit 113 includes a Schmitt trigger U1. Exemplarily, button 111 (as shown) Figure 4The parallel node of bidirectional diode D1 and first filter capacitor C1 shown in SW1 is also used to connect the first pull-up resistor R1 and Schmitt trigger U1, respectively. The output terminal of Schmitt trigger U1 is used to connect the first reset module 120 and the reset monitoring module 130, respectively. Both bidirectional diode D1 and first filter capacitor C1 are grounded, and the first pull-up resistor R1 is connected to the power supply. The power supply terminal of Schmitt trigger U1 is connected to the power supply and the second filter capacitor C2. The power supply is VMAIN (Main Power Supply Voltage) shown in the figure. The second filter capacitor C2 is grounded, and the ground terminal of Schmitt trigger U1 is grounded.

[0031] In this embodiment, button 111 is used to output the initial button input signal, that is, the original voltage jump signal generated when the user presses button 111. The button debouncing unit 112 is used to filter out interference pulses in the initial button input signal. The Schmitt trigger unit 113 is used to perform hysteresis comparison processing on the initial button input signal after debouncing, and convert it into a target button input signal with steep edges and good noise tolerance (such as...). Figure 4 The USER-PB shown is output to subsequent circuits to filter out interference and reduce the false reset trigger rate.

[0032] In one embodiment, such as Figure 5 As shown, the central processing unit wake-up module 160 includes a driver U2 and a second pull-up resistor R2. Exemplarily, the input of the driver U2 is connected to the key input module 110, and the output of the driver U2 is connected to the second pull-up resistor R2 and the central processing unit. The second pull-up resistor R2 is connected to the power supply (e.g., power supply). Figure 5 (VDD shown). The power supply terminal of driver U2 is also connected to the power supply and the third filter capacitor C3, which is grounded. The power supply terminal and ground terminal of driver U2 are grounded.

[0033] In this embodiment, driver U2 is a single-channel open-drain output driver U2. The output terminal has an internal open-drain structure and requires an external pull-up resistor to output a high level. When the target button input signal is input to driver U2, the internal transistor is cut off, and the second pull-up resistor R2 pulls the output terminal (e.g., ...) to the external transistor. Figure 5 The Y signal shown is pulled high to provide a wake-up signal (e.g., Y). Figure 5 The SOC_WAKE parameter shown triggers CPU wake-up. In one embodiment, such as Figure 6 As shown, the first reset module 120 includes a first reset chip U3. Exemplarily, the input terminal of the first reset chip U3 is connected to the key input module 110, and the output terminal of the first reset chip U3 (e.g., ...) is connected to the key input module 110. Figure 6 shown The first logic output module 140 is connected to the first reset chip U3. The input terminal of the first reset chip U3 (e.g., ...) is connected to the first logic output module 140. Figure 6 shown ), reset delay configuration terminal (such as Figure 6 The CTs shown are all connected through a pull-up resistor (such as...). Figure 6 R3 and R4 (as shown) are connected to the power supply. The reset delay configuration terminal is also grounded through a filter capacitor C5. The power supply terminal of the first reset chip (as shown) Figure 6 The VDD terminal and power monitoring terminal (as shown) are shown. Figure 6 All SENSEs shown are connected to a power source.

[0034] In this embodiment, the first reset chip U3 is a dedicated chip for power monitoring / manual reset. The input terminal of the first reset chip U3 receives a target button input signal, triggering a manual reset and outputting a first reset signal (e.g., ...). Figure 6 The VSYSMON_RESET parameter, as shown, is sent to the subsequent circuitry as a system reset request. In one embodiment, such as Figure 7 As shown, the reset monitoring module 130 includes a second reset chip U4 and a multi-input logic device U5. Exemplarily, the input terminal of the second reset chip U4 is connected to the key input module 110, and the output terminal of the second reset chip U4 is connected to the input terminal of the multi-input logic device U5. The input terminal of the multi-input logic device U5 is also used to connect to the central processing unit (CPU) to receive control signals indicating that the CPU is in a power-off state (e.g., ...). Figure 7 As shown in SYS_MCU_PWRDN).

[0035] In one embodiment, the second reset chip U4 is used to output a second reset signal upon receiving a target key input signal to indicate a triggered key reset. The output of the multi-input logic device U5 is connected to the first logic output module 140; the multi-input logic device U5 is used to output a level signal indicating that the central processing unit is not powered on (e.g., upon receiving the second reset signal and a control signal). Figure 7 (Showing SYS_POWER_OFF).

[0036] Among them, the second reset chip U4 is a dedicated power monitoring / reset chip that generates a stable reset output. The power supply terminal of the second reset chip U4 (such as...) Figure 7 The VDD pins are connected to the power supply and grounded via the filter capacitor C7. The other input of the second reset chip U4 (as shown) is... Figure 7 The CTS shown is grounded through the filter capacitor C6, and the output terminal of the second reset chip U4 (as shown) Figure 7 shown The SENSE signal is connected to the power supply via pull-up resistor R9. The multi-input logic device U5 integrates multiple signals into a single output, merging reset and control signals. One input of the multi-input logic device U5 (e.g., ...) is connected to the power supply via pull-up resistor R9. Figure 7 IN1 (shown) is connected to the power supply through pull-up resistor R8. The power supply terminal of the multi-input logic device U5 is connected to the power supply and grounded through a filter capacitor C8.

[0037] In this embodiment, the reset monitoring module 130 monitors the key input signal and the MCU power-on status. Only when it receives a reset output and a control signal indicating that the central processing unit (CPU) is not powered on will it output a power-off level signal. If the CPU outputs a control signal indicating the power-on status after power-on reset, the reset monitoring module 130 will output a CPU power-on level signal even if it receives a target key input signal. The presence of this power-on level signal will not trigger subsequent circuit control of the CPU to power on.

[0038] In one embodiment, such as Figure 8 As shown, the first logic output module 140 includes a dual D flip-flop U6, a first AND gate U7, a second pull-up resistor, and a third pull-up resistor. Exemplarily, the dual D flip-flop U6 is connected to the first reset module 120 and the reset monitoring module 130. The first input of the first AND gate U7 is connected to both the dual D flip-flop U6 and the second pull-up resistor R12. The second input of the first AND gate U7 is connected to the third pull-up resistor R13. The second pull-up resistor R12 and the third pull-up resistor R13 are connected to the power supply. The input of the dual D flip-flop U6 is also connected to a pull-up resistor R10. The data terminal of the dual D flip-flop U6 (e.g., ...) Figure 8 As shown, D) is grounded, and the clock input of the dual D flip-flop U6 (such as...) Figure 8 shown Connect the power supply.

[0039] In this embodiment, the dual D flip-flop U6 outputs an intermediate logic signal upon receiving a first reset signal and a level signal indicating that the central processing unit is not powered on; the first AND gate U7 outputs a first logic signal upon receiving the intermediate logic signal. This application, by employing the dual D flip-flop U6, achieves the output of an intermediate logic signal controlling the MCU's power-on only when the MCU is not powered on and a key input signal is present. The intermediate logic signal is input to the AND gate, further outputting the first logic signal. The structure of the dual D flip-flop U6 working in conjunction with the AND gate achieves synchronized and latched judgment of the startup conditions, effectively avoiding false triggering problems caused by key bounce, power fluctuations, or signal contention; simultaneously, the introduction of pull-up resistors ensures the level stability of the input pins, improving the reliability and anti-interference capability of the entire power-on reset circuit 100.

[0040] In one embodiment, such as Figure 9 As shown, the second logic output module 150 includes a second AND gate U8 and an OR gate U9. Exemplarily, the inputs of the second AND gate U8 are connected to the power supply chip and the first logic output module 140, respectively, to receive a first-level signal indicating that the power supply chip is not in operation (e.g., ...). Figure 9 The inputs of OR gate U9 are connected to the power management chip and the first logic output module 140, respectively, to receive a second-level signal (e.g., LM5143_PG_R) indicating that the power management chip is not in operation. Figure 9 The second AND gate (EN_3V3_VIO_OR) and the second logic signal are shown. The power supply terminals of the second AND gate U8 and the OR gate U9 are both connected to the power supply and grounded through pull-down resistors. One input terminal of the second AND gate U8 is connected to the voltage divider resistor R18. The output terminals of the second AND gate U8 and the OR gate U9 are both connected to parallel resistors (R14, R15, R16, R17 as shown in the figure).

[0041] In one embodiment, the second AND gate U8 is used to output a second logic signal to the timing control circuit upon receiving a first level signal and a first logic signal, so as to power on the central processing unit in a timely manner. The OR gate U9 is used to output a third logic signal to the power supply circuit upon receiving a second level signal and a first logic signal, so as to power on the power supply terminal of the central processing unit.

[0042] In this embodiment, the second AND gate U8 outputs the second logic signal controlling the timing control circuit only when it receives a first level signal and a first logic signal indicating that the power supply chip is not in operation. If the CPU is powered on and the power supply chip is in operation, the second AND gate U8 will not output the second logic signal controlling the timing control circuit, thus preventing MCU reset. The OR gate U9 is used to output a third logic signal to the power supply circuit when any of the above conditions are met, thereby turning on the power supply to the central processing unit.

[0043] This application also provides a central processing unit (CPU), exemplary of which includes: a timing control circuit, a power supply circuit, and a power-on reset circuit 100 as described in the above embodiment. The power-on reset circuit 100 is connected to both the timing control circuit and the power supply circuit. The power supply circuit provides power to the CPU for the various voltage rails required, and the timing control circuit sequentially activates each power rail of the CPU according to a predetermined order.

[0044] Since this central processing unit uses the power-on reset circuit 100 described above, it possesses all the advantages of the power-on reset circuit 100 described above. It is understood that the options in the above embodiments also apply to this embodiment, and therefore will not be described again here.

[0045] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A power-on reset circuit, characterized in that, include: Key input module, first reset module, reset monitoring module, first logic output module and second logic output module; The key input module is connected to the first reset module and the reset monitoring module respectively. The first reset module and the reset monitoring module are connected to the first logic output module respectively. The first logic output module is connected to the second logic output module. The second logic output module is connected to the timing control circuit and the power supply circuit of the central processing unit respectively. The key input module is used to provide the target key input signal after signal processing; The first reset module is used to output a first reset signal when the target key input signal is received; The reset monitoring module is used to output a level signal indicating that the central processing unit is not powered on when the target key input signal is received. The first logic output module is used to output a first logic signal upon receiving the first reset signal and the level signal; The second logic output module is used to output a second logic signal to the timing control circuit and a third logic signal to the power supply circuit when the first logic signal is received, so as to power on the central processing unit.

2. The power-on reset circuit according to claim 1, characterized in that, Also includes: Central processing unit wake-up module; The central processing unit wake-up module is connected to the key input module; The central processing unit wake-up module is used to wake up the central processing unit in a dormant state upon receiving the target key input signal.

3. The power-on reset circuit according to claim 1, characterized in that, The key input module includes a key, a key debouncing unit, and a Schmitt trigger unit connected in sequence. The button is used to output an initial button input signal; The key debouncing unit is used to filter out interference pulses in the initial key input signal and generate the initial key input signal after debouncing. The Schmitt trigger unit is used to perform hysteresis comparison processing on the initial key input signal after debouncing processing, and output the target key input signal.

4. The power-on reset circuit according to claim 3, characterized in that, The button debouncing unit includes a bidirectional diode, a first filter capacitor, and a first pull-up resistor; the Schmitt trigger unit includes a Schmitt trigger. The button connects to the parallel node of the bidirectional diode and the first filter capacitor. The parallel node of the bidirectional diode and the first filter capacitor is also used to connect the first pull-up resistor and the Schmitt trigger, respectively. The output terminal of the Schmitt trigger is used to connect the first reset module and the reset monitoring module, respectively. Both the bidirectional diode and the first filter capacitor are grounded, and the first pull-up resistor is connected to the power supply.

5. The power-on reset circuit according to claim 2, characterized in that, The central processing unit wake-up module includes a driver and a second pull-up resistor; The input terminal of the driver is connected to the key input module, and the output terminal of the driver is connected to the second pull-up resistor and the central processing unit respectively. The second pull-up resistor is connected to the power supply.

6. The power-on reset circuit according to claim 1, characterized in that, The first reset module includes a first reset chip; The input terminal of the first reset chip is connected to the key input module, and the output terminal of the first reset chip is connected to the first logic output module.

7. The power-on reset circuit according to claim 1, characterized in that, The reset monitoring module includes a second reset chip and a multi-input logic device; The input terminal of the second reset chip is connected to the key input module, and the output terminal of the second reset chip is connected to the input terminal of the multi-input logic device. The input terminals of the multi-input logic device are also used to connect to the central processing unit to receive control signals indicating that the central processing unit is in a power-off state; The second reset chip is used to output a second reset signal when the target key input signal is received; The output terminal of the multi-input logic device is connected to the first logic output module; The multi-input logic device is used to output the level signal when it receives the second reset signal and the control signal.

8. The power-on reset circuit according to claim 1, characterized in that, The first logic output module includes dual D flip-flops, a first AND gate, a second pull-up resistor, and a third pull-up resistor; The dual D flip-flop is connected to the first reset module and the reset monitoring module. The first input terminal of the first AND gate is connected to the dual D flip-flop and the second pull-up resistor, respectively. The second input terminal of the first AND gate is connected to the third pull-up resistor. The second pull-up resistor and the third pull-up resistor are connected to the power supply. The dual D flip-flop is used to output an intermediate logic signal when it receives the first reset signal and a level signal indicating that the central processing unit is not powered on. The first AND gate outputs the first logic signal upon receiving the intermediate logic signal.

9. The power-on reset circuit according to claim 1, characterized in that, The second logic output module includes a second AND gate and an OR gate; The input terminals of the second AND gate are respectively connected to the power chip and the first logic output module to receive a first level signal indicating that the power chip is not in a working state and the first logic signal; The input terminals of the OR gate are respectively connected to the power management chip and the first logic output module to receive a second level signal indicating that the power management chip is not in a working state and the second logic signal; The second AND gate is used to output the second logic signal to the timing control circuit when the first level signal and the first logic signal are received, so as to enable the central processing unit to power on in a timing manner; The OR gate is used to output the third logic signal to the power supply circuit when the second level signal and the first logic signal are received, so as to power on the power supply terminal of the central processing unit.

10. A central processing unit, characterized in that, include: The timing control circuit, the power supply circuit, and the power-on reset circuit as described in any one of claims 1-9, wherein the power-on reset circuit is connected to the timing control circuit and the power supply circuit, respectively.

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