Multi-port switching circuit, circuit board and device

Abstract

The application provides a multi-serial port switching circuit, a circuit board and equipment, relates to the technical field of industrial communication, solves the problems of complex circuit structure and large CPU resource occupation when related technologies are compatible with multiple serial ports, the multi-serial port switching circuit can be connected with different logic signals to adjust the working states of different modules through different signal combinations, realizes the switching of three communication functions, effectively reduces the CPU resource occupation rate, has high circuit reliability, and can also realize the compatibility of the interface through the same output interface, reduces the occupation of the circuit to the equipment shell, and is beneficial to the miniaturization design of the equipment.

Description

Technical Field

[0001] This application relates to the field of industrial communication technology, and in particular to a multi-serial port switching circuit, circuit board and device. Background Technology

[0002] In industrial control, smart meters, and data acquisition, various serial port protocols exist, such as RS232, RS485, and RS422. However, industrial equipment requires the coexistence of these three serial ports to achieve communication for each. This necessitates three sets of TTL (Transistor-Transistor Logic) signals. Furthermore, for RS485 and RS422, if high-baud rate, long-distance, and highly stable communication is required in industrial scenarios, conventional transistors cannot be used to control the transmission and reception directions. At least one additional GPIO (General Purpose Input / Output) is needed as the output port to control the enable state of transmission and reception. Therefore, to ensure compatibility with these three serial ports, related technologies require corresponding GPIO and TTL signals for different enable states, consuming significant CPU resources and complicating the internal circuit structure. This increases costs and hinders device miniaturization. Additionally, setting up corresponding external interfaces for different serial port protocols consumes considerable panel space on the casing. Utility Model Content

[0003] This application provides a multi-serial port switching circuit, circuit board, and device, which solves the problem that the circuit structure is complex and occupies a lot of CPU resources when the related technology is compatible with multiple serial ports. This solution can reduce the CPU resource usage rate, and the simple circuit structure helps to miniaturize the device.

[0004] In a first aspect, this application provides a multi-serial port switching circuit, which is used to connect two GPIO pins of an MCU, and the external transceiver terminal of the multi-serial port switching circuit for sending and receiving data to external devices is provided with an output interface. The multi-serial port switching circuit includes a logic chip module, an RS232 transceiver module, a first RS485 transceiver module and a second RS485 transceiver module.

[0005] The logic chip module has two input terminals connected to two GPIO pins of the MCU to receive the first logic signal and the second logic signal provided by the MCU. The logic chip module is used to perform logic operations on the first logic signal and the second logic signal and output the third logic signal. The enable terminal of the RS232 transceiver module is connected to an input terminal of the logic chip module to receive the first logic signal, and the data transmission terminal of the RS232 transceiver module is connected to a pair of output pins of the output interface. The RS232 transceiver module is used to enable or disable the RS232 transceiver function according to the first logic signal. The first logic control terminal of the first RS485 transceiver module is connected to an input terminal of the logic chip module to receive a first logic signal. The second logic control terminal of the first RS485 transceiver module is connected to an output terminal of the logic chip module to receive a third logic signal. The data transmission terminal of the first RS485 transceiver module is connected to another pair of output pins of the output interface. The first RS485 transceiver module is used to enable or disable the RS485 transceiver function according to the first logic signal and the third logic signal, or to enable or disable the RS422 receiving function according to the first logic signal and the third logic signal. The logic control terminal of the second RS485 transceiver module is connected to another input terminal of the logic chip module to receive the second logic signal. The data transmission terminal of the second RS485 transceiver module is connected to a pair of output pins of the output interface for connection with the data transmission terminal of the RS232 transceiver module. The second RS485 transceiver module is used to enable or disable the RS422 transmission function according to the second logic signal.

[0006] Secondly, this application also provides a circuit board that includes the aforementioned multi-serial port switching circuit.

[0007] Thirdly, this application also provides an electronic device that includes the circuit board described above.

[0008] The multi-serial port switching circuit of this application can switch between three communication functions by connecting different logic signals and adjusting the working state of different modules through different signal combinations. This effectively reduces the CPU resource usage and ensures high circuit reliability. Furthermore, it can achieve interface compatibility through the same output interface, reducing the circuit's footprint on the device casing and facilitating miniaturization of the device. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a multi-serial port switching circuit provided in one embodiment of this application.

[0010] Figure 2 This is a schematic diagram of the circuit structure of an RS232 transceiver module provided in an embodiment of this application.

[0011] Figure 3 A schematic diagram of the circuit structure of a first RS485 transceiver module provided in an embodiment of this application.

[0012] Figure 4 This is a schematic diagram of the structure of a second RS485 transceiver module provided in an embodiment of this application. Detailed Implementation

[0013] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of the present application and are not intended to limit the scope of the present application. Furthermore, it should be noted that, for ease of description, the accompanying drawings only show the parts relevant to the embodiments of the present application, and not all structures. Those skilled in the art, after reading this specification, should be able to deduce that any combination of technical features can constitute an optional implementation method, provided that the technical features do not contradict each other.

[0014] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, not limited in number; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship. In the description of this application, "multiple" means two or more, and "several" means one or more.

[0015] In related technologies, to achieve coexistence of multiple serial port protocols within a device, corresponding GPIO and TTL signals are provided for the different enable states required by RS232, RS485, and RS422. This consumes a significant amount of CPU resources, complicates the internal circuit structure, increases costs, and hinders device miniaturization. Furthermore, setting up corresponding external interfaces for different serial port protocols results in numerous external interfaces occupying panel space on the casing. To address this, this application provides a multi-serial port switching circuit, such as... Figure 1 As shown, Figure 1 This is a block diagram of a multi-serial port switching circuit provided in an embodiment of this application. The multi-serial port switching circuit of this solution is compatible with data transmission of different serial port protocols through the same output interface, and adjusts the working state of different modules through logic signals, thereby realizing the switching of different serial port functions.

[0016] The multi-serial port switching circuit connects to two GPIO pins of the MCU, and its external transceiver interface for sending and receiving data from external devices is provided, as shown in the reference. Figure 1The multi-serial port switching circuit includes a logic chip module 110, an RS232 transceiver module 120, a first RS485 transceiver module 130, and a second RS485 transceiver module 140. Specifically, the two input terminals of the logic chip module 110 are respectively connected to two GPIO pins of the MCU to receive the first logic signal and the second logic signal provided by the MCU. The enable terminal of the RS232 transceiver module 120 is connected to one input terminal of the logic chip module 110 to receive the first logic signal, and the data transmission terminal of the RS232 transceiver module 120 is connected to a pair of output pins of the output interface. The first logic control terminal of the first RS485 transceiver module 130 is connected to one input terminal of the logic chip module 110 to receive the first logic signal, the second logic control terminal of the first RS485 transceiver module 130 is connected to the output terminal of the logic chip module 110 to receive the third logic signal, and the data transmission terminal of the first RS485 transceiver module 130 is connected to another pair of output pins of the output interface. The logic control terminal of the second RS485 transceiver module 140 is connected to another input terminal of the logic chip module 110 to access the second logic signal, and the data transmission terminal of the second RS485 transceiver module 140 is connected to a pair of output pins of the output interface for connection with the data transmission terminal of the RS232 transceiver module 120.

[0017] The logic chip module 110 is used to perform logical operations on the first logic signal and the second logic signal and output a third logic signal. The RS232 transceiver module 120 is used to enable or disable the RS232 transceiver function according to the first logic signal. The first RS485 transceiver module 130 is used to enable or disable the RS485 transceiver function according to the first logic signal and the third logic signal, or to enable or disable the RS422 receiving function according to the first logic signal and the third logic signal. The second RS485 transceiver module 140 is used to enable or disable the RS422 transmitting function according to the second logic signal. It is understandable that the MCU outputs a first logic signal and a second logic signal, which are then used by the logic chip module 110 in the circuit to generate a third logic signal through logical operations. Furthermore, the first, second, and third logic signals can form multiple signal combinations to correspond to different serial port functions. For example, when implementing RS232 transceiver functionality, the first and second logic signals from one signal combination output by the MCU are sufficient. When implementing RS485 transceiver functionality, the first and third logic signals from another signal combination output by the MCU are sufficient. When implementing RS422 transmission and reception functionality, the first RS485 transceiver module 130 and the second RS485 transceiver module 140 need to perform different functions. For instance, the first RS485 transceiver module 130 implements the RS422 reception function, and the second RS485 transceiver module 140 implements the RS422 transmission function. The first, second, and third logic signals from another signal combination output by the MCU control the first RS485 transceiver module 130 and the second RS485 transceiver module 140 respectively.

[0018] Therefore, it can be seen that the multi-serial port switching circuit of this solution can switch between three communication functions by connecting different logic signals and adjusting the working state of different modules through different signal combinations. This effectively reduces the CPU resource usage, and the circuit has high reliability. Moreover, it can achieve interface compatibility through the same output interface, reducing the circuit's footprint on the device casing and facilitating the miniaturization of the device.

[0019] Optionally, the output interface is a DB9 interface. The first pin of the DB9 interface (pin1 in the table below) is used as the positive pin for implementing the RS422 receiving function (i.e., RS422_RX+) or the first data pin for implementing the RS485 transceiver function (i.e., RS4285_DATA+). The second pin of the DB9 interface (pin2 in the table below) is used as the negative pin for implementing the RS232 receiving function (i.e., RS232_RXD) or the RS422 transmitting function (i.e., RS422_TX-). The third pin of the DB9 interface (pin3 in the table below) is used as the positive pin for implementing the RS232 transmitting function (i.e., RS232_TXD) or the RS422 transmitting function (i.e., RS422_TX+). The fourth pin of the DB9 interface (pin4 in the table below) is used as the negative pin for implementing the RS422 receiving function (i.e., RS422_RX-) or the second data pin for implementing the RS485 transceiver function (i.e., RS485_DATA-). The pinout definitions for some output pins of the DB9 interface are shown in the table below:

[0020] To address this, the data transmission terminals of the RS232 transceiver module are connected to pins 2 and 3 of the DB9 interface; the data transmission terminals of the first RS485 transceiver module are connected to pins 1 and 4 of the DB9 interface; and the data transmission terminals of the second RS485 transceiver module are connected to pins 2 and 3 of the DB9 interface. This multi-serial port switching circuit utilizes the DB9 interface, which is compatible with multiple serial port protocols, to serve as the data transmission and reception interface. This reduces the footprint on the device's outer panel and contributes to device miniaturization.

[0021] Optionally, the logic chip module includes an XOR gate chip, which is used to perform an XOR operation on the first logic signal and the second logic signal. The truth table of the XOR gate chip is as follows:

[0022] In the process of performing an XOR operation on the first logic signal (A in the table below) and the second logic signal (B in the table below), if both the first logic signal and the second logic signal are low-level signals (L) or both are high-level signals (H), then the third logic signal obtained after the XOR operation is a low-level signal (L); if the first logic signal and the second logic signal correspond to a low-level signal (L) and a high-level signal (H) respectively, such as the input case where the first logic signal is a low-level signal (L) and the second logic signal is a high-level signal (H) or another input case where the first logic signal is a high-level signal (H) and the second logic signal is a low-level signal (L), then the third logic signal obtained after the XOR operation is a high-level signal (H).

[0023] Figure 2 The circuit structure diagram of an RS232 transceiver module provided in one embodiment of this application is shown in the figure. In one embodiment, the RS232 transceiver module includes an RS232 transceiver chip U1, a first resistor R1, a second resistor R2, and an NPN transistor Q1. The enable pin of the RS232 transceiver chip U1 serves as the enable terminal of the RS232 transceiver module and is connected to a first logic signal (GPIO_A in the figure). The enable pin of the RS232 transceiver chip U1 is also connected to the first end of the first resistor R1. The second end of the first resistor R1 is connected to the base terminal of the NPN transistor Q1. The emitter terminal of the NPN transistor Q1 is grounded. The collector terminal of the NPN transistor Q1 is connected to the first end of the second resistor R2. The second end of the second resistor R2 is connected to the operating voltage. The power-off control input pin of the RS232 transceiver chip U1 is connected to the first end of the second resistor R2. Understandably, when the first logic signal is low, the NPN transistor Q1 does not meet the conduction condition due to the low-level first logic signal. Consequently, the power-off control input pin of the RS232 transceiver chip U1 is connected to the operating voltage through the second resistor R2, meaning the power-off control input pin of the RS232 transceiver chip U1 is high. Furthermore, the enable pin of the RS232 transceiver chip U1 is also connected to the low-level first logic signal, thus putting the RS232 transceiver chip U1 into operation and enabling the RS232 transceiver function.

[0024] Figure 3The circuit structure diagram of the first RS485 transceiver module provided in one embodiment of this application is shown in the figure. In one embodiment, the first RS485 transceiver module includes a first RS485 transceiver chip U2, a first logic controller U3, a second logic controller U4, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a first capacitor C1. The enable input pin of the first logic controller U3 is connected to an input terminal of the logic chip module to receive a first logic signal (GPIO_A in the figure). The input pin of the first logic controller U3 is connected to the output pin of the first RS485 transceiver chip U2, and the output pin of the first logic controller U3 serves as the output terminal of the first RS485 transceiver module. The enable input pin of the second logic controller U4 is connected to the output terminal of the logic chip module to receive a third logic signal (Out_Y in the figure). The input pin of the second logic controller U4 serves as the input terminal of the first RS485 transceiver module, and the output pin of the second logic controller U4 is connected to the input pin of the first RS485 transceiver chip U2. The input pins of the first RS485 transceiver chip U2 are also connected to the first end of the third resistor R3. The second end of the third resistor R3 is connected to the operating voltage. The receiver enable pin and the shutdown enable pin of the first RS485 transceiver chip U2 are both connected to the first end of the fourth resistor R4. The second end of the fourth resistor R4 is connected to the operating voltage, and the second end of the fourth resistor R4 is also connected to the grounded first capacitor C1. The two data input / output pins of the first RS485 transceiver chip U2 are respectively connected to the first ends of the fifth resistor R5 and the sixth resistor R6. The first end of the fifth resistor R5 is connected to the grounded seventh resistor R7, and the first end of the sixth resistor R6 is connected to the eighth resistor R8 connected to the operating voltage. The second ends of the fifth resistor R5 and the second ends of the sixth resistor R6 both serve as the data transmission ends of the first RS485 transceiver module.

[0025] It is understandable that the operating states of the first logic controller U3 and the second logic controller U4 are controlled based on the received logic signals. The first logic controller U3 is used to control the data reception of the first RS485 transceiver module, while the second logic controller U4 is used to control the data transmission of the first RS485 transceiver module. For example, when both the enable input pins of the first logic controller U3 and the second logic controller U4 are active high, when a signal combination including a high-level first logic signal and a high-level third logic signal is received, a conduction channel can be formed between the input and output pins of the first logic controller U3, and similarly, a conduction channel can be formed between the input and output pins of the second logic controller U4. This means that both data reception and data transmission of the first RS485 transceiver module can be achieved. Furthermore, the receiver enable pin and shutdown enable pin of the first RS485 transceiver chip U2 are connected to the operating voltage through the fourth resistor R4. That is, the receiver enable pin of the first RS485 transceiver chip U2 is in a high-level state, enabling the first RS485 transceiver chip U2 to transmit and receive data; that is, the two data input / output pins of the first RS485 transceiver chip U2 can receive or send data. Therefore, it can be seen that the first RS485 transceiver module can achieve RS485 transmission and reception functions through corresponding signal combinations. It is conceivable that if the third logic signal is a low-level signal, the second logic controller U4 will not operate, preventing the first RS485 transceiver module from transmitting data.

[0026] In addition, the data transmission terminal of the first RS485 transceiver module is connected to the output interface to transmit data sent to or received from external devices. The input and output terminals of the first RS485 transceiver module are used for internal connections, such as connecting to MCUs, memory, and other modules, to transmit received data to or receive data from other modules and send it back to them. The seventh resistor R7 acts as a pull-down resistor, and the eighth resistor R8 acts as a pull-up resistor to meet the multi-node and long-distance communication requirements of the RS485 transceiver function.

[0027] Therefore, this solution sets up different logic controllers to control the data reception and data transmission of the first RS485 transceiver module, so that the transmission and reception can be controlled after different logic signals are connected, thereby adapting to the communication function to be switched, and the communication function switching is reliable, stable and efficient.

[0028] Figure 4Figure U shows a schematic diagram of the structure of a second RS485 transceiver module provided in one embodiment of this application. In one embodiment, the second RS485 transceiver module includes a second RS485 transceiver chip U5, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a second capacitor C2, a first resistor access unit 141, and a second resistor access unit 142. Specifically, the shutdown enable pin of the second RS485 transceiver chip U5 is connected to another input terminal of the logic chip module to access a second logic signal (GPIO_B in the figure). The receiver enable pin of the second RS485 transceiver chip U5 is connected to the first terminal of the ninth resistor R9. The second terminal of the ninth resistor R9 is connected to the operating voltage, and the second terminal of the ninth resistor R9 is also connected to the grounded second capacitor C2. The two data input / output pins of the second RS485 transceiver chip U5 are respectively connected to the first terminals of the tenth resistor R10 and the eleventh resistor R11. The second terminals of the tenth resistor R10 and the eleventh resistor R11 both serve as data transmission terminals of the second RS485 transceiver module.

[0029] The first end of the tenth resistor R10 is connected to the first resistor access unit 141. The control terminal of the first resistor access unit 141 is connected to an input terminal of the logic chip module to receive the first logic signal. The first resistor access unit 141 is used to provide a first grounding loop when implementing the RS422 transmission function. The first end of the eleventh resistor R11 is connected to the second resistor access unit 142. The control terminal of the second resistor access unit 142 is connected to an input terminal of the logic chip module to receive the first logic signal. The second resistor access unit 142 is used to provide a second loop for receiving the operating voltage when implementing the RS422 transmission function.

[0030] It is conceivable that the second RS485 transceiver chip U5 is controlled by a second logic signal; when the second logic signal is high, the second RS485 transceiver chip U5 operates. Furthermore, to achieve RS422 transmission and reception functions, the first and second RS485 transceiver modules operate simultaneously, with the first RS485 transceiver module implementing RS422 reception and the second RS485 transceiver module implementing RS422 transmission. Moreover, both the first resistor access unit 141 and the second resistor access unit 142 are connected to the first logic signal, providing a first grounding loop and a second loop for the operating voltage to the second RS485 transceiver module based on the signal level of the connected first logic signal, thus enabling the second RS485 transceiver module to achieve RS422 transmission. Therefore, by connecting a signal combination including both a high-level first logic signal and a high-level second logic signal, the second RS485 transceiver module can achieve RS422 reception. Therefore, this solution controls the second RS485 transceiver module to complete the RS422 receiving function by controlling the second RS485 transceiver chip. The circuit structure is simple and the communication function switching is reliable, stable and efficient.

[0031] Optionally, the first resistor access unit 141 includes a twelfth resistor R12 and a first NMOS transistor Q2. Specifically, the first end of the twelfth resistor R12 is connected to the first end of the tenth resistor R10, the second end of the twelfth resistor R12 is connected to the drain terminal of the first NMOS transistor Q2, the source terminal of the first NMOS transistor Q2 is grounded, and the gate terminal of the first NMOS transistor Q2 is used to access the first logic signal. It can be understood that the first NMOS transistor Q2 is used to control the twelfth resistor R12 to be grounded. When a high-level signal is applied to the gate terminal of the first NMOS transistor Q2, the first NMOS transistor Q2 meets the conduction condition, thereby grounding the twelfth resistor R12 connected to the drain terminal of the first NMOS transistor Q2. Therefore, when the second RS485 transceiver module implements the RS422 transmission function, the first logic signal is a high-level signal and the second logic signal is a high-level signal, so that the grounded twelfth resistor R12 is connected to the signal line at the data transmission end of the second RS485 transceiver module. By controlling the logic signals, this solution can provide pull-up and pull-down resistors when switching RS422 transceiver functions is required, thereby effectively meeting communication needs.

[0032] Optionally, the second resistor access unit 142 includes a second NMOS transistor Q3, a first PMOS transistor Q4, a thirteenth resistor R13, and a fourteenth resistor R14. Specifically, the gate of the second NMOS transistor Q3 is used to access the first logic signal, the source of the second NMOS transistor Q3 is grounded, the drain of the second NMOS transistor Q3 is connected to the first terminal of the thirteenth resistor R13, and the second terminal of the thirteenth resistor R13 is connected to the operating voltage. The gate of the first PMOS transistor Q4 is connected to the drain of the second NMOS transistor Q3, the source of the first PMOS transistor Q4 is connected to the first terminal of the fourteenth resistor R14, the second terminal of the fourteenth resistor R14 is connected to the operating voltage, and the drain of the first PMOS transistor Q4 is connected to the first terminal of the eleventh resistor R11.

[0033] Understandably, when no high-level signal is applied to the gate of the second NMOS transistor Q3, Q3 is not turned on. In this case, the gate of the first PMOS transistor Q4 is connected to the operating voltage through the thirteenth resistor R13, meaning the gate of the first PMOS transistor Q4 is at a high level, and Q4 does not meet the turn-on condition. However, when a high-level signal is applied to the gate of the second NMOS transistor Q3, Q3 turns on, pulling its drain voltage low. This means the gate of the first PMOS transistor Q4 is at a low level. Since the drain of the first PMOS transistor Q4 is connected to the operating voltage through the fourteenth resistor R14, Q4 meets the turn-on condition. This provides a second loop for the second RS485 transceiver module to access the operating voltage, allowing the fourteenth resistor R14 to be connected to the signal line at the data transmission end of the second RS485 transceiver module. By controlling the logic signals, this solution can provide pull-up and pull-down resistors when switching RS422 transceiver functions is required, thereby effectively meeting communication needs.

[0034] Reference Figure 1 , Figure 2 , Figure 3 and Figure 4 The multi-serial port switching circuit includes a logic chip module 110, an RS232 transceiver module 120, a first RS485 transceiver module 130, and a second RS485 transceiver module 140. Specifically, the logic chip module 110 includes an XOR gate chip, which is a dual-input single-output chip. That is, by inputting two logic signals (such as a first logic signal and a second logic signal) and performing an XOR operation, it outputs another logic signal (such as a third logic signal). Furthermore, when the first logic signal and the second logic signal are the same, the third logic signal is a low-level signal; when the first logic signal and the second logic signal are different, the third logic signal is a high-level signal.

[0035] In the RS232 transceiver module 120, the enable pin of the RS232 transceiver chip U1 serves as the enable terminal of the RS232 transceiver module 120. The enable pin of the RS232 transceiver chip U1 is also connected to the first end of the first resistor R1. The second end of the first resistor R1 is connected to the base terminal of the NPN transistor Q1. The emitter terminal of the NPN transistor Q1 is grounded. The collector terminal of the NPN transistor Q1 is connected to the first end of the second resistor R2. The second end of the second resistor R2 is connected to the operating voltage. The power-off control input pin of the RS232 transceiver chip U1 is connected to the first end of the second resistor R2.

[0036] In the first RS485 transceiver module 130, the enable input pin of the first logic controller U3 is connected to an input terminal of the logic chip module 110 to receive a first logic signal. The input pin of the first logic controller U3 is connected to the output pin of the first RS485 transceiver chip U2, and the output pin of the first logic controller U3 serves as the output terminal of the first RS485 transceiver module 130. The enable input pin of the second logic controller U4 is connected to the output terminal of the logic chip module 110 to receive a third logic signal. The input pin of the second logic controller U4 serves as the input terminal of the first RS485 transceiver module 130, and the output pin of the second logic controller U4 is connected to the input pin of the first RS485 transceiver chip U2. The input pin of the first RS485 transceiver chip U2 is also connected to the first terminal of the third resistor R3, and the second terminal of the third resistor R3 is connected to the operating voltage. The receiver enable pin and the shutdown enable pin of the first RS485 transceiver chip U2 are both connected to the first terminal of the fourth resistor R4, and the second terminal of the fourth resistor R4 is connected to the operating voltage. The second terminal of the fourth resistor R4 is also connected to the grounded first capacitor C1. The two data input / output pins of the first RS485 transceiver chip U2 are connected to the first end of the fifth resistor R5 and the first end of the sixth resistor R6, respectively. The first end of the fifth resistor R5 is connected to the grounded seventh resistor R7, and the first end of the sixth resistor R6 is connected to the eighth resistor R8 which is connected to the working voltage. The second ends of the fifth resistor R5 and the second ends of the sixth resistor R6 are both used as data transmission ends of the first RS485 transceiver module 130.

[0037] In the second RS485 transceiver module 140, the shutdown enable pin of the second RS485 transceiver chip U5 is connected to another input terminal of the logic chip module 110 to receive the second logic signal. The receiver enable pin of the second RS485 transceiver chip U5 is connected to the first terminal of the ninth resistor R9. The second terminal of the ninth resistor R9 is connected to the operating voltage, and the second terminal of the ninth resistor R9 is also connected to the grounded second capacitor C2. The two data input / output pins of the second RS485 transceiver chip U5 are respectively connected to the first terminals of the tenth resistor R10 and the eleventh resistor R11. The second terminals of the tenth resistor R10 and the eleventh resistor R11 both serve as data transmission terminals of the second RS485 transceiver module 140. The first terminal of the twelfth resistor R12 is connected to the first terminal of the tenth resistor R10, and the second terminal of the twelfth resistor R12 is connected to the drain terminal of the first NMOS transistor Q2. The source terminal of the first NMOS transistor Q2 is grounded, and the gate terminal of the first NMOS transistor Q2 is used to receive the first logic signal. The gate of the second NMOS transistor Q3 is used to receive the first logic signal. The source of the second NMOS transistor Q3 is grounded, and the drain of the second NMOS transistor Q3 is connected to the first terminal of the thirteenth resistor R13. The second terminal of the thirteenth resistor R13 is connected to the operating voltage. The gate of the first PMOS transistor Q4 is connected to the drain of the second NMOS transistor Q3. The source of the first PMOS transistor Q4 is connected to the first terminal of the fourteenth resistor R14. The second terminal of the fourteenth resistor R14 is connected to the operating voltage, and the drain of the first PMOS transistor Q4 is connected to the first terminal of the eleventh resistor R11.

[0038] Four signal combinations can be determined from the first, second, and third logic signals. The first signal combination, where the first, second, and third logic signals are all low, is used to implement RS232 transceiver functionality in the multi-serial port switching circuit. The second signal combination, where the first, second, and third logic signals are all high, is used to implement RS422 transceiver functionality in the multi-serial port switching circuit. Finally, the third signal combination, where the first, second, and third logic signals are all high, is used to implement RS485 transceiver functionality in the multi-serial port switching circuit.

[0039] Therefore, under the control of the first signal combination, the enable pin of RS232 transceiver chip U1, the enable input pin of the first logic controller U3, the enable input pin of the second logic controller U4, the receiver enable pin of the second RS485 transceiver chip U5, the first NMOS transistor Q2, and the second NMOS transistor Q3 are all connected to low-level signals. At this time, RS232 transceiver chip U1 is in the working state, while the first logic controller U3, the second logic controller U4, and the second RS485 transceiver chip U5 are not working, and the first NMOS transistor Q2 and the second NMOS transistor Q3 do not meet the conduction condition. Therefore, under the first signal combination, RS232 transceiver module 120 is working, while the first RS485 transceiver module 130 and the second RS485 transceiver module 140 are not working. Furthermore, in this scheme, the RS232 and RS422 transceiver functions share the same output pins. The low level of the first logic signal keeps both the first NMOS transistor Q2 and the second NMOS transistor Q3 in a non-conducting state. Therefore, no pull-up or pull-down resistors are connected to the signal lines of the RS232 transceiver function, and the overall communication level of the RS232 transceiver function will not be affected.

[0040] Under the control of the second signal combination, the enable pin of RS232 transceiver chip U1, the enable input pin of the first logic controller U3, the receiver enable pin of the second RS485 transceiver chip U5, the first NMOS transistor Q2, and the second NMOS transistor Q3 are all connected to a high-level signal, while the enable input pin of the second logic controller U4 is connected to a low-level signal. At this time, neither RS232 transceiver chip U1 nor the second logic controller U4 is in operation, while both the first logic controller U3 and the second RS485 transceiver chip U5 are in operation. Since the second logic controller U4 controls the transmission channel of the first RS485 transceiver module 130, the RS232 transceiver module 120 is not in operation. Although the first RS485 transceiver chip U2 is in operation, it only provides data reception, enabling the first RS485 transceiver module 130 to implement RS422 reception. Furthermore, the second RS485 chip being in operation enables the second RS485 transceiver module 140 to implement RS422 transmission. Furthermore, since the first logic signal is a high-level signal, both the first NMOS transistor Q2 and the second NMOS transistor Q3 are in the conducting state. Therefore, pull-up resistors and pull-down resistors can be connected to the signal lines corresponding to the RS422 transmitting and receiving functions to meet the multi-node and long-distance communication requirements of the RS422 transceiver function.

[0041] Under the control of the third signal combination, the enable pin of RS232 transceiver chip U1, the enable input pin of the first logic controller U3, the enable input pin of the second logic controller U4, the first NMOS transistor Q2, and the second NMOS transistor Q3 are all connected to a high-level signal, while the receiver enable pin of the second RS485 transceiver chip U5 is connected to a low-level signal. At this time, neither RS232 transceiver chip U1 nor the second RS485 transceiver chip U5 works, while both the first logic controller U3 and the second logic controller U4 work and provide data transmission and reception channels for the second RS485 transceiver chip U5, so that the second RS485 transceiver module 140 can realize the RS485 transceiver function. Furthermore, the pull-up resistors and pull-down resistors corresponding to the RS485 transceiver function can be connected to meet the multi-node and long-distance communication requirements of the RS485 transceiver function.

[0042] This application embodiment also provides a circuit board, which includes the multi-serial port switching circuit provided in the above embodiment. The multi-serial port switching circuit on the circuit board can adjust the working state of different modules by connecting different logic signals and adjusting the signal combination to achieve switching of three communication functions. This effectively reduces the CPU resource usage and the circuit has high reliability. Moreover, it can achieve interface compatibility through the same output interface, reducing the circuit's footprint on the device casing and facilitating the miniaturization of the device.

[0043] This application also provides an electronic device including the circuit board described above. By integrating the output interface, the interface occupies a smaller area on the casing of the electronic device. Moreover, the circuit structure on the circuit board is simple, highly reliable, and can quickly and effectively switch between different communication functions, so that the device can be compatible with RS232, RS485, and RS422 serial port protocols without complex internal circuit design.

[0044] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0045] Note that the above description is merely a preferred embodiment and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of this application, and the scope of this application is determined by the scope of the appended claims.

Claims

1. A multi-serial port switching circuit, characterized in that, The multi-serial port switching circuit is used to connect two GPIO pins of the MCU, and the external transceiver terminal of the multi-serial port switching circuit for sending and receiving data to external devices is provided with an output interface. The multi-serial port switching circuit includes: A logic chip module, wherein the two input terminals of the logic chip module are respectively connected to the two GPIO pins of the MCU to receive the first logic signal and the second logic signal provided by the MCU, and the logic chip module is used to perform logical operations on the first logic signal and the second logic signal and output a third logic signal; The RS232 transceiver module has its enable terminal connected to an input terminal of the logic chip module to receive the first logic signal, and its data transmission terminal connected to a pair of output pins of the output interface. The RS232 transceiver module is used to enable or disable the RS232 transceiver function according to the first logic signal. The first RS485 transceiver module has a first logic control terminal connected to an input terminal of the logic chip module to receive the first logic signal, a second logic control terminal connected to an output terminal of the logic chip module to receive the third logic signal, and a data transmission terminal connected to another pair of output pins of the output interface. The first RS485 transceiver module is used to enable or disable the RS485 transceiver function or the RS422 receiving function according to the first logic signal and the third logic signal. The second RS485 transceiver module has its logic control terminal connected to another input terminal of the logic chip module to receive the second logic signal. The data transmission terminal of the second RS485 transceiver module is connected to a pair of output pins of the output interface for connection with the data transmission terminal of the RS232 transceiver module. The second RS485 transceiver module is used to enable or disable the RS422 transmission function according to the second logic signal.

2. The multi-serial port switching circuit according to claim 1, characterized in that, The RS232 transceiver module includes an RS232 transceiver chip, a first resistor, a second resistor, and an NPN transistor; The enable pin of the RS232 transceiver chip serves as the enable terminal of the RS232 transceiver module. The enable pin of the RS232 transceiver chip is also connected to the first end of the first resistor. The second end of the first resistor is connected to the base terminal of the NPN transistor. The emitter terminal of the NPN transistor is grounded. The collector terminal of the NPN transistor is connected to the first end of the second resistor. The second end of the second resistor is connected to the operating voltage. The power-off control input pin of the RS232 transceiver chip is connected to the first end of the second resistor.

3. The multi-serial port switching circuit according to claim 1, characterized in that, The first RS485 transceiver module includes a first RS485 transceiver chip, a first logic controller, a second logic controller, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a first capacitor; The enable input pin of the first logic controller is connected to an input terminal of the logic chip module to receive the first logic signal. The input pin of the first logic controller is connected to the output pin of the first RS485 transceiver chip. The output pin of the first logic controller serves as the output terminal of the first RS485 transceiver module. The enable input pin of the second logic controller is connected to the output terminal of the logic chip module to access the third logic signal. The input pin of the second logic controller serves as the input terminal of the first RS485 transceiver module, and the output pin of the second logic controller is connected to the input pin of the first RS485 transceiver chip. The input pin of the first RS485 transceiver chip is also connected to the first end of the third resistor, the second end of the third resistor is connected to the operating voltage, the receiver enable pin and the shutdown enable pin of the first RS485 transceiver chip are both connected to the first end of the fourth resistor, the second end of the fourth resistor is connected to the operating voltage, and the second end of the fourth resistor is also connected to the grounded first capacitor. The two data input / output pins of the first RS485 transceiver chip are respectively connected to the first end of the fifth resistor and the first end of the sixth resistor. The first end of the fifth resistor is connected to the grounded seventh resistor, and the first end of the sixth resistor is connected to the eighth resistor connected to the working voltage. The second ends of the fifth resistor and the second ends of the sixth resistor both serve as the data transmission ends of the first RS485 transceiver module.

4. The multi-serial port switching circuit according to claim 1, characterized in that, The second RS485 transceiver module includes a second RS485 transceiver chip, a ninth resistor, a tenth resistor, an eleventh resistor, a second capacitor, a first resistor access unit, and a second resistor access unit. The shutdown enable pin of the second RS485 transceiver chip is connected to another input terminal of the logic chip module to access the second logic signal. The receiver enable pin of the second RS485 transceiver chip is connected to the first terminal of the ninth resistor. The second terminal of the ninth resistor is connected to the operating voltage, and the second terminal of the ninth resistor is also connected to the grounded second capacitor. The two data input / output pins of the second RS485 transceiver chip are respectively connected to the first end of the tenth resistor and the first end of the eleventh resistor. The second end of the tenth resistor and the second end of the eleventh resistor both serve as the data transmission ends of the second RS485 transceiver module. The first end of the tenth resistor is connected to the first resistor access unit, and the control end of the first resistor access unit is connected to an input end of the logic chip module to access the first logic signal. The first resistor access unit is used to provide a first grounding loop when implementing the RS422 transmission function. The first end of the eleventh resistor is connected to the second resistor access unit, and the control end of the second resistor access unit is connected to an input end of the logic chip module to access the first logic signal. The second resistor access unit is used to provide a second circuit for accessing the working voltage when implementing the RS422 transmission function.

5. The multi-serial port switching circuit according to claim 4, characterized in that, The first resistor access unit includes a twelfth resistor and a first NMOS transistor. The first end of the twelfth resistor is connected to the first end of the tenth resistor, the second end of the twelfth resistor is connected to the drain terminal of the first NMOS transistor, the source terminal of the first NMOS transistor is grounded, and the gate terminal of the first NMOS transistor is used to access the first logic signal.

6. The multi-serial port switching circuit according to claim 4 or 5, characterized in that, The second resistor access unit includes a second NMOS transistor, a first PMOS transistor, a thirteenth resistor, and a fourteenth resistor; The gate terminal of the second NMOS transistor is used to connect to the first logic signal, the source terminal of the second NMOS transistor is grounded, the drain terminal of the second NMOS transistor is connected to the first terminal of the thirteenth resistor, and the second terminal of the thirteenth resistor is connected to the operating voltage. The gate of the first PMOS transistor is connected to the drain of the second NMOS transistor, the source of the first PMOS transistor is connected to the first terminal of the fourteenth resistor, the second terminal of the fourteenth resistor is connected to the operating voltage, and the drain of the first PMOS transistor is connected to the first terminal of the eleventh resistor.

7. The multi-serial port switching circuit according to claim 1, characterized in that, The logic chip module includes an XOR gate chip, which is used to perform an XOR operation on the first logic signal and the second logic signal.

8. The multi-serial port switching circuit according to claim 1, characterized in that, The output interface is a DB9 interface. The first pin of the DB9 interface is used as the positive pin for implementing RS422 reception or the first data pin for implementing RS485 transceiver function. The second pin of the DB9 interface is used as the negative pin for implementing RS232 reception or RS422 transmission. The third pin of the DB9 interface is used as the positive pin for implementing RS232 transmission or RS422 transmission. The fourth pin of the DB9 interface is used as the negative pin for implementing RS422 reception or the second data pin for implementing RS485 transceiver function. The data transmission terminal of the RS232 transceiver module is connected to the second and third pins of the DB9 interface, the data transmission terminal of the first RS485 transceiver module is connected to the first and fourth pins of the DB9 interface, and the data transmission terminal of the second RS485 transceiver module is connected to the second and third pins of the DB9 interface.

9. A circuit board, characterized in that, Includes a multi-serial port switching circuit as described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes the multi-serial port switching circuit as described in claim 9.

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