Chip package structure

CN224890141UActive Publication Date: 2026-10-23SHENZHEN DEMINGLI OPTOELECTRONICS CO LTD
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Patent Information

Application Number
CN202521747625.4
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2025-08-18
Publication Date
2026-10-23
Estimated Expiration
2035-08-18

AI Technical Summary

Technical Problem

[0002]VCSEL(Vertical-Cavity Surface-Emitting Laser,垂直腔面发射激光器)芯片通常通过金线与PCB焊盘连接,在运输过程中或跌落时,因机械振动等原因,容易出现焊点、金线断裂的问题,尤其在手机等便携设备中,出现焊点、金线断裂的几率更大,相关技术中,为了解决因机械振动导致的焊点断裂问题,可以使用硅胶进行填充加固,但该方式需要额外增加新的工艺过程,导致会增加约20%的生产成本,综上,在控制生产成本情况下,相关技术缺乏针对因机械振动等原因导致的焊点、金线断裂问题的有效解决方案

Benefits of technology

[0014]本实用新型提供的芯片封装结构,包括:芯片、芯片焊接在PCB板上,PCB板上设置有至少一个PCB焊盘;针对每个PCB焊盘,在该PCB焊盘与芯片之间的PCB板区域内刻蚀有支撑柱;该PCB焊盘与芯片之间通过焊线连接,焊线跨越支撑柱,支撑柱的高度与焊线的拱高相关联;该PCB焊盘的侧边与支撑柱的侧边之间的距离大于或等于焊线的直径的第一预设倍数;该芯片封装结构中,在PCB焊盘与芯片之间的PCB板区域内刻蚀有支撑柱,由于支撑柱可以与PCB板同步刻蚀得到,因此,不需要额外增加新的工艺过程,从而可以有效控制生产成本;并且,PCB焊盘与芯片之间的焊线会跨越支撑柱,可以根据焊线的拱高和PCB焊盘的位置,设置合适的支撑柱的高度和位置,当发生机械振动等情况时,可以通过该支撑柱支撑焊线,从而有效减少焊点、焊线断裂问题。

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Abstract

The utility model provides a kind of chip packaging structure, chip is welded on the PCB board of at least one PCB pad;The PCB board area between each PCB pad and chip is etched support column;The solder wire between PCB pad and chip spans support column, its height is related with solder wire arch height;The side distance of PCB pad and support column is greater than or equal to the first preset multiple of solder wire diameter;In the structure, support column is etched in the PCB board area between PCB pad and chip, since support column can be etched synchronously with PCB board, thus, it is not necessary to additionally increase new technological process, so as to effectively control production cost;And, solder wire between PCB pad and chip will span support column, can set the height and position of appropriate support column according to the arch height of solder wire and the position of PCB pad, when mechanical vibration etc. occur, solder wire can be supported by the support column, so as to effectively reduce the problem of solder joint, solder wire fracture.
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Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure. Background Technology

[0002] VCSEL (Vertical-Cavity Surface-Emitting Laser) chips are typically connected to PCB pads via gold wires. During transportation or drops, mechanical vibrations can easily cause solder joints and gold wires to break, especially in portable devices such as mobile phones. While silicone can be used to reinforce solder joints caused by mechanical vibrations, this requires additional processing steps, increasing production costs by approximately 20%. Therefore, while controlling production costs is important, there is currently a lack of effective solutions for solder joint and gold wire breakage caused by mechanical vibrations. Utility Model Content

[0003] The purpose of this invention is to provide a chip packaging structure that reduces the problem of solder joint and wire breakage caused by mechanical vibration and other reasons while controlling production costs.

[0004] This utility model provides a chip packaging structure, including: a chip, the chip being soldered onto a PCB board, the PCB board having at least one PCB pad; for each PCB pad, a support pillar is etched in the PCB board area between the PCB pad and the chip; the PCB pad and the chip are connected by a bonding wire, the bonding wire crossing the support pillar, the height of the support pillar being related to the arch height of the bonding wire; the distance between the side of the PCB pad and the side of the support pillar is greater than or equal to a first preset multiple of the diameter of the bonding wire.

[0005] Furthermore, the first preset multiple includes: 2 times.

[0006] Furthermore, the height of the support column is a second preset multiple of the arc height of the welding wire.

[0007] Furthermore, the second preset multiplier is 0.7 to 0.9 times.

[0008] Furthermore, the upper surface of the support column is covered with copper.

[0009] Furthermore, the supporting column is cylindrical in shape.

[0010] Furthermore, the diameter of the cylindrical support column is a third preset multiple of the diameter of the welding wire.

[0011] Furthermore, the third preset multiplier includes: 2 times.

[0012] Furthermore, the bonding wire includes: gold wire.

[0013] Furthermore, the chip is a VCSEL chip.

[0014] The chip packaging structure provided by this utility model includes: a chip, the chip being soldered onto a PCB board, and at least one PCB pad being provided on the PCB board; for each PCB pad, a support pillar is etched in the PCB board area between the PCB pad and the chip; the PCB pad and the chip are connected by a bonding wire, the bonding wire crossing the support pillar, and the height of the support pillar is related to the arch height of the bonding wire; the distance between the side of the PCB pad and the side of the support pillar is greater than or equal to a first preset multiple of the diameter of the bonding wire; in this chip packaging structure, the support pillar is etched in the PCB board area between the PCB pad and the chip. Since the support pillar can be etched simultaneously with the PCB board, no additional new process is required, thereby effectively controlling production costs; furthermore, the bonding wire between the PCB pad and the chip crosses the support pillar, and the appropriate height and position of the support pillar can be set according to the arch height of the bonding wire and the position of the PCB pad. When mechanical vibration or other situations occur, the bonding wire can be supported by the support pillar, thereby effectively reducing solder joint and bonding wire breakage problems. Attached Figure Description

[0015] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a traditional chip packaging structure. Figure 2 A schematic diagram of a chip packaging structure provided in an embodiment of this utility model; Figure 3 A schematic diagram of a chip packaging structure provided in an embodiment of this utility model; Figure 4 This is a schematic diagram of an automatic recovery process provided by an embodiment of the present utility model. Detailed Implementation

[0017] The technical solution of this utility model will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0018] like Figure 1 The diagram shows a traditional chip packaging structure. As can be seen from the diagram, the VCSEL chip is usually connected to the PCB pads via gold wires, which are suspended in the air. This packaging structure is prone to solder joint and gold wire breakage during transportation or drops due to mechanical vibration. Under the premise of controlling production costs, related technologies lack effective solutions for solder joint and gold wire breakage caused by mechanical vibration. Based on this, this utility model embodiment provides a chip packaging structure that can be applied to applications that require chip packaging.

[0019] To facilitate understanding of this embodiment, a chip packaging structure disclosed in this utility model embodiment will first be described, such as... Figure 2 As shown, the chip packaging structure includes: a chip, the chip soldered onto a PCB board, and at least one PCB pad on the PCB board; the chip can be a VCSEL chip or other types of chips, which are not limited here; For each PCB pad, a support pillar is etched in the PCB area between the pad and the chip. In this embodiment, each support pillar is etched onto the PCB and can be manufactured on the same layer as the circuitry, protected by a solder mask window, eliminating the need for an additional mask. The support pillar can be cylindrical, cuboid, or similar shapes. The PCB pad and chip are connected by a bonding wire, which can be gold, aluminum, or other suitable materials. Since the support pillar is positioned between the pad and the chip, the bonding wire will cross it. The height of the support pillar is related to the arch height of the bonding wire, which can be understood as the height of the highest point of the wire's arc. A suitable support pillar height can be determined based on this arch height; for example, the support pillar height could be 80% of the arch height. The distance between the side of the PCB pad and the side of the support post is greater than or equal to a first preset multiple of the diameter of the solder wire. In other words, in this embodiment, the minimum distance between the edge of the PCB pad and the edge of the support post is limited so that the support post and the solder joint on the PCB pad do not contact each other. Specifically, it can be a first preset multiple of the diameter of the solder wire, which can be set according to actual needs.

[0020] In one implementation, there can be multiple support pillars. For example, multiple support pillars can be etched sequentially at preset etching intervals in the PCB area between the PCB pads and the chip. The bonding wires between the PCB pads and the chip will cross multiple support pillars. When mechanical impact occurs, the bonding wires can be better supported by multiple support pillars, thereby further reducing the problem of solder joint and bonding wire breakage.

[0021] In the above chip packaging structure, since the support pillars are obtained by etching the PCB board, the support pillars and the PCB board are made of the same material, so no new variables need to be introduced. As shown in Table 1, compared with dissimilar materials, this same-material structure has several advantages: Table 1

[0022] In the aforementioned chip packaging structure, support pillars are etched in the PCB area between the PCB pads and the chip. Since the support pillars can be etched simultaneously with the PCB, no additional process is required, thus effectively controlling production costs. Furthermore, the bonding wires between the PCB pads and the chip cross the support pillars. The height and position of the support pillars can be set appropriately based on the arch height of the bonding wires and the position of the PCB pads. In the event of mechanical vibration, the bonding wires can be supported by these support pillars, thereby effectively reducing solder joint and bonding wire breakage issues.

[0023] In one embodiment, the first preset multiple includes 2 times, that is, the distance between the side of the PCB pad and the side of the support post is greater than or equal to twice the diameter of the solder wire. For example, if the solder wire is a gold wire with a diameter of 25μm, then the distance between the side of the PCB pad and the side of the support post is at least 50μm.

[0024] In one embodiment, the distance between the side of the PCB pad and the side of the support post can be in the range of 0.1mm-0.3mm.

[0025] In one embodiment, the height of the support column is a second preset multiple of the arc height of the welding wire. This second preset multiple can be set according to actual needs, and the appropriate height of the support column can be set according to the arc height of the welding wire.

[0026] Specifically, the second preset multiple is 0.7 to 0.9 times, preferably 0.8 times, that is, the height of the support column can be set to 80% of the arch height of the welding wire.

[0027] Furthermore, the upper surface of the support column is covered with copper. Taking gold wire as an example, during normal operation, the gold wire does not contact the support post (which does not affect the optoelectronic performance of the device); during a drop, the impact duration is about 50ms-200ms, and the contact time between the gold wire and the support post is <10ms. The contact time is extremely short, and the contact resistance is relatively high. Therefore, this extremely short contact time will not affect the long-term performance of the device. For details, please refer to the parameter diagram shown in Table 2 below. Table 2

[0028] In one embodiment, the support post is cylindrical, and its diameter is a third preset multiple of the diameter of the bonding wire. That is, in this embodiment, if the support post is cylindrical, its diameter can be determined based on the diameter of the bonding wire; for example, the third preset multiple can be any multiple between 2 and 3 times. Furthermore, taking a gold wire with a diameter of 25 μm as an example, the diameter of the support post can range from 0.03 mm to 0.08 mm.

[0029] Preferably, the third preset multiple includes: 2 times, that is, twice the diameter of the welding wire can be determined as the diameter of the support column.

[0030] In one embodiment, the bonding wire includes: gold wire; the chip is a VCSEL chip. That is, in the package structure for a VCSEL chip, gold wire can be used to connect the VCSEL chip and the PCB pads to achieve electrical connection, such as... Figure 3 The diagram shows a schematic of a chip packaging structure.

[0031] The working mechanism of the above chip packaging structure will be explained below, taking gold wire as an example: When subjected to external impact, the gold wire presses down on the support column to disperse stress and prevent the solder joint from tearing.

[0032] (1) Core design logic: Table 3 shows the comparison between the limited contact form of the structure in this scheme and the permanent fracture form of the traditional structure.

[0033] Table 3

[0034] (2) The core value of the support column: replacing uncontrollable permanent damage (irreversible) with controllable instantaneous risk (reversible).

[0035] (3) Automatic recovery process after the impact ends A. As Figure 4 The diagram shows an automatic recovery process. When the device is subjected to an impact, the gold wire will press down and contact the support column. The gold wire will elastically deform to store energy. After the impact ends, the gold wire will spring back to its original position.

[0036] B. Elastic deformation of gold wire, as shown in Table 4, is a table of relevant parameters of gold wire. The table shows the relevant parameter values ​​of elastic modulus, yield strength, and maximum elastic deformation of gold wire, as well as the corresponding recovery principle. That is, based on the characteristics of gold wire itself, the gold wire can basically recover to its original position after the impact.

[0037] Table 4

[0038] C. Rigid support columns (to prevent plastic deformation): Support column hardness: HV 80-100; Gold wire hardness: HV 25-30; Upon contact, the support column remains almost unchanged, with only the gold wire undergoing elastic bending.

[0039] D. Non-viscous contact (zero residue) Table 5 illustrates the contact types and their corresponding recoverability. In the table, metal fusion welding can be understood as a welding process where metal is heated to a molten state, causing partial melting of the workpieces, followed by cooling and solidification to form a permanent connection. Molecular adsorption refers to the process and phenomenon of molecules (solute molecules placed in a gas or liquid) adhering to or accumulating on the surface of another substance. As can be seen from Table 5, this scheme does not involve metal fusion welding or molecular adsorption; only mechanical contact occurs. This mechanical contact can be separated instantaneously and exhibits good recoverability.

[0040] Table 5

[0041] The following describes the fabrication steps for the chip packaging structure, which are compatible with existing processes: 1. Etch support pillars on the PCB board (the support pillars are manufactured on the same layer as the PCB circuit and protected by openings in the solder mask layer, without the need for additional mask). 2. Mounting VCSEL chips (1) As shown in Table 6, a process adjustment comparison table shows that the VCSEL chip in this scheme is compatible with traditional processes.

[0042] Table 6

[0043] (2) Placement accuracy requirements: The distance between the edge of the VCSEL chip and the support post is 0.15±0.05mm (high-precision placement machine required); 3. Gold wire bonding (parameters unchanged) (1) Bonding parameter optimization As shown in Table 7, a bonding parameter table shows that, due to the presence of support columns, the position and height of the support columns need to be considered in this scheme.

[0044] Table 7

[0045] (2) Compatibility verification: The height of the support post is less than the lowest point of the arc (under normal conditions, the distance between the lowest point of the arc and the edge of the pad is ≥20μm); the bonding machine program does not need to be modified (only the pad coordinates need to be adjusted). 4. Dispensing and encapsulation The following compares the proposed solution with the traditional structure in terms of relevant test items, specifically as shown in Table 8, which compares one type of test item. The test items mainly consider drop test pass rate and production cost. In terms of drop test pass rate, the traditional structure has a pass rate of about 70%, while the proposed solution has a pass rate of about 95%, an improvement of about 25%. In terms of processing cost, the traditional method using silicone filling increases production cost by ¥0.15 / piece, an increase of about 20%, while the proposed solution using etched support pillars increases production cost by approximately ¥0.01 / piece, an increase of about 1%. It can be seen that the proposed solution reduces production cost by about 19% compared to the traditional structure.

[0046] Table 8

[0047] The chip packaging structure described above provides a low-cost, breakage-resistant VCSEL packaging solution: it can reduce the risk of solder joint and wire breakage, is compatible with existing production lines, and does not require significant additional material costs.

[0048] In the description of this utility model, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0049] Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0050] Finally, it should be noted that the above-described embodiments are merely specific implementations of this utility model, used to illustrate the technical solution of this utility model, and not to limit it. The protection scope of this utility model is not limited thereto. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the technical scope disclosed in this utility model. These modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be covered within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A chip packaging structure, characterized in that, include: The chip is soldered onto a PCB board, and the PCB board is provided with at least one PCB pad. For each of the PCB pads, a support pillar is etched in the PCB board area between the PCB pad and the chip; the PCB pad and the chip are connected by a bonding wire, the bonding wire crosses the support pillar, and the height of the support pillar is related to the arch height of the bonding wire; the distance between the side of the PCB pad and the side of the support pillar is greater than or equal to a first preset multiple of the diameter of the bonding wire.

2. The chip packaging structure according to claim 1, characterized in that, The first preset multiple includes: 2 times.

3. The chip packaging structure according to claim 1, characterized in that, The height of the support column is a second preset multiple of the arch height of the welding wire.

4. The chip packaging structure according to claim 3, characterized in that, The second preset multiplier is 0.7 to 0.

9.

5. The chip packaging structure according to claim 1, characterized in that, The upper surface of the support column is covered with copper.

6. The chip packaging structure according to claim 1, characterized in that, The support column is cylindrical in shape.

7. The chip packaging structure according to claim 6, characterized in that, The diameter of the cylindrical support column is a third preset multiple of the diameter of the welding wire.

8. The chip packaging structure according to claim 7, characterized in that, The third preset multiple includes: 2 times.

9. The chip packaging structure according to claim 7, characterized in that, The bonding wire includes: gold wire.

10. The chip packaging structure according to claim 7, characterized in that, The chip is a VCSEL chip.