Power supply device and test system

Abstract

The application discloses a power supply device and a test system, and belongs to the technical field of chip performance test verification, and is used for connecting a chip to be tested and a storage battery, and comprises a control module, wherein the control module comprises a control unit, a feedback unit and an interaction unit, the control unit is connected with the feedback unit and the interaction unit respectively; a power supply module, wherein the power supply module comprises an input unit, a topology selection unit, a power supply unit and an output unit, the input unit, the topology selection unit, the power supply unit and the output unit are connected in sequence; wherein the topology selection unit is connected with the control unit, the feedback unit is connected with the power supply unit, and the interaction unit is connected with the output unit. The power supply device provided by the embodiment of the application can comprehensively evaluate the chip, and the evaluation result is high in accuracy.

Description

Technical Field

[0001] This application relates to the field of chip performance testing and verification technology, and in particular to a power supply device and a testing system. Background Technology

[0002] Chips are the carriers of integrated circuits and the most important components of electronic devices, undertaking functions such as computation, processing, and control. With the increasing integration and complexity of chips, and the trend towards domestic chip production, the electromagnetic compatibility (EMC) risks of 12V system designs (where the product input voltage is 12V) have significantly increased. In the early stages of product design, for newly introduced chips, it is necessary to conduct an EMC performance assessment of the chip's EVM (Evaluation Module) board, implement relevant EMC rectifications, and derive the optimal rectification plan to guide later design and reduce risks. However, current evaluation methods cannot comprehensively assess chip performance, and the evaluation results are inaccurate. Utility Model Content

[0003] A power supply device and a testing system are provided to address the aforementioned technical problems.

[0004] To achieve the above objectives, in a first aspect, a power supply device is provided for connecting a chip under test (DUT) and a battery, comprising: A control module, comprising a control unit, a feedback unit, and an interaction unit, wherein the control unit is connected to the feedback unit and the interaction unit respectively; A power module, comprising an input unit, a topology selection unit, a power supply unit, and an output unit, wherein the input unit, the topology selection unit, the power supply unit, and the output unit are connected in sequence; The topology selection unit is connected to the control unit, the feedback unit is connected to the power supply unit, and the interaction unit is connected to the output unit.

[0005] In conjunction with the first aspect, the input unit includes a protection circuit, a first filter circuit, and a second filter circuit. The protection circuit is used to connect to the battery, the second filter circuit is connected to the topology selection unit, and the first filter circuit is connected between the protection circuit and the second filter circuit.

[0006] In conjunction with the first aspect, the protection circuit includes a protection diode, a direction-limiting diode, a current-limiting resistor, and multiple protection capacitors. The protection diode is used to connect to the output terminal of the battery. The protection diode, the current-limiting resistor, and the multiple protection capacitors are connected in parallel and then grounded. The direction-limiting diode is used to connect to the output terminal of the battery to prevent reverse current flow.

[0007] In conjunction with the first aspect, the first filter circuit includes a first common-mode inductor, a plurality of first filter capacitors, and a plurality of second filter capacitors. The first common-mode inductor has a first common-mode terminal, a second common-mode terminal, a third common-mode terminal, and a fourth common-mode terminal. The first filter capacitors are connected to the first common-mode terminal and the second common-mode terminal, and the second filter capacitors are connected to the third common-mode terminal and the fourth common-mode terminal.

[0008] In conjunction with the first aspect, the second filter circuit includes a differential-mode inductor and a third filter capacitor. One end of the differential-mode inductor is connected to one end of the third filter capacitor, and the other end of the differential-mode inductor is configured as the output terminal of the input unit. Multiple third filter capacitors are connected in parallel and then grounded.

[0009] In conjunction with the first aspect, the power supply unit includes any one of a through circuit, a boost power supply circuit, and a buck power supply circuit; wherein, the through circuit includes a through wire, the boost power supply circuit is used to boost the input voltage, and the buck power supply circuit is used to buck the input voltage.

[0010] In conjunction with the first aspect, the topology selection unit includes a through selection circuit, a boost selection circuit, and a buck selection circuit. The through selection circuit is connected to the through wire, the boost selection circuit is connected to the boost power supply circuit, and the buck selection circuit is connected to the buck power supply circuit.

[0011] In conjunction with the first aspect, the control unit includes a microprocessor, the feedback unit is connected to a feedback pin on the microprocessor, the feedback unit includes a first voltage divider resistor, a second voltage divider resistor and a digital potentiometer, the first voltage divider resistor is connected in series with the digital potentiometer, the digital potentiometer is connected to the output terminal of the microprocessor, the other end of the first voltage divider resistor is connected to the feedback pin, one end of the second voltage divider resistor is connected to the feedback pin, and the other end is grounded.

[0012] In conjunction with the first aspect, the interactive unit includes a topology selection button circuit, a voltage adjustment button circuit, and a display circuit. The topology selection button circuit is used to select the desired topology circuit; the voltage adjustment button circuit is used to input the desired voltage value; and the display circuit is used to display the selected topology circuit and / or the input voltage value.

[0013] In conjunction with the first aspect, the output unit includes a third filter circuit and a fourth filter circuit. The third filter circuit includes a second common-mode inductor, a plurality of fourth filter capacitors, and a plurality of fifth filter capacitors. The second common-mode inductor includes a first connection terminal, a second connection terminal, a third connection terminal, and a fourth connection terminal. The plurality of fourth filter capacitors are connected to the first connection terminal and the second connection terminal, and the plurality of fifth filter capacitors are connected to the third connection terminal and the fourth connection terminal. The fourth filter circuit includes multiple sixth filter capacitors, which are connected in parallel and then grounded.

[0014] In a second aspect, a testing system is provided, comprising: a power supply device as described in any one of the first aspects above.

[0015] One of the above technical solutions has the following advantages or beneficial effects: This application provides a power supply device for connecting a chip under test (DUT) and a battery, comprising: a control module including a control unit, a feedback unit, and an interaction unit, wherein the control unit is connected to the feedback unit and the interaction unit respectively; and a power supply module including an input unit, a topology selection unit, a power supply unit, and an output unit, wherein the input unit, topology selection unit, power supply unit, and output unit are connected sequentially; wherein the topology selection unit is connected to the control unit, the feedback unit is connected to the power supply unit, and the interaction unit is connected to the output unit. The power supply device provided in this application, through its input and output units, can effectively filter the voltage signal from the input chip, thereby reducing voltage signal noise and improving the accuracy of the DUT evaluation results. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the module connection structure of a power supply device according to an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram of the circuit connection of the input unit in an exemplary embodiment of this disclosure; Figure 3 This is a circuit connection diagram of a power supply unit according to an exemplary embodiment of this disclosure; Figure 4 This is a circuit connection diagram of a topology selection unit according to an exemplary embodiment of this disclosure; Figure 5 This is a circuit connection diagram of the control unit according to an exemplary embodiment of the present disclosure; Figure 6 This is a schematic diagram showing the connection of the topology selection button circuit and the voltage adjustment button circuit in an exemplary embodiment of this disclosure; Figure 7 This is a schematic diagram of the module connections of a display circuit according to an exemplary embodiment of this disclosure; Figure 8 This is a connection diagram of the ADC sampling module according to an exemplary embodiment of this disclosure; Figure 9 This is a connection diagram of the digital tube display portion according to an exemplary embodiment of this disclosure; Figure 10 This is a schematic diagram of the circuit connection of the output unit in an exemplary embodiment of this disclosure. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] Furthermore, descriptions involving "first," "second," etc., in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0020] Electromagnetic compatibility (EMC) refers to the ability of electronic equipment or systems to operate normally in the expected electromagnetic environment without causing unacceptable electromagnetic interference to other equipment or systems. It essentially includes two aspects: 1. Electromagnetic interference (EMI): This refers to the interference caused to other equipment by electromagnetic signals generated by the equipment or system. 2. Electromagnetic immunity (EMS): This refers to the ability of equipment to maintain normal operation under electromagnetic interference.

[0021] Those skilled in the art have noted that, in 12V systems, when evaluating the EMC performance of newly introduced chips, chip manufacturers typically provide EVM boards for EMC performance testing and verification, using two main approaches. Option 1: Power is supplied via a programmable power supply isolated by a LISN (Line Impedance Stabilization Network). This option is suitable for 12V direct-drive primary chips. However, for secondary chips with other power supply voltages (greater or less than 12V), since these chips are not directly connected to the interface in the actual application system but are isolated by other primary chip modules, this power supply option may lead to incomplete and inaccurate EMC performance evaluation of the chips.

[0022] Option 2: Borrowing power modules from other products or designing a dedicated switching power supply. While this approach can address the second-level chip evaluation issue in Solution 1, it's typically a one-to-one solution, only compatible with a fixed voltage output and incompatible with other voltages. It's also single-use; replacing chips with different power requirements necessitates a redesign, making the power supply unit non-reusable and wasteful. Furthermore, these imported power supplies often neglect EMC performance, resulting in inaccurate evaluations and limited EMC modification options, hindering a comprehensive assessment of chip performance and the determination of the optimal solution.

[0023] like Figure 1 As shown in the illustration, this application proposes a power supply device for connecting a chip under test (DUT) and a battery. The device includes: a control module comprising a control unit, a feedback unit, and an interaction unit, with the control unit connected to both the feedback unit and the interaction unit; and a power supply module comprising an input unit, a topology selection unit, a power supply unit, and an output unit, connected sequentially. The topology selection unit is connected to the control unit, the feedback unit to the power supply unit, and the interaction unit to the output unit. Specifically, the DUT is typically mounted on an EVM board, a dedicated circuit board primarily provided by chip manufacturers for demonstrating and evaluating the performance of one or more chips. The target chip is directly soldered onto the EVM board, which also integrates necessary peripheral components for chip operation, such as power supplies, interfaces, and memory chips, essentially creating a plug-and-play chip testing platform. This allows users to test the chip's core functions—such as computing power and interface communication—as soon as they receive the chip and power it on. One end of the power supply device is connected to the EVM board, and the other end is connected to a battery providing a 12V DC voltage. It should be noted that the battery can also be powered by a LINS. LINS is primarily used to provide a standard, stable high-frequency impedance for the device under test, ensuring the repeatability and accuracy of electromagnetic interference conducted tests.

[0024] In this embodiment, the control module is the control center of the entire power supply device. The interaction unit can interact with the user to confirm the selection of voltage and topology circuit. The feedback unit is used to feed the selection result back to the power supply module. The input unit is used to connect to the battery and protect and filter the voltage input from the battery to remove noise. The topology selection unit acts as a selection switch to select the corresponding circuit. The power supply unit has multiple built-in voltage processing circuits, which adjust the voltage differently under the selection of the topology selection unit to achieve controlled voltage output. The output unit filters the output voltage signal again.

[0025] It is understood that the power supply device proposed in this application embodiment can realistically simulate the actual usage state of the chip under test, has a wide range of applications, greatly improves the reliability and accuracy of chip EMC performance evaluation, and provides strong reference value for subsequent design. Furthermore, the power supply device can dynamically adjust the output voltage, is compatible with the input voltage requirements of different chips, and the power supply device and test platform are reusable, greatly improving test efficiency and reducing costs.

[0026] like Figure 2 As shown in this embodiment, the input unit includes a protection circuit, a first filter circuit, and a second filter circuit. The protection circuit is connected to the battery, the second filter circuit is connected to the topology selection unit, and the first filter circuit is connected between the protection circuit and the second filter circuit. Specifically, the voltage input from the battery first passes through the protection circuit, then through the first filter circuit and the second filter circuit. The protection circuit primarily limits the strength of the battery voltage signal input to prevent large currents or voltages from impacting the circuit. The first filter circuit primarily filters out common-mode noise in the voltage signal, and the second filter circuit primarily filters out differential-mode noise in the voltage signal.

[0027] It is understandable that by setting up a protection circuit, a first filter circuit, and a second filter circuit in the input unit, not only can the circuit be effectively protected, but it can also filter out common-mode noise and differential-mode noise in the input voltage signal, thereby avoiding excessive noise from interfering with the equipment and affecting the test results of the chip under test.

[0028] like Figure 2As shown in this embodiment, the protection circuit includes a protection diode D4, a direction-limiting diode D1, a current-limiting resistor R1, and multiple protection capacitors. The protection diode D4 is connected to the output terminal of the battery. The protection diode D4, the current-limiting resistor, and the multiple protection capacitors are connected in parallel and then grounded. The direction-limiting diode D1 is connected to the output terminal of the battery to prevent reverse current flow. Specifically, the protection diode D4 includes two TVS diodes with their anodes connected together. The cathode of one TVS diode is connected to the output terminal of the battery, and the cathode of the other TVS diode is grounded. The two TVS diodes are used to achieve bidirectional transient voltage suppression of the circuit. The protection capacitors include at least a first protection capacitor CX1 and a second protection capacitor CX2. The first and second protection capacitors are connected in parallel with the two TVS diodes with adjacent anodes. The anode of the direction-limiting diode D1 is connected to the output terminal of the battery, and the cathode is connected to the current-limiting resistor, which is connected in parallel with the second protection capacitor.

[0029] Understandably, connecting the anodes of two TVS diodes eliminates the polarity dependence of a unidirectional TVS diode, adapts to bidirectional surge voltages, and reduces residual voltage compared to a single bidirectional TVS diode. Simultaneously, the use of a direction-limiting diode D1 prevents reverse current flow, thus protecting the battery; and the included protective capacitor enables primary filtering of the voltage signal, reducing noise and improving signal quality.

[0030] like Figure 2 As shown in the embodiment of this application, the first filter circuit includes a first common-mode inductor FIL1, multiple first filter capacitors, and multiple second filter capacitors. The first common-mode inductor has a first common-mode terminal, a second common-mode terminal, a third common-mode terminal, and a fourth common-mode terminal. The first filter capacitors are connected to the first and second common-mode terminals, and the second filter capacitors are connected to the third and fourth common-mode terminals. Specifically, the first common-mode inductor is essentially two sets of coils with the same number of turns but opposite winding directions, wound on the same magnetic core. Its main function is to impede the flow of common-mode current. When a common-mode current occurs in the circuit, the two sets of coils generate magnetic fields in opposite directions. These magnetic fields superimpose and enhance each other, thereby generating a large inductive reactance, preventing the common-mode current from passing through, and reducing the conduction of common-mode noise to the power grid or other equipment. For normal differential-mode current, the magnetic fields generated by the two sets of coils are in opposite directions and cancel each other out, resulting in almost zero inductive reactance, which does not impede the transmission of normal signals or power supply current.

[0031] In this embodiment, the first and second common-mode terminals of the first common-mode inductor are the input terminals. Multiple capacitors are connected to the input terminals of the first common-mode inductor to filter out common-mode noise at the input. It is worth noting that multiple capacitors with different capacitance values ​​are used at the input terminals of the first common-mode inductor. Since different capacitance values ​​result in different filtering effects for noise at different frequencies, a combination of multiple capacitors (e.g., large capacitance + small capacitance) can cover a wider frequency range and improve the overall filtering capability for high and low frequency noise. Correspondingly, the third and fourth common-mode terminals of the first common-mode inductor refer to its output terminals. By connecting multiple capacitors with different capacitance values ​​to the output terminals of the first common-mode inductor, residual noise after passing through the first common-mode inductor is filtered out, thereby protecting sensitive downstream circuitry. Both the input and output terminals of the first common-mode inductor are grounded; the input terminal is the interface ground, and the output terminal is the on-board ground, effectively preventing ground noise coupling. Meanwhile, a first ferrite bead FB1 is connected between the first common-mode terminal and the third common-mode terminal of the first common-mode inductor to further filter out high-frequency common-mode noise that is not completely suppressed by the first common-mode inductor; a second resistor R2 is connected between the second common-mode terminal and the fourth common-mode terminal of the first common-mode inductor for impedance matching, suppression of resonance, or attenuation of common-mode interference at a specific frequency.

[0032] It should be noted that the first filter capacitor includes at least a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5 with different capacitance values. These capacitors are connected in parallel to the first and second common-mode terminals of the first common-mode inductor. The second filter capacitor includes at least a sixth capacitor C6 and a seventh capacitor C7 with different capacitance values. These capacitors are connected in parallel to the third and fourth common-mode terminals of the first common-mode inductor. It is worth noting that multiple reserved positions are provided at the first, second, third, and fourth common-mode terminals of the first common-mode inductor. These reserved positions are used to connect filter capacitors, thus providing connection potentials for subsequent additions or replacements of capacitors with other capacitance values.

[0033] It is understandable that by setting a first common-mode inductor and connecting multiple capacitors of different capacitance values ​​in parallel at both the input and output terminals of the first common-mode inductor, the voltage signal input to the first common-mode inductor is filtered, and the voltage signal output from the first common-mode inductor is also filtered. This achieves multi-stage filtering of the voltage signal, avoids common-mode noise in the voltage signal from interfering with subsequent circuits, and improves the quality of the voltage signal.

[0034] like Figure 2As shown in this embodiment, the second filter circuit includes a differential-mode inductor L2 and a third filter capacitor. One end of the differential-mode inductor L2 is connected to one end of the third filter capacitor, and the other end of the differential-mode inductor L2 serves as the output of the input unit. Multiple third filter capacitors are connected in parallel and grounded. Specifically, the differential-mode inductor L2 is a single-coil inductor that only significantly impedes differential-mode current, having minimal impact on normal signals or supply current. When differential-mode current occurs in the circuit, the differential-mode inductor L2 generates a large inductive reactance, preventing these noise currents from passing through and avoiding their interference with subsequent circuits. Connecting multiple capacitors with different capacitance values ​​to the input terminal of the differential-mode inductor L2 serves to filter out high-frequency differential-mode noise in advance, thereby optimizing the overall filtering efficiency. It is worth noting that the third filter capacitors include at least an eighth capacitor C8, a ninth capacitor C9, and a tenth capacitor C10 with different capacitance values. Different capacitance values ​​correspond to different filtering frequency bands; for example, large capacitance values ​​are good at filtering low-frequency differential-mode noise, while small capacitance values ​​are good at filtering high-frequency differential-mode noise. By combining multiple capacitors, a wide frequency range from low to high frequencies can be covered, thus dealing with differential-mode interference at different frequencies.

[0035] It is understandable that differential mode noise in the circuit is suppressed by setting a differential mode inductor L2, and multiple capacitors with different capacitance values ​​are connected to the input terminal of the differential mode inductor L2. This is mainly to filter out some differential mode noise in advance, reduce the filtering burden of the differential mode inductor L2, and thus form a synergistic filtering effect of capacitors and inductors.

[0036] like Figure 3 As shown in the embodiments of this application, the power supply unit includes any one of a through circuit, a boost power supply circuit, and a buck power supply circuit. The through circuit includes a through wire. The boost power supply circuit is used to boost the input voltage, and the buck power supply circuit is used to buck the input voltage. Both the boost and buck power supply circuits include buck-boost power supply chips, with the model number including MPQ4232. Specifically, a through circuit is a no-topology circuit where the voltage signal does not undergo any boost or buck processing. This type of through circuit does not perform any voltage conversion and is mainly used for evaluating the performance of chips requiring a 12V voltage. Such chips are typically located at the port position, do not require isolation from other modules, do not require voltage conversion, and have no circuit structure; the circuit consists of direct wire connections.

[0037] In this embodiment, the buck power supply circuit, i.e., the BUCK power module, enables voltage step-down conversion and is mainly used for performance evaluation of chips requiring voltages less than 12V. The boost power supply circuit, i.e., the BOOST power module, enables voltage step-up conversion and is mainly used for performance evaluation of chips requiring voltages greater than 12V. It is noteworthy that the selected BUCK and BOOST power modules can be integrated into a single BUCK-BOOST module, and it is a Class 5 rated switching power supply with minimal high dv / dt and di / dt loops and a shielding cover to ensure high EMC performance. The BUCK-BOOST module includes a buck-boost chip MPQ4232, which includes an input pin VIN, an output pin OUT, and a feedback pin FB. A third resistor R3 and multiple parallel filter capacitors are connected in series on the input pin VIN. These filter capacitors include an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, a fourteenth capacitor C14, and a fifteenth capacitor C15. These filter capacitors are mainly used to filter the received input signal. The output pin OUT is used to connect to the output unit. The output pin OUT is connected to the fourth resistor R4 and multiple parallel filter capacitors, including the sixteenth capacitor C16, the seventeenth capacitor C17, the eighteenth capacitor C18, and the nineteenth capacitor C19. The feedback pin FB is connected to the feedback unit through the twenty-second resistor R22.

[0038] It is worth noting that, such as Figure 3 As shown, the MPQ4232 buck-boost chip also includes an enable pin EN, a clock pin SDA, and an I2C pin. 2 The circuit includes the following pins: Clock pin SCL, Alternate function pin ALT, First bootstrap pin BST1, Second bootstrap pin BST2, First switch pin SW1, Second switch pin SW2, Address pin ADDR, 5V power input / output pin V5V, Chip power supply pin VCC, Analog ground pin AGND, Power ground pin PGND, Current sensing positive pin ISEN+, Current sensing negative pin ISEN-, and Current monitoring output pin IMON. The enable pin EN is connected to the input terminal through the fifth resistor R5, and is also grounded through the sixth resistor R6, which is connected in parallel with the twentieth capacitor C20. The clock pin SDA is connected to the 3.54V operating voltage through the seventh resistor R7. 2The clock pin SCL is connected to the 3.54V operating voltage via resistor R8 (eighth resistor); the alternative function pin ALT is connected to the 3.54V operating voltage via resistor R9 (ninth resistor); the first bootstrap pin BST1 is connected to the first port of inductor L1 via resistor R10 (tenth resistor) and capacitor C21 (twentieth capacitor); the second bootstrap pin BST2 is connected to the second port of inductor L1 via resistor R11 (eleventh resistor) and capacitor C22 (twentieth capacitor); the first switch pin SW1 is connected to the first port of inductor L1; the second switch pin SW2 is connected to the second port of inductor L1. The first port of inductor L1 is grounded via resistor R12 (twelfth resistor) and capacitor C23 (twentieth capacitor), and the second port of inductor L1 is grounded via resistor R13 (thirteenth resistor) and capacitor C24 (twentieth capacitor); ground The address pin ADDR is connected to the 3.54V operating voltage through the fourteenth resistor R14, and grounded through the fifteenth resistor R15; the 5V power input / output pin V5V is grounded through the twenty-fifth capacitor C25; the chip power supply pin VCC is grounded through the twenty-sixth capacitor C26; the analog ground pin AGND and the power ground pin PGND are both grounded; the current sensing positive pin ISEN+ is grounded through the sixteenth resistor R16 and the twenty-seventh capacitor C27; the current sensing negative pin ISEN- is grounded through the seventeenth resistor R17 and the twenty-eighth capacitor C28; the sixteenth resistor R16 is also connected to the twenty-eighth capacitor C28 through the thirtieth capacitor C30; the current monitoring output pin IMON is grounded through the twenty-ninth capacitor C29.

[0039] It is understandable that by setting up a boost power supply circuit, the input voltage signal can be boosted to meet the voltage requirements of chips that need boosting; by setting up a buck power supply circuit, the input voltage signal can be bucked to meet the voltage requirements of chips that need bucking; by setting up a pass-through circuit, the input voltage signal can be directly connected to the chip to meet the corresponding chip requirements; by setting up various types of power supply circuits, the needs of various chips are met, expanding the application range and adaptability of the power supply device.

[0040] In this embodiment, the topology selection unit includes a through-through selection circuit, a boost selection circuit, and a buck selection circuit. The through-through selection circuit is connected to a through wire, the boost selection circuit is connected to a boost power supply circuit, and the buck selection circuit is connected to a buck power supply circuit. Specifically, the topology selection unit is a selector circuit, mainly used to select different circuits to be connected according to different needs. It is worth noting that the circuit structures of the through-through selection circuit, boost selection circuit, and buck selection circuit are the same. Figure 4As shown in the embodiment, this application uses a buck selection circuit as an example. The buck circuit includes a transistor Q1 and a MOSFET Q2. The base of transistor Q1 is connected to the GPIO pin of the microprocessor through the seventeenth resistor R17, and the collector of transistor Q1 is connected to the gate of the MOSFET through the eighteenth resistor R18. The emitter of transistor Q1 is grounded. A second diode D2 and a thirty-first capacitor C31 are connected in parallel between the base and emitter of transistor Q1. The anode of the second diode D2 is connected to the emitter of the transistor. The source of MOSFET Q2 serves as the input port, connected to the output of the input module. The drain of MOSFET Q2 serves as the output port, connected to one of a pass-through circuit, a boost power supply circuit, or a buck power supply circuit. A third diode D3, an eighteenth resistor R18, and a thirty-second capacitor C32 are connected between the gate and source of the MOSFET. The anode of the third diode D3 is connected to the gate of MOSFET Q2. A 33rd capacitor C33 is connected between the gate and drain of the MOSFET; a 19th resistor R19 is connected between the drain and source of the MOSFET. It should be noted that MOSFET Q2 is a P-type MOSFET. Therefore, when the microprocessor's GPIO pin outputs a high level, transistor Q1 conducts, and MOSFET Q2, with its gate grounded, receives a low level and conducts. At this time, the MOSFET connects both the input and output ports, and one of the corresponding through-circuit, boost, or buck power supply circuits will be selected.

[0041] It is understandable that by setting up pass-through selection circuits, boost selection circuits, and buck selection circuits, the corresponding circuits can be turned on according to the selected voltage, thereby achieving the adaptation of various voltages.

[0042] like Figure 5 As shown in this embodiment, the control unit includes a microprocessor, and the feedback unit is connected to the feedback pin on the microprocessor. The feedback unit includes a first voltage divider resistor FR1, a second voltage divider resistor FR1, and a digital potentiometer R. d The first voltage divider resistor FR1 and the digital potentiometer R d Series connection, digital potentiometer R d Connected to the output of the microprocessor, the other end of the first voltage divider resistor FR1 is connected to the feedback pin, and one end of the second voltage divider resistor FR2 is connected to the feedback pin, while the other end is grounded. Specifically, the microprocessor includes a buck-boost chip MPQ4232, and the microprocessor adjusts the digital potentiometer R... d The resistance values ​​are adjusted to control the voltage ratio between the first voltage divider resistor FR1 and the second voltage divider resistor FR2, thereby adjusting the voltage ratio and controlling the output voltage. This is achieved in the digital potentiometer R... d When the resistance of the digital potentiometer R increases, d As the total resistance of the first voltage divider resistor FR1 increases, the output voltage also increases; while in the digital potentiometer R...d The resistance of the digital potentiometer R decreases. d When the total resistance of the first voltage divider resistor FR1 decreases, the output voltage also decreases. That is, the output voltage is related to the resistance of the digital potentiometer R... d The resistance values ​​are positively correlated.

[0043] Understandably, this is achieved by controlling the digital potentiometer R. d The resistance value is adjusted to control the output voltage, thereby meeting the different voltage requirements of different chips and expanding the application range of the power supply device.

[0044] like Figure 6 As shown in this embodiment, the interaction unit includes a topology selection button circuit and a voltage adjustment button circuit. The topology selection button circuit is used to select the desired topology circuit; the voltage adjustment button circuit is used to input the required voltage value. Specifically, the button portion of the interaction unit is connected to the control unit, and the desired topology circuit can be selected through button operation, including one of a through circuit, a boost power supply circuit, or a buck power supply circuit. The topology selection button circuit includes a first button SW1, a second button SW2, and a third button SW3, and the voltage adjustment button circuit includes a fourth button SW4 and a fifth button SW5. One end of the first button SW1 is connected to the microprocessor through a twenty-third resistor R23; one end of the second button SW2 is connected to the microprocessor through a twenty-fourth resistor R24; one end of the third button SW3 is connected to the microprocessor through a twenty-fifth resistor R25; one end of the fourth button SW4 is connected to the microprocessor through a twenty-sixth resistor R26; one end of the fifth button SW5 is connected to the microprocessor through a twenty-seventh resistor R27; the other ends of the first button SW1, second button SW2, third button SW3, fourth button SW4, and fifth button SW5 are all grounded. Meanwhile, the first button SW1, the second button SW2, the third button SW3, the fourth button SW4, and the fifth button SW5 are all connected to a 3.3V voltage through the twenty-eighth resistor R28. For example... Figure 6 As shown, the circuit also includes a bidirectional suppressor D6 and a forty-fourth capacitor C44. The bidirectional suppressor D6 and the forty-fourth capacitor C44 are connected in parallel and then connected to the twenty-eighth resistor R28. The first button SW1 is the through-circuit selection button; the second button SW2 is the boost power supply circuit selection button; and the third button SW3 is the buck power supply circuit selection button. Pressing the corresponding button transmits a corresponding voltage signal to the microprocessor. The microprocessor determines the selected circuit based on the voltage signal and controls the corresponding circuit to conduct. The fourth button SW4 is the voltage increase button, and the fifth button SW5 is the voltage decrease button. Pressing these buttons selects the corresponding voltage value for the chip. After this voltage value is input to the microprocessor, the microprocessor adjusts the digital potentiometer R based on the magnitude of the voltage value. d The resistance value.

[0045] like Figure 7 , Figure 8 and Figure 9 As shown, the interactive unit also includes a display circuit; the display circuit is used to display the selected topology circuit and / or the input voltage value. The display circuit includes an AD conversion section and a digital tube display section. The AD conversion section is connected to the microprocessor and is used to receive voltage signals from the topology selection button circuit and the voltage adjustment button circuit, converting the voltage signals into conversion signals that the microprocessor can recognize. The digital tube display section is connected to the microprocessor, and the microprocessor controls the corresponding digital tubes in the digital tube display section to light up based on the conversion signals, thereby realizing the display of the selected circuit and voltage value. For example, Figure 8 As shown, the AD conversion circuit includes resistor R29 (29th), resistor R30 (30th), resistor R31 (31st), resistor R32 (32nd), capacitor C45 (45th), capacitor C46 (46th), and operational amplifier U2. One end of resistor R29 receives the voltage signals from the topology selection button circuit and the voltage adjustment button circuit. The other end of resistor R29 is connected to one end of resistor R30, and the other end of resistor R30 is grounded. One end of resistor R31 is connected between resistors R29 and R30, and the other end of resistor R31 is connected to... The positive input of operational amplifier U2 is connected to the non-inverting input, and the negative input is connected to the output. The positive terminal of operational amplifier U2 is connected to +3.3V, and the negative terminal is grounded. One end of capacitor C46 (46th capacitor) is connected between the non-inverting input of operational amplifier U2 and resistor R31 (31st resistor), and the other end is grounded. The output of operational amplifier U2 is connected to the ADC sampling module of the microprocessor through resistor R32 (32nd resistor). One end of capacitor C45 (45th capacitor) is connected between resistor R32 (32nd resistor) and the microprocessor, and the other end is grounded. The voltage signals from the topology selection button circuit and the voltage adjustment button circuit are divided by resistors R29 (29th resistor) and R30 (30th resistor), filtered by capacitor C46 (46th capacitor), amplified by operational amplifier U2, and then input to the microprocessor, thus realizing the amplification and transmission of the voltage signal.

[0046] like Figure 9As shown, the digital tube display section includes a first digital tube DS1, a second digital tube DS2, a third digital tube DS3, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a thirty-third resistor R33, a thirty-fourth resistor R34, a thirty-fifth resistor R35, a thirty-sixth resistor R36, a seventh diode D7, and an eighth diode D8; the microprocessor's first output pin IO_1 is connected to the base of the third transistor Q3 through the thirty-third resistor R33, and the collector of the third transistor Q3 is connected to pin 8 of the first digital tube DS1; the microprocessor's second output pin... Pin IO_2 is connected to the base of transistor Q4 via resistor R34 (34th resistor). The collector of transistor Q4 is connected to pin 8 of the first digital display DS1. Simultaneously, output pins IO_1 and IO_2 are connected to one end of resistor R35 via diodes D7 (7th diode) and D8 (8th diode), respectively. The cathodes of diodes D7 and D8 are both connected to resistor R35. The other end of resistor R35 is connected to the base of transistor Q5. The collector of transistor Q5 obtains its operating voltage VCC through resistor R36 (36th resistor). The base of transistor Q6 is connected to resistor R36 (36th resistor), and the collector of transistor Q6 is connected to pin 8 of the third digital display DS3. The emitters of transistors Q3, Q4, Q5, and Q6 are all grounded. Pins 1, 2, 3, 4, 5, 6, and 7 of the first digital tube DS1, the second digital tube DS2, and the third digital tube DS3 correspond to the strokes a, b, c, d, e, f, and g, respectively. Pins 1 to 7 are connected to the corresponding control pins of the microprocessor. When the topology selection button circuit and the voltage adjustment button circuit press the corresponding button to output a voltage signal, the microprocessor analyzes the voltage signal to obtain the specific number or letter, and sends a level signal to the corresponding pin according to the pre-defined lighting rules. When any of the pins 1 to 7 receives the corresponding level signal, the corresponding stroke is lit, thus realizing the display of numbers and letters.

[0047] Understandably, by setting up topology selection button circuit, voltage adjustment button circuit, and display circuit, a platform is provided for users to actively select and directly view the data. The voltage adjustment button circuit can select and adjust the voltage according to the required voltage of the battery cell to ensure that the battery cell receives the corresponding voltage. The topology selection button circuit can select the appropriate topology circuit according to the voltage signal boosting or bucking requirements. The display circuit can display the selection process and results to avoid errors.

[0048] like Figure 10As shown in the embodiment of this application, the output unit includes a third filtering circuit and a fourth filtering circuit. The third filtering circuit includes a second common-mode inductor, multiple fourth filtering capacitors, and multiple fifth filtering capacitors. The second common-mode inductor includes a first connection terminal, a second connection terminal, a third connection terminal, and a fourth connection terminal. The multiple fourth filtering capacitors are connected to the first connection terminal and the second connection terminal, and the multiple fifth filtering capacitors are connected to the third connection terminal and the fourth connection terminal. The fourth filtering circuit includes multiple sixth filtering capacitors, which are connected in parallel and then grounded. Specifically, the first and second connection terminals of the second common-mode inductor are the input terminals, and the third and fourth connection terminals of the second common-mode inductor refer to the output terminals of the first common-mode inductor. By connecting multiple capacitors to the input terminal of the second common-mode inductor, the core purpose is to filter out common-mode noise in the output signal. It is worth noting that multiple capacitors with different capacitance values ​​are provided at both the input and output terminals of the second common-mode inductor. By using capacitors with different capacitance values, the noise remaining after passing through the inductor is filtered out, thereby ensuring that the output signal does not contain common-mode noise. Both the input and output terminals of the second common-mode inductor are grounded. The input terminal is the interface ground, and the output terminal is the on-board ground, effectively preventing ground noise coupling. A second ferrite bead FB2 is connected between the first and third connection terminals of the second common-mode inductor to further filter out high-frequency common-mode noise that the second common-mode inductor does not completely suppress. A twentieth resistor R20 is connected between the second and fourth connection terminals of the second common-mode inductor for impedance matching, suppression of resonance, or attenuation of common-mode interference at specific frequencies.

[0049] It should be noted that the fourth filter capacitor includes at least the thirty-fourth capacitor C34, the thirty-fifth capacitor C35, the thirty-sixth capacitor C36, and the thirty-seventh capacitor C37, each with different capacitance values. The second filter capacitor includes at least the thirty-eighth capacitor C38 and the thirty-ninth capacitor C39, each with different capacitance values. It is worth noting that multiple reserved positions are provided at the first, second, third, and fourth connection terminals of the second common-mode inductor. These reserved positions are used to connect filter capacitors, thus providing connection potentials for subsequent additions or replacements of capacitors with other capacitance values. The sixth filter capacitor includes at least the fortieth capacitor C40, the forty-first capacitor C41, the forty-second capacitor C42, and the forty-third capacitor C43, each with different capacitance values. A twenty-first resistor R21 is connected between the fortieth capacitor C40 and the thirty-ninth capacitor C39.

[0050] It is understandable that by setting up a third and fourth filter circuit, including a second common-mode inductor in the third filter circuit, and connecting multiple capacitors of different capacitance values ​​in parallel at both the input and output terminals of the second common-mode inductor, the voltage signal input to the second common-mode inductor is filtered, and the voltage signal output from the second common-mode inductor is also filtered. This achieves multi-stage filtering of the voltage signal, avoiding interference from common-mode noise in the voltage signal to the chip, and improving the quality of the voltage signal.

[0051] In summary, the power supply device provided in this application has high EMC performance and a wealth of related EMC modification points, greatly avoiding the problem of inaccurate chip performance evaluation caused by EMC issues arising from external power supplies. Furthermore, the abundant EMC modification points help derive optimal solutions, providing a reference for later design and reducing risks. The power supply device is compatible with different power supply voltages, can be reused on a platform basis, improving efficiency and saving costs.

[0052] This application also provides a testing system, including a power supply device as provided in any of the above embodiments.

[0053] The above are merely optional embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A power supply device, characterized in that, Used to connect the chip under test and the battery, including: A control module, comprising a control unit, a feedback unit, and an interaction unit, wherein the control unit is connected to the feedback unit and the interaction unit respectively; A power module, comprising an input unit, a topology selection unit, a power supply unit, and an output unit connected in sequence; The topology selection unit is connected to the control unit, the feedback unit is connected to the power supply unit, and the interaction unit is connected to the output unit.

2. The power supply device according to claim 1, characterized in that, The input unit includes a protection circuit, a first filter circuit, and a second filter circuit. The protection circuit is used to connect to the battery, the second filter circuit is connected to the topology selection unit, and the first filter circuit is connected between the protection circuit and the second filter circuit.

3. The power supply device according to claim 2, characterized in that, The protection circuit includes a protection diode, a direction-limiting diode, a current-limiting resistor, and multiple protection capacitors. The protection diode is used to connect to the output terminal of the battery. The protection diode, the current-limiting resistor, and the multiple protection capacitors are connected in parallel and grounded. The direction-limiting diode is used to connect to the output terminal of the battery to prevent reverse current flow.

4. The power supply device according to claim 2 or 3, characterized in that, The first filter circuit includes a first common-mode inductor, a plurality of first filter capacitors and a plurality of second filter capacitors. The first common-mode inductor has a first common-mode terminal, a second common-mode terminal, a third common-mode terminal and a fourth common-mode terminal. The first filter capacitors are connected to the first common-mode terminal and the second common-mode terminal, and the second filter capacitors are connected to the third common-mode terminal and the fourth common-mode terminal.

5. The power supply device according to claim 4, characterized in that, The second filter circuit includes a differential-mode inductor and a third filter capacitor. One end of the differential-mode inductor is connected to one end of the third filter capacitor, and the other end of the differential-mode inductor is configured as the output terminal of the input unit. Multiple third filter capacitors are connected in parallel and then grounded.

6. The power supply device according to claim 1 or 2, characterized in that, The power supply unit includes any one of a through circuit, a boost power supply circuit, and a buck power supply circuit; wherein, the through circuit includes a through wire, the boost power supply circuit is used to boost the input voltage, and the buck power supply circuit is used to buck the input voltage.

7. The power supply device according to claim 6, characterized in that, The topology selection unit includes a through selection circuit, a boost selection circuit, and a buck selection circuit. The through selection circuit is connected to the through wire, the boost selection circuit is connected to the boost power supply circuit, and the buck selection circuit is connected to the buck power supply circuit.

8. The power supply device according to claim 6, characterized in that, The control unit includes a microprocessor, and the feedback unit is connected to a feedback pin on the microprocessor. The feedback unit includes a first voltage divider resistor, a second voltage divider resistor, and a digital potentiometer. The first voltage divider resistor is connected in series with the digital potentiometer, and the digital potentiometer is connected to the output terminal of the microprocessor. The other end of the first voltage divider resistor is connected to the feedback pin, and one end of the second voltage divider resistor is connected to the feedback pin, while the other end is grounded.

9. The power supply device according to claim 1, characterized in that, The interactive unit includes a topology selection button circuit, a voltage adjustment button circuit, and a display circuit. The topology selection button circuit is used to select the desired topology circuit; the voltage adjustment button circuit is used to input the desired voltage value; and the display circuit is used to display the selected topology circuit and / or the input voltage value.

10. The power supply device according to claim 2, characterized in that, The output unit includes a third filter circuit and a fourth filter circuit. The third filter circuit includes a second common-mode inductor, a plurality of fourth filter capacitors and a plurality of fifth filter capacitors. The second common-mode inductor includes a first connection terminal, a second connection terminal, a third connection terminal and a fourth connection terminal. The plurality of fourth filter capacitors are connected to the first connection terminal and the second connection terminal, and the plurality of fifth filter capacitors are connected to the third connection terminal and the fourth connection terminal. The fourth filter circuit includes multiple sixth filter capacitors, which are connected in parallel and then grounded.

11. A testing system, characterized in that, include: The power supply device as described in any one of claims 1 to 10.

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