Dual power automatic switching circuit
Patent Information
- Application Number
- CN202522379300.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-10
- Publication Date
- 2026-10-23
- Estimated Expiration
- 2035-11-10
AI Technical Summary
[0005]对于主电源A1和备用电源B1同时供电时，输出端电源VCC_OUT1会矛盾，无法确定采用主电源A1的供电还是备用电源B1的供电
[0026]本实用新型提供的一种双电源自动切换电路，包括：第一供电电源接口、第二供电电源接口以及供电输出端，还包括第一供电导通电路、第二供电导通电路，其中，第一供电导通电路位于第一供电电源接口与供电输出端之间，第二供电导通电路位于第二供电电源接口与供电输出端之间，第一供电导通电路包括第一PMOS、第二PMOS、第一NMOS以及第一电阻、第二电阻、第三电阻以及第四电阻，第二供电导通电路包括：第三PMOS、第四PMOS、第二NMOS、第三NMOS以及第第五电阻、第六电阻、第七电阻、第八电阻、第九电阻，进而在第一供电电源接口和第二供电电源接口均供电时优先选择第一供电电源接口实现供电，并且也保障了电路的安全性。
Smart Images
Figure CN224890384U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of power supply circuit technology, and in particular to a dual power supply automatic switching circuit. Background Technology
[0002] Existing dual power supply switching circuits, such as Figure 1 in, Figure 1 The dual power supply switching circuit shown is suitable for low-power power supply circuit scenarios, typically with a main power supply of 5V / 1.5A and a backup power supply of 3.3V / 1A.
[0003] When the main power supply A1 is powered, diode D26 is turned on and D27 is turned off. The output power supply VCC_OUT1 is approximately the same as VCC_A1. At the same time, since D25 is in the off state, it can effectively prevent current from flowing back to the input terminal of the backup power supply VCC_B1.
[0004] When backup power supply B1 is in operation, diode D27 is turned on and D26 is turned off. The output power supply VCC_OUT1 is approximately the same as VCC_B1. At the same time, since D26 is in the off state, it can effectively prevent current from flowing back to the input terminal of VCC_A1.
[0005] When the main power supply A1 and the backup power supply B1 supply power simultaneously, the output power supply VCC_OUT1 will be inconsistent, and it will be impossible to determine whether to use the power supply from the main power supply A1 or the backup power supply B1.
[0006] Therefore, how to achieve safe and automatic switching between dual power supplies is a technical problem that urgently needs to be solved. Utility Model Content
[0007] In view of the above problems, this utility model is proposed to provide a dual power supply automatic switching circuit that overcomes or at least partially solves the above problems.
[0008] In a first aspect, this utility model provides a dual-power automatic switching circuit, comprising:
[0009] First power supply interface, second power supply interface and power output terminal;
[0010] The first power supply conduction circuit is located between the first power supply interface and the power supply output terminal, and includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a first resistor, a second resistor, a third resistor and a fourth resistor;
[0011] The first power supply interface is connected to the first source of the first PMOS transistor, the first drain of the first PMOS transistor is connected to the second drain of the second PMOS transistor, the first gate of the first PMOS transistor is connected to the second gate of the second PMOS transistor to form a first connection point, and the second source of the second PMOS transistor is connected to the power supply output terminal.
[0012] The first power supply interface is connected to the second resistor and the third resistor in sequence and then grounded. The third gate of the first NMOS transistor is connected between the second resistor and the third resistor. The third drain of the first NMOS transistor is connected to the first connection point, and the first connection point is connected to the first resistor and then connected to the power supply output terminal. The third source of the first NMOS transistor is connected to the fourth resistor and then grounded.
[0013] The second power supply conduction circuit is located between the second power supply interface and the power supply output terminal, and includes: a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor.
[0014] The second power supply interface is connected to the fourth source of the third PMOS transistor, the fourth drain of the third PMOS transistor is connected to the fifth drain of the fourth PMOS transistor, the fourth gate of the third PMOS transistor is connected to the fifth gate of the fourth PMOS transistor, forming a second connection point, and the fifth source of the fourth PMOS transistor is connected to the power supply output terminal.
[0015] The first power supply interface is connected to the seventh resistor and the ninth resistor in sequence and then grounded. The sixth gate of the second NMOS transistor is connected between the seventh resistor and the ninth resistor. The sixth source of the second NMOS transistor is grounded. The sixth drain of the second NMOS transistor is connected to the sixth resistor and then connected to the power supply output terminal.
[0016] The seventh gate of the third NMOS transistor is connected to the sixth drain of the second NMOS transistor, the seventh source of the third NMOS transistor is connected to the eighth resistor and then grounded, the seventh drain of the third NMOS transistor is connected to the second connection point, and the second connection point is connected to the power supply output terminal after being connected to the fifth resistor.
[0017] Preferably, the resistance of the first resistor is equal to the resistance of the fourth resistor, and the resistance of the second resistor is greater than the resistance of the third resistor.
[0018] Preferably, when the first power supply interface is powered and the second power supply interface is not powered, the second NMOS transistor is turned on first, and both the first PMOS transistor and the second PMOS transistor are turned on, so that the power supply voltage at the power supply output terminal is equal to the power supply voltage at the first power supply interface.
[0019] Preferably, the first body diode in the fourth PMOS transistor ensures that the power output terminal does not backflow to the second power supply interface.
[0020] Preferably, the resistance of the fifth resistor is equal to the resistance of the eighth resistor, and the resistance of the seventh resistor is greater than the resistance of the ninth resistor.
[0021] Preferably, when the second power supply interface is powered and the first power supply interface is not powered, the third PMOS transistor is turned on first, and the fourth PMOS transistor is also turned on, while the second NMOS transistor is turned off and the third NMOS transistor is turned on, so that the power supply voltage at the power supply output terminal is equal to the power supply voltage at the second power supply interface.
[0022] Preferably, the second body diode in the second PMOS transistor prevents backflow from the power output terminal to the first power supply interface.
[0023] Preferably, when the first power supply interface is powered and the second power supply interface is also powered, the second NMOS transistor is turned on, the third NMOS transistor is turned off, and the third PMOS transistor and the fourth PMOS transistor are both turned off, so that the power supply voltage at the power supply output terminal is equal to the power supply voltage at the first power supply interface.
[0024] Preferably, the first power supply interface is the main power supply interface, and the second power supply interface is the backup power supply interface.
[0025] One or more technical solutions in the embodiments of this utility model have at least the following technical effects or advantages:
[0026] This utility model provides a dual-power automatic switching circuit, including: a first power supply interface, a second power supply interface, and a power supply output terminal, as well as a first power supply conduction circuit and a second power supply conduction circuit. The first power supply conduction circuit is located between the first power supply interface and the power supply output terminal, and the second power supply conduction circuit is located between the second power supply interface and the power supply output terminal. The first power supply conduction circuit includes a first PMOS, a second PMOS, a first NMOS, and a first resistor, a second resistor, a third resistor, and a fourth resistor. The second power supply conduction circuit includes: a third PMOS, a fourth PMOS, a second NMOS, a third NMOS, and a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor. Thus, when both the first power supply interface and the second power supply interface are supplying power, the first power supply interface is preferentially selected for power supply, which also ensures the safety of the circuit. Attached Figure Description
[0027] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, the same reference figures denote the same parts throughout the drawings. In the drawings:
[0028] Figure 1 A schematic diagram of the structure of a related processor in the related technology is shown;
[0029] Figure 2A schematic diagram of the dual-power automatic switching circuit in an embodiment of this utility model is shown. Detailed Implementation
[0030] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0031] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this utility model, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0032] This utility model embodiment provides a dual-power automatic switching circuit, such as... Figure 2 As shown, it includes:
[0033] The first power supply interface VCC_A2, the second power supply interface VCC_B2, and the power output terminal VCC_OUT2;
[0034] It also includes: a first power supply conduction circuit and a second power supply conduction circuit;
[0035] The first power supply conduction circuit is located between the first power supply interface VCC_A2 and the power supply output terminal VCC_OUT2, and includes a first PMOS transistor Q1, a second PMOS transistor Q2, a first NMOS transistor Q3, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4.
[0036] Specifically, the first power supply interface VCC_A2 is connected to the first source S1 of the first PMOS transistor Q1, the first drain D1 of the first PMOS transistor Q1 is connected to the second drain D2 of the second PMOS transistor Q2, the first gate G1 of the first PMOS transistor Q1 is connected to the second gate G2 of the second PMOS transistor Q2, forming the first connection point P1, and the second source S2 of the second PMOS transistor Q2 is connected to the power supply output terminal VCC_OUT2.
[0037] The first power supply interface VCC_A2 is connected to the second resistor R2 and the third resistor R3 in sequence and then grounded. The third gate G3 of the first NMOS transistor Q3 is connected between the second resistor R2 and the third resistor R3. The third drain D3 of the first NMOS transistor Q3 is connected to the first connection point P1, and the first connection point P1 is connected to the first resistor R1 and then connected to the power supply output terminal VCC_OUT2. The third source S3 of the first NMOS transistor Q3 is connected to the fourth resistor R4 and then grounded.
[0038] The second power supply conduction circuit, located between the second power supply interface and the power supply output terminal, includes: a third PMOS transistor Q4, a fourth PMOS transistor Q5, a second NMOS transistor Q7, a third NMOS transistor Q6, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9.
[0039] Specifically, the second power supply interface VCC_B2 is connected to the fourth source S4 of the third PMOS transistor Q4, the fourth drain D4 of the third PMOS transistor Q4 is connected to the fifth drain D5 of the fourth PMOS transistor Q5, the fourth gate G4 of the third PMOS transistor Q4 is connected to the fifth gate G5 of the fourth PMOS transistor Q5, forming the second connection point P2, and the fifth source S5 of the fourth PMOS transistor Q5 is connected to the power supply output terminal VCC_OUT2.
[0040] The first power supply interface VCC_A2 is connected to the seventh resistor R7 and the ninth resistor R9 in sequence and then grounded. The sixth drain D6 of the second NMOS transistor Q7 is connected between the seventh resistor R7 and the ninth resistor R9. The sixth source S6 of the second NMOS transistor Q7 is grounded. The sixth drain D6 of the second NMOS transistor Q7 is connected to the sixth resistor R6 and then connected to the power supply output terminal VCC_OUT2.
[0041] The seventh gate G7 of the third NMOS transistor Q6 is connected to the sixth drain D6 of the second NMOS transistor Q7. The seventh source S7 of the third NMOS transistor Q6 is connected to the eighth resistor R8 and then grounded. The seventh drain D7 of the third NMOS transistor Q6 is connected to the second connection point P2, and the second connection point P2 is connected to the power supply output terminal VCC_OUT2 through the fifth resistor.
[0042] The following defines some of the resistors: the resistance of the first resistor is equal to the resistance of the fourth resistor, and the resistance of the second resistor is greater than the resistance of the third resistor.
[0043] The following sections will explain the conduction principles for separately powering the first power supply interface VCC_A2, separately powering the second power supply interface VCC_B2, and simultaneously powering the first power supply interface VCC_A2 and the second power supply interface VCC_B2:
[0044] The system is configured to use a high-voltage and high-current power supply. Specifically, the first power supply interface VCC_A2 is equipped with a power supply voltage of 28V, the second power supply interface VCC_B2 is equipped with a power supply voltage of 28V, and the power supply current is 10A for both.
[0045] First, when the first power supply interface VCC_A2 is powered, the second power supply interface VCC_B2 is not powered. As a result, the second NMOS transistor Q7 is turned on first, and the first PMOS transistor Q1 and the second PMOS transistor Q2 are both turned on, so that the power supply voltage of the power supply output terminal VCC_OUT2 is equal to the power supply voltage of the first power supply interface VCC_B2.
[0046] Specifically, the resistance of the first resistor R1 is equal to the resistance of the fourth resistor R4, R1 = R4 = 51kΩ, R2 = 10kΩ, and R3 = 4.7kΩ. With these parameters set, when the first power supply interface VCC_A2 is powered alone, the supply voltage, divided by the second resistor R2 and the third resistor R3, causes the voltage corresponding to the third gate G3 of the first NMOS transistor Q3 to... GS3 =8.95V, here the threshold voltage of NMOS is set to V. th1 =1V, the threshold voltage of the PMOS is V th2 = -2V. Wherein, the threshold voltage V corresponding to the first NMOS transistor Q3 is... th1 =1V, at this time V GS3 >V th1 Therefore, the first NMOS transistor Q3 is turned on. Then, the voltages at the first gate G1 of the first PMOS transistor Q1 and the second gate G2 of the second PMOS transistor Q2 are both 0. The voltage V of the first PMOS transistor Q1... GS1 = -28V, while the threshold voltage of the first PMOS transistor Q1 and the threshold voltage of the second PMOS transistor Q2 both satisfy V th2 = -2V, V GS1 <V th2 This causes the first PMOS transistor Q1 to conduct, while the first body diode of the second PMOS transistor Q2 is forward-biased, resulting in the gate-source voltage of the second PMOS transistor Q2 being lower than the threshold voltage. GS2 <V th2 This will also turn on the second PMOS transistor Q2, and the output voltage at the power supply output terminal VCC_OUT2 will be equal to the supply voltage of the first power supply interface VCC_A2. Even later, after the voltage is divided to 14V at the first connection point P1, the first PMOS transistor Q1 and the second PMOS transistor Q2 will still satisfy the condition that their respective gate-source voltages are less than the threshold voltage. Therefore, the first PMOS transistor Q1 and the second PMOS transistor Q2 will still be turned on. Moreover, due to the presence of the first body diode in the fourth PMOS transistor Q5, the voltage at the power supply output terminal VCC_OUT2 will not flow back to the second power supply interface VCC_B2.
[0047] Next, the second power supply circuit is described separately, wherein the resistance of the fifth resistor R5 is equal to the resistance of the eighth resistor R8, and the resistance of the seventh resistor R7 is greater than the resistance of the ninth resistor R9.
[0048] Specifically, when the second power supply interface VCC_B2 is powered and the first power supply interface is not powered, the third PMOS transistor Q4 is turned on first, and the fourth PMOS transistor Q5 is also turned on, while the second NMOS transistor Q7 is turned off and the third NMOS transistor Q6 is turned on, so that the output of the power supply output terminal VCC_OUT2 is equal to the power supply voltage of the second power supply interface VCC_B2.
[0049] In the specific implementation, R5 = R8 = 51kΩ, R7 = 10kΩ, and R9 = 4.7kΩ. With these parameters, when the second power supply interface VCC_B2 is powered alone, neither the second NMOS transistor Q7 nor the fourth PMOS transistor Q5 is turned on, while the third PMOS transistor Q4 is turned on because its gate-source voltage satisfies V... GS4 <V th2 Therefore, the third PMOS transistor Q4 turns on first. At this time, under the action of the first body diode of the fourth PMOS transistor Q5, Q5 also turns on. Thus, the output of the power supply output terminal VCC_OUT2 is equal to the supply voltage of the second power supply interface VCC_B2. The voltage at the seventh gate S7 of the third NMOS transistor Q6 is 28V, corresponding to V... GS7 >V th2 This causes the third NMOS transistor Q6 to conduct. After voltage division at the second connection point P2 via the fifth resistor R5 and the fourth resistor R4, the voltage at P2 is determined to be 14V, thus ensuring that the third PMOS transistor Q4 and the fourth PMOS transistor Q5 remain conducting. Furthermore, the second body diode of the second PMOS transistor Q2 prevents backflow from the power supply output terminal VCC_OUT2 to the first power supply interface VCC_A2.
[0050] When the first power supply interface VCC_A2 and the second power supply interface VCC_B2 are powered simultaneously, regardless of whether the first power supply interface VCC_A2 or the second power supply interface VCC_B2 is powered first, the second NMOS transistor Q7 is turned on, the third NMOS transistor Q6 is turned off, and the third PMOS transistor Q4 and the fourth PMOS transistor Q5 are both turned off, so that the output of the power supply output terminal VCC_OUT2 is equal to the supply voltage of the first power supply interface VCC_A2.
[0051] Therefore, when the first power supply interface VCC_A2 and the second power supply interface VCC_B2 are powered simultaneously, the power supply voltage of the first power supply interface VCC_A2 is selected first to ensure the safety of the power supply circuit.
[0052] Specifically, when the first power supply interface VCC_A2 and the second power supply interface VCC_B2 are powered simultaneously, the supply voltage, after being divided by the seventh resistor R7 and the ninth resistor R9, is divided into a voltage of 8.95V at the sixth gate G6 of the second NMOS transistor Q7, which is the V corresponding to the second NMOS transistor Q7. GS6 >V th1 Thus, the second NMOS transistor Q7 is turned on, and the seventh gate voltage of the third NMOS transistor Q6 is 0. Therefore, the V corresponding to the third NMOS transistor Q6... GS7 Less than V th1 Therefore, the third NMOS transistor Q6 is turned off. At this time, the second connection point P2 is pulled up to 28V through the fifth resistor R5, which causes the gate-drain voltages corresponding to the third PMOS transistor Q4 and the fourth PMOS transistor Q5 to be greater than the threshold voltage, so that the third PMOS transistor Q4 and the fourth PMOS transistor Q5 are both turned off. Thus, the output voltage of the final power supply output terminal VCC_OUT2 is the power supply voltage of the first power supply interface VCC_A2.
[0053] This dual-power automatic switching circuit is suitable for power supply scenarios with a main power supply and a backup power supply. Power can be supplied by either power supply, but when the main power supply and the backup power supply are supplying power at the same time, the supply voltage of the main power supply is selected first.
[0054] Therefore, the first power supply interface VCC_A1 is the main power supply interface, while the second power supply interface VCC_B2 is the backup power supply interface.
[0055] Moreover, this dual-power automatic switching circuit can be applied to high-voltage and high-current power supply scenarios. The present invention uses a voltage of 28V and a current of 10A, which will not burn out the circuit and ensure the safety of the circuit.
[0056] One or more technical solutions in the embodiments of this utility model have at least the following technical effects or advantages:
[0057] This utility model provides a dual-power automatic switching circuit, including: a first power supply interface, a second power supply interface, and a power supply output terminal, and also includes a first power supply conduction circuit and a second power supply conduction circuit. The first power supply conduction circuit is located between the first power supply interface and the power supply output terminal, and the second power supply conduction circuit is located between the second power supply interface and the power supply output terminal. The first power supply conduction circuit includes a first PMOS, a second PMOS, a first NMOS, and a first resistor, a second resistor, a third resistor, and a fourth resistor. The second power supply conduction circuit includes a third PMOS, a fourth PMOS, a second NMOS, a third NMOS, and a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor. Thus, when both the first power supply interface and the second power supply interface are supplying power, the first power supply interface is preferentially selected for power supply, which can be applied to scenarios with large power input.
[0058] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.
[0059] Obviously, those skilled in the art can make various modifications and variations to this utility model without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this utility model and their equivalents, this utility model also intends to include these modifications and variations.
Claims
1. A dual-power automatic switching circuit, characterized in that, include: First power supply interface, second power supply interface and power output terminal; The first power supply conduction circuit is located between the first power supply interface and the power supply output terminal, and includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a first resistor, a second resistor, a third resistor and a fourth resistor; The first power supply interface is connected to the first source of the first PMOS transistor, the first drain of the first PMOS transistor is connected to the second drain of the second PMOS transistor, the first gate of the first PMOS transistor is connected to the second gate of the second PMOS transistor to form a first connection point, and the second source of the second PMOS transistor is connected to the power supply output terminal. The first power supply interface is connected to the second resistor and the third resistor in sequence and then grounded. The third gate of the first NMOS transistor is connected between the second resistor and the third resistor. The third drain of the first NMOS transistor is connected to the first connection point, and the first connection point is connected to the first resistor and then connected to the power supply output terminal. The third source of the first NMOS transistor is connected to the fourth resistor and then grounded. The second power supply conduction circuit is located between the second power supply interface and the power supply output terminal, and includes: a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor. The second power supply interface is connected to the fourth source of the third PMOS transistor, the fourth drain of the third PMOS transistor is connected to the fifth drain of the fourth PMOS transistor, the fourth gate of the third PMOS transistor is connected to the fifth gate of the fourth PMOS transistor, forming a second connection point, and the fifth source of the fourth PMOS transistor is connected to the power supply output terminal. The first power supply interface is connected to the seventh resistor and the ninth resistor in sequence and then grounded. The sixth gate of the second NMOS transistor is connected between the seventh resistor and the ninth resistor. The sixth source of the second NMOS transistor is grounded. The sixth drain of the second NMOS transistor is connected to the sixth resistor and then connected to the power supply output terminal. The seventh gate of the third NMOS transistor is connected to the sixth drain of the second NMOS transistor, the seventh source of the third NMOS transistor is connected to the eighth resistor and then grounded, the seventh drain of the third NMOS transistor is connected to the second connection point, and the second connection point is connected to the power supply output terminal after being connected to the fifth resistor.
2. The dual-power automatic switching circuit as described in claim 1, characterized in that, The resistance of the first resistor is equal to the resistance of the fourth resistor, and the resistance of the second resistor is greater than the resistance of the third resistor.
3. The dual-power automatic switching circuit as described in claim 1, characterized in that, When the first power supply interface is powered and the second power supply interface is not powered, the second NMOS transistor is turned on first, and both the first PMOS transistor and the second PMOS transistor are turned on, so that the power supply voltage at the power supply output terminal is equal to the power supply voltage at the first power supply interface.
4. The dual-power automatic switching circuit as described in claim 3, characterized in that, The first body diode in the fourth PMOS transistor ensures that the power output terminal does not backflow to the second power supply interface.
5. The dual-power automatic switching circuit as described in claim 1, characterized in that, The resistance of the fifth resistor is equal to that of the eighth resistor, and the resistance of the seventh resistor is greater than that of the ninth resistor.
6. The dual-power automatic switching circuit as described in claim 1, characterized in that, When the second power supply interface is powered and the first power supply interface is not powered, the third PMOS transistor turns on first, and the fourth PMOS transistor also turns on, while the second NMOS transistor is turned off and the third NMOS transistor turns on, so that the power supply voltage at the power supply output terminal is equal to the power supply voltage at the second power supply interface.
7. The dual-power automatic switching circuit as described in claim 1, characterized in that, The second body diode in the second PMOS transistor ensures that the power output terminal does not backflow to the first power supply interface.
8. The dual-power automatic switching circuit as described in claim 1, characterized in that, When the first power supply interface is powered and the second power supply interface is also powered, the second NMOS transistor is turned on, the third NMOS transistor is turned off, and the third PMOS transistor and the fourth PMOS transistor are both turned off, so that the power supply voltage at the power supply output terminal is equal to the power supply voltage at the first power supply interface.
9. The dual-power automatic switching circuit as described in claim 1, characterized in that, The first power supply interface is the main power supply interface, and the second power supply interface is the backup power supply interface.