A power supply bleed circuit and power supply arrangement for chip testing

Abstract

The utility model provides a kind of power supply bleed circuit and power supply device for chip test, the power supply bleed circuit includes bleed unit and control unit;One end of the bleed unit is used to access power supply unit, and the other end is connected to the control unit;The bleed unit includes multiple bleed paths arranged in parallel, and the bleed path is provided with a switching element, and the control unit is connected to the switching element to control the switch of the switching element to realize the on-off of the bleed path.The utility model is for the up and down power redundancy test setting of chip development verification stage, can flexibly switch bleed path by control unit, to meet the different needs of discharge rate, residual charge discharge degree in test process, greatly facilitate the up and down power redundancy test of chip.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, and more specifically to a power discharge circuit and a power supply device for chip testing. Background Technology

[0002] In the power-on / off redundancy test of chip development and verification, the chip performance needs to be verified by adjusting the power supply voltage discharge time. However, adjusting the discharge time depends on the discharge resistor with different resistance values. In the existing technology, the discharge resistor value is fixed, and the resistor needs to be manually soldered and changed every time it is adjusted. This operation wastes a lot of time, seriously reduces the chip timing debugging efficiency, and brings great inconvenience to the chip development and verification work. Utility Model Content

[0003] The purpose of this utility model is to overcome the defects of the prior art and provide a power supply device for chip testing. Its purpose is to solve the technical problem that the power supply needs to be manually disassembled and installed when it needs to be depressurized during chip testing, which is cumbersome.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: A power discharge circuit includes: a discharge unit and a control unit; one end of the discharge unit is connected to a power supply unit, and the other end is connected to the control unit; the discharge unit includes multiple discharge paths arranged in parallel, and a switching element is provided in each discharge path; the control unit is connected to the switching element to control the switching of the switching element to realize the opening and closing of the discharge path.

[0005] In one embodiment, the discharge path includes a discharge resistor and the switching element, the switching element being a field-effect transistor (FET). One end of the discharge resistor is connected to the power supply unit, and the other end is connected to the drain of the FET. The source of the FET is grounded, and the gate is connected to the control unit.

[0006] In one embodiment, a bias resistor is also connected between the source and gate of the field-effect transistor.

[0007] In one embodiment, a bidirectional breakdown diode is also connected between the source and gate of the field-effect transistor.

[0008] In one embodiment, the gate of the field-effect transistor has a built-in resistor.

[0009] In one embodiment, the control unit is an MCU chip.

[0010] In one embodiment, the MCU chip has several general-purpose input / output pins, and the multiple switching elements are respectively connected to different general-purpose input / output pins of the MCU chip.

[0011] In one embodiment, the MCU chip is an STM32H523VCT6.

[0012] Secondly, this utility model embodiment also provides a power supply device for chip testing, including the power discharge circuit as described above, and further including a power supply unit and an energy storage capacitor. The output terminal of the power supply unit is connected to one end of the energy storage capacitor and the discharge unit, and is used to connect to the chip under test. The other end of the energy storage capacitor is grounded.

[0013] In one embodiment, the power supply unit includes a DC-DC voltage converter, an input filter capacitor, a pull-up resistor, an energy storage inductor, a first voltage divider resistor, and a second voltage divider resistor. The input voltage terminal of the DC-DC voltage converter is connected to a DC power source and is connected to one end of the input filter capacitor and one end of the pull-up resistor. The other end of the input filter capacitor is grounded. The other end of the pull-up resistor is connected to the enable terminal of the DC-DC voltage converter. The switching terminal of the DC-DC voltage converter is connected to one end of the energy storage inductor. The other end of the energy storage inductor is connected to one end of the first voltage divider resistor and the energy storage capacitor, and is used to connect to the chip under test. The other end of the first voltage divider resistor is connected to the feedback terminal of the DC-DC voltage converter and one end of the second voltage divider resistor. The other end of the second voltage divider resistor is grounded.

[0014] Compared with the prior art, the advantages of this utility model are as follows: by setting up multiple parallel discharge paths and controlling the switching elements by the control unit, the on and off of different switching elements can be controlled to make one or more of the discharge paths conduct, thereby quickly adjusting the discharge time. There is no need to manually solder and change the discharge resistor value, which greatly simplifies the operation process, avoids the trouble and time waste caused by manually changing the resistor, provides great convenience for chip power-on and power-off redundancy testing, and effectively improves the chip timing debugging efficiency.

[0015] The above description is only an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model, it can be implemented according to the contents of the specification. In order to make the above and other objects, features and advantages of this utility model more obvious and easy to understand, the following are preferred embodiments, which are described in detail below. Attached Figure Description

[0016] Figure 1 A circuit diagram of a power supply device for chip testing provided by this utility model.

[0017] Figure Labels 1. Discharge unit; 11. Discharge path; 2. Control unit; 3. Power supply unit Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0020] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0021] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0022] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0023] See Figure 1 As shown, this utility model provides an embodiment of a power discharge circuit, including: a discharge unit 1 and a control unit 2; one end of the discharge unit 1 is connected to a power supply unit 3, and the other end is connected to the control unit 2; the discharge unit 1 includes multiple discharge paths 11 arranged in parallel, and each discharge path 11 is provided with a switching element (e.g., Figure 1 (Q126, Q127, Q128 in the code) Control unit 2 is connected to the switching element to control the switching of the switching element, thereby realizing the opening and closing of the discharge passage 11.

[0024] Specifically, the power supply discharge circuit provided in this embodiment is mainly designed for power-on / off redundancy testing during the chip development and verification phase. Chips typically have multiple power supplies, with specific timing requirements for both power-on and power-off cycles. In power-on / off redundancy testing, chip performance needs to be verified by adjusting the discharge time of the supply voltage. Adjusting the discharge time relies on discharge resistors with different resistance values. This embodiment uses multiple parallel discharge paths 11 and a control unit 2 to control the switching elements, thereby controlling the on / off states of different switching elements to activate one or more of the discharge paths 11. This allows for rapid adjustment of the discharge time without the need for manual soldering and changing the discharge resistor values, greatly simplifying the operation process and avoiding the hassle and time waste associated with manually changing resistors. This provides convenience for chip power-on / off redundancy testing and effectively improves chip timing debugging efficiency. It is understood that the number of discharge paths 11 can be flexibly set according to testing requirements.

[0025] In one embodiment, the discharge path 11 includes a discharge resistor (e.g., Figure 1 The circuit consists of R1, R2, R3 and a switching element, which is a field-effect transistor. One end of the bleed resistor is connected to the power supply unit 3, and the other end is connected to the drain of the field-effect transistor. The source of the field-effect transistor is grounded, and the gate is connected to the control unit 2.

[0026] Specifically, the bleeder resistor is the core component for discharging the supply voltage and adjusting the discharge time. Different resistance values ​​correspond to different discharge times. It consumes residual charge in the circuit through its own resistance characteristics, ensuring the power-down sequence meets test requirements. Considering the requirements for the response speed and stability of the discharge path 11 in the chip's power-up redundancy test, the field-effect transistor (FET) has the characteristics of fast switching speed and low power consumption, enabling rapid response to the software control commands of the control unit 2. Therefore, the switching element is designed as a FET, and the connection relationship between the bleeder resistor, the FET, and the control unit 2 is clearly defined to ensure a clear current path, facilitating circuit design and debugging. This allows the bleeder resistor to accurately participate in the discharge process under the control of the switching element, achieving rapid adjustment of the discharge time. It is understandable that the bleeder resistor can be selected with a corresponding resistance value according to different discharge time requirements.

[0027] In one embodiment, a bias resistor (e.g., a bias resistor) is also connected between the source and gate of the field-effect transistor. Figure 1 (R4, R5, R6 in the text).

[0028] Specifically, this embodiment, by adding a bias resistor, can provide a suitable bias voltage to the gate of the field-effect transistor (FET), enabling the FET to operate in a suitable on or off state. This avoids malfunctions caused by unstable gate voltage, effectively improving the stability of the FET's operation. Consequently, it ensures the accuracy of the on / off control of the discharge path 11, guarantees the normal operation of the power discharge circuit during chip power-on / off redundancy testing, reduces test errors caused by FET malfunctions, and ensures the accuracy of chip timing debugging results.

[0029] In one embodiment, a bidirectional breakdown diode is also connected between the source and gate of the field-effect transistor.

[0030] Specifically, this embodiment connects a bidirectional breakdown diode. When an excessively high voltage occurs between the source and gate of the field-effect transistor (FET), the bidirectional breakdown diode will break down and conduct, clamping the excessive voltage within a certain range. This protects the FET from damage by excessive voltage, extends the FET's lifespan, and also improves the anti-interference capability and reliability of the entire power discharge circuit. This ensures that the power discharge circuit can still operate stably in complex test environments, providing a guarantee for the continuous testing of chip power-on and power-off redundancy.

[0031] In one embodiment, the gate of the field-effect transistor has a built-in resistor.

[0032] Specifically, this embodiment uses a built-in resistor to limit the current flowing into the gate of the field-effect transistor (FET), preventing excessive current from damaging the FET gate. The built-in resistor also suppresses parasitic gate oscillations, reducing interference signals' impact on the FET's operating state. This allows the FET to respond more stably and accurately to the control signals of the control unit 2, ensuring the on / off control accuracy of the discharge path 11. Furthermore, it improves the performance of the power discharge circuit in chip power-on / off redundancy testing, ensuring the accuracy and speed of discharge time adjustment.

[0033] In one embodiment, the control unit 2 is an MCU chip U14.

[0034] Specifically, this embodiment uses an MCU chip U14 as the control unit 2. Control commands can be input to it through software programs. The MCU chip U14 can accurately control the switching state of each switching element according to the commands, realizing flexible control of the on / off state of the discharge path 11, and meeting the adjustment requirements for different discharge times in the chip power-on and power-off redundancy test. At the same time, the MCU chip U14 is small in size, which makes it easy to integrate into the power discharge circuit, reducing the overall circuit size and design complexity. This provides the possibility for the miniaturization and integration of the power discharge circuit, further improving the practicality of the chip testing equipment and adapting to the testing scenarios of chip development and verification.

[0035] In one embodiment, the MCU chip U14 is provided with several general-purpose input / output pins, and multiple switching elements are respectively connected to different general-purpose input / output pins of the MCU chip U14.

[0036] Specifically, the general-purpose input / output pins of the MCU chip U14 can provide independent and stable control signal outputs. By connecting multiple switching elements to different pins, the MCU chip U14 can independently control each switching element through software instructions, thereby achieving individual control over the on / off state of each discharge path 11. This independent control method increases the flexibility of the discharge resistor combination, and can accurately select one or more discharge paths 11 to conduct according to the specific discharge time requirements of the chip's power-on / off redundancy test. This further enhances the adaptability of the power discharge circuit to different test scenarios, without the need for manual circuit modification, and provides more convenience for chip timing debugging.

[0037] In one embodiment, the MCU chip U14 is model STM32H523VCT6.

[0038] Specifically, this model is selected to meet the performance requirements of the control core in the power-on / off redundancy test of the chip. During the test, the state of the discharge path 11 needs to be quickly adjusted by software instructions to change the discharge time. The STM32H523VCT6 MCU chip U14 has the advantages of high performance, low power consumption and rich peripheral interfaces. It can quickly receive and process software control instructions, ensuring that the switching elements respond in a timely manner and avoiding the impact of instruction processing delay on the efficiency of discharge time adjustment. At the same time, its market-proven stability can ensure continuous and reliable operation during long-term testing, reduce test interruptions caused by control unit failures, and further improve the chip timing debugging efficiency.

[0039] In addition, this utility model embodiment also provides a power supply device for chip testing, including the power discharge circuit as described above, and also includes a power supply unit 3 and an energy storage capacitor C2. The output terminal of the power supply unit 3 is connected to one end of the energy storage capacitor C2 and the discharge unit 1, and is used to connect the chip under test. The other end of the energy storage capacitor C2 is grounded.

[0040] Specifically, this power supply device is designed for testing during the chip development and verification phase. In chip testing, a stable power supply is required to meet the chip power-on timing requirements, and a reliable discharge function is needed to adjust the discharge time during power-on and power-off redundancy testing. Therefore, the power discharge circuit is combined with the power supply unit 3 and the energy storage capacitor C2 to form a complete test power supply solution. No additional discharge equipment is required, which simplifies the configuration of test equipment.

[0041] In this embodiment, through the above structural combination, the power supply unit 3 can provide a stable power supply to the chip under test, meeting the chip power-on timing requirements and operational needs; the energy storage capacitor C2 can store electrical energy and release it to maintain voltage stability when the output voltage of the power supply unit 3 fluctuates, ensuring stable chip operating voltage and avoiding voltage fluctuations affecting test results; and the power discharge circuit can control the combination of discharge paths through software instructions, quickly adjust the discharge time, meet the power-on and power-off redundancy test requirements, and eliminate the need for manual disassembly and reassembly of the discharge resistor, providing convenience for chip testing, and improving the practicality and reliability of the power supply device used for chip testing, thus helping to improve the efficiency of chip development and verification.

[0042] In one embodiment, the power supply unit 3 includes a DC-DC voltage converter U1, an input filter capacitor C1, a pull-up resistor R9, an energy storage inductor L1, a first voltage divider resistor R7, and a second voltage divider resistor R8. The input voltage terminal of the DC-DC voltage converter U1 is used to connect to a DC power supply and is connected to one end of the input filter capacitor C1 and one end of the pull-up resistor R9. The other end of the input filter capacitor C1 is grounded. The other end of the pull-up resistor R9 is connected to the enable terminal of the DC-DC voltage converter U1. The switching terminal of the DC-DC voltage converter U1 is connected to one end of the energy storage inductor L1. The other end of the energy storage inductor L1 is connected to one end of the first voltage divider resistor R7 and the energy storage capacitor C2, and is used to connect to the chip under test. The other end of the first voltage divider resistor R7 is connected to the feedback terminal of the DC-DC voltage converter U1 and one end of the second voltage divider resistor R8. The other end of the second voltage divider resistor R8 is grounded.

[0043] Specifically, the structure of the power supply unit 3 is adapted to the requirements of multi-channel power supply stability and accuracy in chip testing. The chip power-on / off redundancy test requires a stable power supply to ensure test accuracy. Therefore, an input filter capacitor C1 is designed to filter impurity signals in the input DC power supply and provide a stable input for the DC voltage converter U1. A pull-up resistor R9 ensures that the enable terminal of the DC voltage converter U1 is at a high level, ensuring its stable operation and avoiding power interruption. An energy storage inductor L1 works with the DC voltage converter U1 to realize voltage conversion and output multiple stable voltages required by the chip. The first voltage divider resistor R7 and the second voltage divider resistor R8 form a feedback circuit, which samples the output voltage in real time and feeds it back to the DC voltage converter U1, so that it adjusts the output according to the feedback to ensure voltage accuracy and form a complete and stable power supply structure, providing reliable power supply support for chip testing. In this embodiment, through the structural design of the power supply unit 3, the input filter capacitor C1 filters the input DC power supply, removes impurity signals, and provides a clean and stable input voltage for the DC voltage converter U1; the pull-up resistor R9 ensures that the enable terminal of the DC voltage converter U1 is always at a high level, ensuring its normal operation and avoiding power interruption due to abnormal enable terminal signal, which would affect chip testing; the energy storage inductor L1 and the DC voltage converter U1 work together to achieve efficient voltage conversion, accurately outputting the multiple voltages required by the chip under test, and meeting the chip power-on timing requirements; the voltage divider circuit composed of the first voltage divider resistor R7 and the second voltage divider resistor R8 can sample the output voltage in real time and feed the signal back to the DC voltage converter U1, enabling it to adjust the output voltage in a timely manner, ensuring stable and high-precision output voltage, providing reliable power supply for the chip under test, avoiding the impact of unstable power supply on test results, further improving the reliability of the power supply device used for chip testing, and ensuring the smooth progress of chip power-on redundancy testing.

[0044] The above examples are merely illustrative of the technical content of this utility model to facilitate reader understanding, but do not imply that the implementation of this utility model is limited to these embodiments. Any technical extensions or re-creations made based on this utility model are protected by this utility model. The scope of protection of this utility model is defined by the claims.

Claims

1. A power discharge circuit, characterized in that, include: A discharge unit and a control unit; one end of the discharge unit is connected to a power supply unit, and the other end is connected to the control unit; the discharge unit includes multiple discharge paths arranged in parallel, and a switching element is provided in the discharge path; the control unit is connected to the switching element to control the switching of the switching element to realize the opening and closing of the discharge path.

2. The power discharge circuit according to claim 1, characterized in that, The discharge path includes a discharge resistor and the switching element, which is a field-effect transistor. One end of the discharge resistor is connected to the power supply unit, and the other end is connected to the drain of the field-effect transistor. The source of the field-effect transistor is grounded, and the gate is connected to the control unit.

3. The power discharge circuit according to claim 2, characterized in that, A bias resistor is also connected between the source and gate of the field-effect transistor.

4. A power discharge circuit according to claim 2, characterized in that, A bidirectional breakdown diode is also connected between the source and gate of the field-effect transistor.

5. A power discharge circuit according to claim 2, characterized in that, The gate of the field-effect transistor has a built-in resistor.

6. The power discharge circuit according to claim 1, characterized in that, The control unit is an MCU chip.

7. A power discharge circuit according to claim 6, characterized in that, The MCU chip has several general-purpose input / output pins, and the multiple switching elements are respectively connected to different general-purpose input / output pins of the MCU chip.

8. A power discharge circuit according to claim 6, characterized in that, The MCU chip is model STM32H523VCT6.

9. A power supply device for chip testing, comprising a power discharge circuit as described in any one of claims 1-8, further comprising a power supply unit and an energy storage capacitor, wherein the output terminal of the power supply unit is connected to one end of the energy storage capacitor and the discharge unit, and is used to connect to the chip under test, and the other end of the energy storage capacitor is grounded.

10. A power supply device for chip testing according to claim 9, characterized in that, The power supply unit includes a DC-DC voltage converter, an input filter capacitor, a pull-up resistor, an energy storage inductor, a first voltage divider resistor, and a second voltage divider resistor. The input voltage terminal of the DC-DC voltage converter is connected to a DC power source and is connected to one end of the input filter capacitor and one end of the pull-up resistor. The other end of the input filter capacitor is grounded. The other end of the pull-up resistor is connected to the enable terminal of the DC-DC voltage converter. The switching terminal of the DC-DC voltage converter is connected to one end of the energy storage inductor. The other end of the energy storage inductor is connected to one end of the first voltage divider resistor and the energy storage capacitor, and is used to connect to the chip under test. The other end of the first voltage divider resistor is connected to the feedback terminal of the DC-DC voltage converter and one end of the second voltage divider resistor. The other end of the second voltage divider resistor is grounded.

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