A low-noise amplification circuit based on terahertz communication

Abstract

The utility model relates to the technical field of radio frequency integrated circuit design, concretely relates to a low noise amplifier circuit based on terahertz communication, including input matching network, first stage amplifier circuit, second stage amplifier circuit and third stage amplifier circuit that are connected in series along signal path in proper order, first stage amplifier circuit includes first transistor, and the source of first transistor is grounded through a source inductance (L1), constitutes source degeneration structure, second stage amplifier circuit includes second transistor, and the source of second transistor is grounded, third stage amplifier circuit includes third transistor, and the source of third transistor is grounded, the utility model discloses through adopting three -stage common source cascade topology, and the synergic design of input matching network and first transistor source ground inductance is helped, has optimized the input matching and noise matching of circuit in broadband range, has effectively eased the performance deterioration that the best noise matching point of transistor shifts with frequency.

Description

Technical Field

[0001] This utility model relates to the field of radio frequency integrated circuit design technology, specifically to a low-noise amplifier circuit based on terahertz communication. Background Technology

[0002] As wireless communication technology evolves towards sixth generation (6G), high-frequency spectrum resources have become a key support for achieving ultra-high-speed data transmission. Among them, the 20-37 GHz band, as an important component of millimeter-wave communication, combines the advantages of large bandwidth capacity and high equipment maturity, and has become the core front-end frequency band for 5G millimeter-wave systems and future terahertz communication links. This band not only provides tens of GHz of continuous available bandwidth for high-throughput communication, but also significantly improves spectrum efficiency through high-order modulation techniques (such as 64 / 256-QAM). It is widely used in high-speed short-range transmission, data center interconnection, and mobile terminal access scenarios, and serves as an important bridge connecting existing millimeter-wave technology and future terahertz communication systems.

[0003] However, achieving stable and low-noise signal amplification across the wide 20-37 GHz band presents significant challenges. Due to the physical characteristics of semiconductor devices, the optimal noise matching point of a transistor shifts significantly with frequency, making it difficult for conventional low-noise amplifiers to maintain uniform noise performance across the entire frequency band. Simultaneously, parasitic parameters in the matching circuit, dielectric losses, and transmission line radiation deteriorate sharply with increasing frequency, further raising the system's noise floor and ultimately limiting receiver sensitivity and the reliability of higher-order modulation and demodulation.

[0004] Therefore, how to flatten the noise figure over a wide bandwidth has become a core challenge in the design of current high-frequency receiver circuits. Utility Model Content

[0005] To solve the above technical problems, this utility model provides a technical solution for a low-noise amplifier circuit based on terahertz communication.

[0006] The technical problem solved by this utility model can be achieved by the following technical solution: A low-noise amplifier circuit based on terahertz communication includes: an input matching network, a first-stage amplifier circuit, a second-stage amplifier circuit, and a third-stage amplifier circuit connected in series along the signal path. The first stage amplifier circuit includes a first transistor, the source of which is grounded through a source inductor, forming a source degradation structure; The second-stage amplifier circuit includes a second transistor, the source of which is grounded; The third-stage amplifier circuit includes a third transistor, the source of which is grounded.

[0007] Preferably, the input matching network includes: A first capacitor, the first end of which is connected to the signal input terminal; A first microstrip line, the first end of which is connected to the second end of the first capacitor, and the second end of which is connected to the first stage amplifier circuit; The second microstrip line has a first end connected between the first capacitor and the signal input terminal, and a second end grounded.

[0008] Preferably, the gate of the first transistor is connected to the output of the input matching network and is connected to the first gate bias voltage through a first bias resistor.

[0009] Preferably, the first-stage amplifier circuit further includes a first-stage matching network, which includes: A third microstrip line, the first end of which is connected to the drain of the first transistor; A fourth microstrip line, wherein the first end of the fourth microstrip line is connected to the second end of the third microstrip line; The second capacitor has its first end connected between the third microstrip line and the fourth microstrip line, and its second end connected to the second stage amplifier circuit.

[0010] Preferably, the gate of the second transistor is connected to the output of the first stage amplifier circuit and is connected to the second gate bias voltage through a second bias resistor.

[0011] Preferably, the second-stage amplifier circuit further includes a second-stage matching network, which includes: A fifth microstrip line, the first end of which is connected to the drain of the second transistor; A sixth microstrip line, wherein the first end of the sixth microstrip line is connected to the second end of the fifth microstrip line; The fourth capacitor has its first end connected between the fifth and sixth microstrip lines, and its second end connected to the third-stage amplifier circuit.

[0012] Preferably, the gate of the third transistor is connected to the output of the second stage amplifier circuit and is connected to the third gate bias voltage through a third bias resistor.

[0013] Preferably, the third-stage amplifier circuit further includes an output matching network, the output matching network comprising: A seventh microstrip line, the first end of which is connected to the drain of the third transistor; An eighth microstrip line, the first end of which is connected to the second end of the seventh microstrip line; The sixth capacitor has its first end connected between the seventh microstrip line and the eighth microstrip line, and its second end connected to the signal output terminal.

[0014] Preferably, it further includes a third-stage DC bias circuit, which is connected to the output matching network; The third-stage DC bias circuit includes: The third drain bias voltage is connected to the second end of the eighth microstrip line; The seventh capacitor has its first terminal connected between the third drain bias voltage and the eighth microstrip line, and its second terminal grounded.

[0015] Preferably, the first transistor, the second transistor, and the third transistor are all MOS transistors.

[0016] Beneficial effects: This utility model optimizes the input matching and noise matching of the circuit in the wide bandwidth by adopting a three-stage common-source cascaded amplifier circuit and by using the cooperative design of the input matching network and the source-grounded inductor of the first-stage transistor. It effectively alleviates the performance degradation caused by the frequency shift of the transistor's optimal noise matching point, thereby helping to obtain a flatter and better noise figure throughout the target frequency band. Attached Figure Description

[0017] Figure 1 This is a circuit diagram of a low-noise amplifier based on terahertz communication according to this utility model. Detailed Implementation

[0018] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0019] It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention.

[0021] Reference Figure 1 This utility model provides a low-noise amplifier circuit based on terahertz communication, comprising: an input matching network 1, a first-stage amplifier circuit 2, a second-stage amplifier circuit 3, and a third-stage amplifier circuit 4 connected in series along the signal path; The first stage amplifier circuit 2 includes a first transistor Q1, the source of the first transistor Q1 is grounded through a source inductor L1, forming a source degradation structure; The second-stage amplifier circuit 3 includes a second transistor Q2, the source of which is grounded; The third-stage amplifier circuit 4 includes a third transistor Q3, the source of which is grounded.

[0022] Specifically, in this embodiment of the invention, to address the problem of noise performance degradation caused by the frequency shift of the optimal noise matching point of the transistor in the 20-37GHz wideband, a three-stage cascaded common-source amplifier circuit is adopted. Through the collaborative design of the input matching network and the source degradation inductor of the first-stage transistor, the real part of the boosted input impedance is aligned with the optimal noise source impedance in the wideband, achieving synergistic optimization of noise matching and gain matching. This avoids the defects of traditional single matching structures in high-frequency broadband conditions, such as uneven noise performance and severe gain roll-off. It achieves a lower noise figure, good gain flatness, excellent receiving sensitivity, and optimized power consumption performance in the entire 20-37GHz band.

[0023] Specifically, the first-stage amplifier circuit 2 focuses on optimizing noise performance and input standing wave ratio (VSWR). By using a short-circuited microstrip line as a degenerate inductor at the source of its first-stage transistor Q1, it significantly improves circuit stability while moderately sacrificing the gain of this stage. The key function of this structure is to increase the real part of the transistor's input impedance from approximately 11Ω to approximately 36Ω, thereby significantly reducing the quality factor of the input loop. This impedance transformation effectively widens the matchable frequency band and lays the foundation for broadband design. More importantly, the boosted input impedance is closer to the transistor's optimal noise source impedance of approximately 73 + j52 ohms at 28GHz, making the system's noise matching and gain matching requirements more compatible across the entire frequency band.

[0024] Meanwhile, neither the second-stage amplifier circuit 3 nor the third-stage amplifier circuit 4 incorporates a source degradation inductor to maximize gain. Through an optimization strategy that performs maximum gain matching at different characteristic frequency points within the bandwidth, these two circuit stages effectively compensate for the gain loss introduced by the first stage and synergistically shape a flat and excellent frequency response characteristic of the overall amplifier in the 20 to 37 GHz frequency band.

[0025] Input matching network 1 is used to achieve impedance matching between the signal source and the first-stage amplifier circuit 2, thereby improving power transmission efficiency. The second-stage amplifier circuit 3 and the third-stage amplifier circuit 4 further optimize the in-band gain flatness while ensuring that the overall link has sufficient gain, thus fully meeting the requirements of terahertz communication front-end for high sensitivity, high linearity and wide bandwidth stability.

[0026] More specifically, in this embodiment of the present invention, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are all 0.12 × 12 μm. 2 The small-sized MOSFETs have a smaller gate width (12μm), which helps reduce the parasitic capacitance of the transistors, thus ensuring that they can maintain a high cutoff frequency and good gain in the high-frequency range of 20-37 GHz. At the same time, this size is physically easy to implement for precise layout, which helps to ensure the performance consistency among multiple transistors. In addition, the inherently low quiescent current of the small-sized transistors is consistent with the design strategy of reducing current density in the first-stage amplifier circuit 2 to prioritize noise optimization, effectively controlling the power consumption of the overall circuit.

[0027] It is evident that this device achieves the best balance between RF performance, process controllability, and power consumption, laying a solid hardware foundation for the entire broadband low-noise amplifier to achieve excellent high-frequency performance and stable mass production consistency.

[0028] In a preferred embodiment of this utility model, the input matching network 1 includes: The first capacitor C1, with its first terminal connected to the signal input terminal IN; The first microstrip line TL1 has its first end connected to the second end of the first capacitor C1, and its second end connected to the first stage amplifier circuit 2. The second microstrip line TL2 has its first end connected between the first capacitor C1 and the signal input terminal IN, and its second end grounded.

[0029] Specifically, in this embodiment of the invention, the input matching network 1 constructs a low-Q broadband matching structure through the coordinated operation of the first capacitor C1, the first microstrip line TL1, and the second microstrip line TL2. The first capacitor C1 and the first microstrip line TL1, connected in series, together constitute the impedance transformation body, used to smoothly transform the input impedance (e.g., real part 36Ω) raised after source degradation of the first-stage transistor to a system characteristic impedance close to 50Ω, thereby achieving good input return loss over a wide bandwidth. The second microstrip line TL2, connected in parallel, acts as a parallel stub, further performing broadband compensation and frequency response shaping on the imaginary part of the input impedance, optimizing the matching effect in the high-frequency band.

[0030] Through the above design, the input matching network 1 effectively balances the requirements of noise matching and gain matching in the full frequency band of 20–37 GHz. It ensures that the optimal noise source impedance is as close as possible to the input conjugate impedance to reduce the noise figure, while also ensuring sufficient signal transmission. Ultimately, it achieves a balance between low noise, high gain flatness, and good input VSWR.

[0031] In a preferred embodiment of the present invention, the gate of the first transistor Q1 is connected to the second end of the first microstrip line TL1, and is connected to the first gate bias voltage Vg1 through the first bias resistor R1.

[0032] Specifically, in this embodiment of the invention, the gate bias of the first-stage amplifier circuit 2 adopts a high-resistance resistor feeding scheme, and the first gate bias voltage Vg1 is connected to the gate of the first transistor Q1 through the first bias resistor R1. This design utilizes the high impedance characteristics of the resistor to the radio frequency signal to effectively block the leakage of radio frequency energy to the bias network, significantly reducing the additional noise introduced by the bias path, thereby helping to achieve a lower overall noise figure.

[0033] In a preferred embodiment of the present invention, the first-stage amplifier circuit 2 further includes a first-stage matching network 5, which includes: The third microstrip line TL3, the first end of which is connected to the drain of the first transistor Q1; The fourth microstrip line TL4, the first end of which is connected to the second end of the third microstrip line TL3; The second capacitor C2 has its first end connected between the third microstrip line TL3 and the fourth microstrip line TL4, and its second end connected to the second stage amplifier circuit 3.

[0034] Specifically, in this embodiment of the invention, the first interstage matching network 5 adopts a T-shaped network structure composed of a third microstrip line TL3, a fourth microstrip line TL4, and a second capacitor C2. This structure is primarily used to achieve efficient signal transmission and impedance transformation between the first-stage amplifier circuit 2 and the second-stage amplifier circuit 3. The series-connected third microstrip line TL3 and fourth microstrip line TL4 together constitute the impedance transformation body, used to gradually reduce the high output impedance of the first-stage transistor Q1 to near the input impedance of the second-stage transistor Q2, thereby improving interstage power transmission efficiency. The parallel-connected second capacitor C2 serves as DC blocking and resonance compensation. By working in conjunction with the distributed parameters of the microstrip lines, it effectively absorbs parasitic capacitance in the circuit and optimizes the phase characteristics at the high end of the frequency band, thereby expanding the operating bandwidth of the interstage matching.

[0035] Through the above design, the first-stage inter-matching network 5 significantly improves the flatness of signal transmission across the 20–37 GHz full-bandwidth range. It effectively suppresses gain fluctuations caused by impedance mismatch and retains the low-noise characteristics obtained from the pre-amplification stage to the maximum extent, providing key support for the overall amplifier to achieve high gain, wide bandwidth and stable output.

[0036] In addition, as a preferred embodiment of the present invention, a first-stage DC bias circuit is also included, which is connected to the first-stage inter-matching network 5.

[0037] Accordingly, the first-stage DC bias circuit includes: The first drain bias voltage VCC1 is connected to the second terminal of the fourth microstrip line TL4; The third capacitor C3 has its first terminal connected between the first drain bias voltage VCC1 and the fourth microstrip line TL4, and its second terminal grounded.

[0038] Specifically, since the fourth microstrip line TL4 exhibits high impedance characteristics in the radio frequency path, its second end can serve as an ideal DC feed node, referring to... Figure 1 In this embodiment of the invention, by directly feeding the first drain bias voltage VCC1 into the second end of the fourth microstrip line TL4, the high radio frequency impedance characteristics of the microstrip line at approximately one-quarter wavelength in the 20-37GHz operating frequency band are fully utilized.

[0039] This design minimizes the impact of the DC bias path on the main RF signal path: the high-impedance microstrip line effectively blocks the leakage of RF energy towards the bias power supply, ensuring efficient transfer of signal energy to the second stage; simultaneously, the parallel third capacitor C3 provides a low-impedance path to ground for any residual RF components that may leak, further enhancing the RF isolation of the bias network and effectively suppressing external interference introduced through the power line; ultimately, this DC bias scheme achieves both stable DC power supply and excellent RF isolation without introducing additional active components, providing an important guarantee for the amplifier to maintain high gain and stable operation over a wide bandwidth.

[0040] In a preferred embodiment of the present invention, the gate of the second transistor Q2 is connected to the second terminal of the second capacitor C2, and is connected to the second gate bias voltage Vg2 through the second bias resistor R2.

[0041] Specifically, in this embodiment of the present invention, the gate bias of the second stage amplifier circuit 3 also adopts a high resistance resistor feeding scheme, and the second gate bias voltage Vg2 is connected to the gate of the second transistor Q2 through the second bias resistor R2.

[0042] This design continues the low-noise concept of the pre-amplifier bias, utilizing the high impedance characteristics of the resistor to RF signals to effectively prevent RF energy leakage through the bias path and avoid the introduction of additional noise. Simultaneously, this bias structure provides a stable and controllable operating point for the second transistor Q2, enabling it to operate in the optimal linear region and fully unleash its gain potential, compensating for the gain sacrificed in the first stage due to noise optimization. Ultimately, this design ensures the low noise contribution of the second stage while guaranteeing a balance between high gain, good linearity, and low noise figure for the overall amplifier within the 20-37GHz frequency band.

[0043] In a preferred embodiment of the present invention, the second-stage amplifier circuit 3 further includes a second-stage inter-stage matching network 6, which includes: The fifth microstrip line TL5, the first end of which is connected to the drain of the second transistor Q2; The sixth microstrip line TL6, the first end of which is connected to the second end of the fifth microstrip line TL5; The fourth capacitor C4 has its first end connected between the fifth microstrip line TL5 and the sixth microstrip line TL6, and its second end connected to the third-stage amplifier circuit 4.

[0044] Specifically, in this embodiment of the invention, the second-stage inter-matching network 6 adopts a T-shaped topology that is completely identical to the first-stage inter-matching network 5, consisting of a fifth microstrip line TL5, a sixth microstrip line TL6, and a fourth capacitor C4. This network continues the design concept of the preceding stage matching, achieving impedance transformation through series microstrip lines, gradually reducing the relatively high output impedance of the second-stage transistor Q2 to near the input impedance of the third-stage transistor Q3, ensuring efficient signal transmission; the parallel fourth capacitor C4 also serves as DC blocking and resonance compensation, expanding the working bandwidth of the inter-stage matching by optimizing the high-frequency phase response.

[0045] Through this symmetrical design, the second-stage interstage matching network 6 effectively suppresses gain fluctuations caused by interstage mismatch while maintaining impedance continuity throughout the entire link, providing the optimal drive signal for the third-stage amplifier circuit 4. Ultimately, this unified matching structure not only simplifies the circuit design and optimization process but also ensures that the overall amplifier exhibits highly consistent gain flatness and excellent stability across the entire 20-37 GHz frequency band.

[0046] Considering the need to provide a stable DC bias for the second-stage amplifier circuit 3 with minimal impact on the RF path, this embodiment of the invention also includes a second-stage DC bias circuit, which is connected to the second-stage inter-matching network 6.

[0047] The second-stage DC bias circuit includes: The second drain bias voltage VCC2 is connected to the second terminal of the sixth microstrip line TL6; The fifth capacitor C5 has its first terminal connected between the second drain bias voltage VCC2 and the sixth microstrip line TL6, and its second terminal grounded.

[0048] Specifically, in this embodiment of the invention, the second-stage DC bias circuit adopts the same feeding strategy as the first stage. By connecting the second drain bias voltage VCC2 to the second terminal of the sixth microstrip line TL6, it cleverly utilizes the high RF impedance characteristics of the microstrip line in the target frequency band, ensuring that the impact of the DC bias path on the main RF signal path is minimized. This efficiently provides the drain operating voltage required by the second transistor Q2 and effectively blocks the leakage of RF energy to the bias network. The parallel fifth capacitor C5 also serves as a high-frequency decoupling capacitor, providing a path to ground for any potentially leaked RF components, further enhancing the RF isolation of the bias network and suppressing potential power supply interference. Ultimately, this symmetrical bias design ensures that the second-stage amplifier circuit achieves optimal operating conditions while maintaining the stability of the overall link gain and the purity of the signal, making it one of the key supports for the overall amplifier to achieve excellent wideband performance.

[0049] In a preferred embodiment of the present invention, the gate of the third transistor Q3 is connected to the second terminal of the fourth capacitor C4, and is connected to the third gate bias voltage Vg3 through the third bias resistor R3.

[0050] Specifically, in this embodiment of the invention, the gate bias of the third-stage amplifier circuit 4 adopts the same high-resistance resistor feeding scheme as the first and second stages. The third gate bias voltage Vg3 is fed into the gate of the third transistor Q3 through the third bias resistor R3. This design maintains the consistency of the bias structure of the entire circuit. By utilizing the high impedance characteristics of the resistor to the RF signal, it effectively prevents the leakage of the final stage amplified signal through the bias path, ensuring that the accumulated gain and optimized noise performance of the first two stages can be fully utilized. At the same time, this bias structure provides a stable and independently controllable static operating point for the output stage transistor, enabling it to achieve maximum output power and linearity while maintaining the power consumption balance of the overall circuit. Ultimately, this design ensures the driving capability and signal integrity at the end of the amplification chain, enabling the overall circuit to achieve a balance of high gain, good linearity, and stable output across the entire 20-37GHz frequency band.

[0051] In a preferred embodiment of this utility model, the third-stage amplifier circuit 4 further includes an output matching network 7, which comprises: The seventh microstrip line TL7, the first end of which is connected to the drain of the third transistor Q3; The eighth microstrip line TL8, the first end of which is connected to the second end of the seventh microstrip line TL7; The sixth capacitor C6 has its first end connected between the seventh microstrip line TL7 and the eighth microstrip line TL8, and its second end connected to the signal output terminal OUT.

[0052] Specifically, in this embodiment of the invention, the output matching network 7 adopts a T-shaped topology consistent with the inter-stage matching network, consisting of a seventh microstrip line TL7, an eighth microstrip line TL8, and a sixth capacitor C6. This network efficiently transforms the relatively high output impedance of the third-stage transistor Q3 to a standard 50-ohm load impedance, ensuring that the amplified RF signal can be transmitted to subsequent circuits or antennas with minimal reflection.

[0053] Among them, the seventh microstrip line TL7 and the eighth microstrip line TL8 connected in series together complete the main impedance transformation function. Through the precise design of the microstrip line length and width, the real part of the output impedance is matched. The sixth capacitor C6 connected in parallel provides the necessary DC blocking function, and at the same time forms resonance with the equivalent inductance of the microstrip line to compensate for the phase distortion in the high-frequency band and effectively expand the output matching bandwidth.

[0054] Through this design, the output matching network 7 achieves excellent output return loss in the 20-37GHz full-band, significantly improving signal transmission efficiency while ensuring the flatness of the overall amplifier gain response, ultimately ensuring that the RF signal amplified by three stages can be output to the load completely and with low distortion.

[0055] Because an efficient and well-isolated DC feed is required for the output stage, a third-stage DC bias circuit is also included, which is connected to the output matching network 7.

[0056] The third-stage DC bias circuit includes: The third drain bias voltage VCC3 is connected to the second terminal of the eighth microstrip line TL8; The seventh capacitor C7 has its first terminal connected between the third drain bias voltage VCC3 and the eighth microstrip line TL8, and its second terminal grounded.

[0057] Specifically, in this embodiment of the present invention, the third-stage DC bias circuit continues the mature and efficient power supply scheme of the first two stages. By connecting the third drain bias voltage VCC3 to the second end of the eighth microstrip line TL8, the high RF impedance characteristics of the microstrip line at approximately one-quarter wavelength in the 20-37GHz frequency band are fully utilized. The parallel seventh capacitor C7 serves as a high-frequency decoupling capacitor, which also provides a low-impedance path to ground for any residual RF leakage components, further enhancing the bias isolation and purifying the power quality.

[0058] This unified bias architecture, spanning all three stages, systematically solves the problems of stable power supply and RF isolation for each stage of the amplifier circuit without the need for additional complex circuitry. This lays a solid foundation for the entire broadband low-noise amplifier to achieve high gain, high stability, and excellent noise performance across the entire frequency band.

[0059] In a preferred embodiment of this utility model, the resistance values ​​of the first bias resistor R1, the second bias resistor R2, and the third bias resistor R3 are all 5KΩ.

[0060] Specifically, in this embodiment of the invention, a gate bias resistor with a resistance of 5KΩ is uniformly configured for all three-stage amplifier circuits. This design achieves the best balance between circuit performance and physical implementation. On the one hand, this resistance value can provide a sufficiently high impedance path for RF signals, effectively suppressing leakage of signals from each amplification stage through the bias circuit, thereby avoiding noise figure deterioration and gain loss.

[0061] On the other hand, this resistance value ensures RF isolation while also meeting the basic linearity requirements of the bias circuit, and avoids the chip area occupation problem caused by using a large-size inductor.

[0062] This standardized bias scheme not only simplifies circuit design and layout, but also ensures a high degree of consistency in the three-stage amplifier circuit in terms of operational stability and noise performance, providing an important guarantee for the overall amplifier to achieve excellent performance over a wide frequency band.

[0063] In summary, this invention employs a three-stage common-source cascaded topology. By introducing a source-degraded inductor and an input matching network in the critical first stage, the real part of the transistor's input impedance is increased from 11Ω to 36Ω. This successfully solves the core problem of balancing noise matching and gain matching across a wide bandwidth, ensuring that the optimal noise source impedance and input conjugate impedance are consistent across the entire frequency band. The subsequent two stages utilize a passive, degraded high-gain design, coupled with a unified T-type matching network and standardized bias structure. This effectively compensates for the gain of the preceding stage and achieves full-band response flattening while ensuring excellent RF isolation and low noise characteristics. Ultimately, it achieves a complete performance unification of low noise figure, high gain flatness, good linearity, and optimized power consumption within the 20-37GHz range, providing a high-performance solution for terahertz communication front-ends.

[0064] The above description is only a preferred embodiment of the present utility model and does not limit the implementation method and protection scope of the present utility model. Those skilled in the art should realize that all solutions obtained by equivalent substitutions and obvious changes made based on the description and illustrations of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A low-noise amplifier circuit based on terahertz communication, characterized in that, include: The input matching network (1), the first stage amplifier circuit (2), the second stage amplifier circuit (3) and the third stage amplifier circuit (4) are connected in series along the signal path. The first stage amplifier circuit (2) includes a first transistor (Q1), and the source of the first transistor (Q1) is grounded through a source inductor (L1), forming a source degradation structure; The second stage amplifier circuit (3) includes a second transistor (Q2), the source of which is grounded; The third-stage amplifier circuit (4) includes a third transistor (Q3), the source of which is grounded.

2. The low-noise amplifier circuit based on terahertz communication according to claim 1, characterized in that, The input matching network (1) includes: The first capacitor (C1) has its first terminal connected to the signal input terminal (IN). The first microstrip line (TL1) has its first end connected to the second end of the first capacitor (C1), and its second end connected to the first stage amplifier circuit (2). The second microstrip line (TL2) has its first end connected between the first capacitor (C1) and the signal input terminal (IN), and its second end grounded.

3. The low-noise amplifier circuit based on terahertz communication according to claim 1, characterized in that, The gate of the first transistor (Q1) is connected to the output of the input matching network (1) and is connected to the first gate bias voltage (Vg1) through the first bias resistor (R1).

4. The low-noise amplifier circuit based on terahertz communication according to claim 3, characterized in that, The first stage amplifier circuit (2) further includes a first stage inter-stage matching network (5), which includes: The third microstrip line (TL3) has its first end connected to the drain of the first transistor (Q1); A fourth microstrip line (TL4), the first end of which is connected to the second end of the third microstrip line (TL3); The second capacitor (C2) has its first end connected between the third microstrip line (TL3) and the fourth microstrip line (TL4), and its second end connected to the second stage amplifier circuit (3).

5. A low-noise amplifier circuit based on terahertz communication according to claim 1, characterized in that, The gate of the second transistor (Q2) is connected to the output of the first stage amplifier circuit (2) and is connected to the second gate bias voltage (Vg2) through the second bias resistor (R2).

6. A low-noise amplifier circuit based on terahertz communication according to claim 5, characterized in that, The second-stage amplifier circuit (3) further includes a second-stage inter-matching network (6), which includes: The fifth microstrip line (TL5) has its first end connected to the drain of the second transistor (Q2); The sixth microstrip line (TL6) has its first end connected to the second end of the fifth microstrip line (TL5); The fourth capacitor (C4) has its first end connected between the fifth microstrip line (TL5) and the sixth microstrip line (TL6), and its second end connected to the third-stage amplifier circuit (4).

7. A low-noise amplifier circuit based on terahertz communication according to claim 1, characterized in that, The gate of the third transistor (Q3) is connected to the output of the second stage amplifier circuit (3) and is connected to the third gate bias voltage (Vg3) through the third bias resistor (R3).

8. A low-noise amplifier circuit based on terahertz communication according to claim 7, characterized in that, The third-stage amplifier circuit (4) further includes an output matching network (7), which comprises: The seventh microstrip line (TL7) has its first end connected to the drain of the third transistor (Q3); The eighth microstrip line (TL8) has its first end connected to the second end of the seventh microstrip line (TL7); The sixth capacitor (C6) has its first end connected between the seventh microstrip line (TL7) and the eighth microstrip line (TL8), and its second end connected to the signal output terminal (OUT).

9. A low-noise amplifier circuit based on terahertz communication according to claim 8, characterized in that, It also includes a third-stage DC bias circuit, which is connected to the output matching network (7); The third-stage DC bias circuit includes: The third drain bias voltage (VCC3) is connected to the second terminal of the eighth microstrip line (TL8); The seventh capacitor (C7) has its first terminal connected between the third drain bias voltage (VCC3) and the eighth microstrip line (TL8), and its second terminal grounded.

10. A low-noise amplifier circuit based on terahertz communication according to claim 1, characterized in that, The first transistor (Q1), the second transistor (Q2), and the third transistor (Q3) are all MOS transistors.

Images