Capacitively coupled chopper instrument amplifier

Abstract

The application discloses a high input impedance, low noise capacitor coupling chopper instrument amplifier, which comprises a main amplifier, a positive feedback loop, a pre-charge circuit and a direct current servo loop. in The application adopts the positive feedback loop and the pre-charge technology, reduces the current flowing into the input capacitor C in by current compensation, realizes the improvement of the input impedance, shares one chopper by the positive feedback loop and the negative feedback loop, reduces the use of one chopper, reduces the layout area, and uses the pre-charge circuit to take the amplifier with smaller power consumption as a buffer to reduce the power consumption of the system. The multi-rate duty cycle resistance is used to replace the pseudo resistance as the large resistance of the integrator, and the noise introduced by the direct current servo loop is further reduced. The application has good performance and the advantages of high input impedance, low noise and low power consumption.

Description

Technical Field

[0001] This utility model belongs to the field of integrated circuit technology, specifically relating to a capacitively coupled chopper instrumentation amplifier. Background Technology

[0002] Common human physiological signals include electrocardiogram (ECG), electroencephalogram (EEG), and electromyography (EMG). These signals are typically very weak, ranging from a few microvolts to a few millivolts, and their frequency range is below 1 kHz. These tiny signals are easily drowned out by noise, especially the 1 / f noise of the amplifier. Therefore, biosignal amplifiers have high requirements for noise performance. Currently, most wearable devices use dry electrodes to connect the human body and sensors. Compared to wet electrodes, dry electrodes offer a better user experience in terms of convenience and durability. Typical dry electrodes transmit signals through the stratum corneum and skin, with impedance ranging from hundreds of kilohms to tens of megahms, which exacerbates the partial pressure effect (PDE). PDE can lead to poor CMRR, a higher risk of motion artifacts, and reduced SNR. Therefore, to achieve better performance, the input impedance of the instrumentation amplifier needs to be greater than 1 GΩ.

[0003] Capacitively coupled chopper-stabilized instrumentation amplifiers have the following advantages in biosignal detection: (1) outstanding suppression of 1 / f noise and offset; (2) rail-to-rail input range can be achieved through capacitive coupling; (3) high common-mode rejection ratio can be achieved. Therefore, this structure is widely used in the analog front end of biosignals. However, after introducing the chopper circuit, the chopper and input capacitor at the input end of the amplifier form a switched capacitor structure, which reduces its equivalent input impedance. When introducing a DC servo loop structure to suppress electrode offset, an additional loop is added, which also increases the input reference noise of the amplifier. Utility Model Content

[0004] To address the problems existing in the prior art, this invention provides a capacitor-coupled chopper instrumentation amplifier with high input impedance and low noise. To address the input impedance reduction problem caused by chopper modulation technology, this invention employs a positive feedback loop and pre-charging technology, and through current compensation, reduces the input impedance reduction caused by the signal source to the input capacitor C. in The incoming current increases the input impedance. Furthermore, replacing the pseudo-resistor with a multi-rate duty-cycled resistor (MDCR) as the large resistor in the integrator reduces noise introduced by the DC servo loop. This invention exhibits excellent performance, with advantages of high input impedance, low noise, and low power consumption.

[0005] This invention includes a main amplifier, a positive feedback loop, a pre-charge circuit, a DC servo loop, and a low-pass filter.

[0006] The main amplifier includes: input capacitor C in1 and C in2 First stage amplifier G m1 DC blocking capacitors C1 and C2, second-stage amplifier G m2 Feedback resistor R f1 and R f2 Common-mode bias resistor R b1 and R b2 Second chopper CH2, zero-adjustment resistor R C1 and R C2 Miller compensation capacitor C C1 and C C2 The third chopper CH3, and the feedback capacitor C fb1 and C fb2 Among them, the first output port of the first chopper CH1 is connected to the input capacitor C. in1 The second port is connected to the input capacitor C. The second output port of the first chopper CH1 is connected to the input capacitor C. in2 The second port is connected to the input capacitor C. in1 The first port and the first stage amplifier G m1 Connect to the positive input port, and the input capacitor C in2 The first port and the first stage amplifier G m1 The inverting input port is connected. Feedback resistor R f1 The first port and the first stage amplifier G m1 The non-inverting input terminal is connected, and the feedback resistor R f1 The second port is connected to the first stage amplifier G. m1 The inverting output port is connected, and the feedback resistor R f2 The first port and the first stage amplifier G m1 The inverting input terminal is connected, and the feedback resistor R f2 The second port is connected to the first stage amplifier G. m1 The positive output port is connected to the first input port of the second chopper CH2. The first port of the DC blocking capacitor C1 is connected to the first input port of the second chopper CH2, and the second port of the DC blocking capacitor C1 is connected to the first stage amplifier G. m1 The inverting output port of the first stage amplifier G is connected to the second input port of the second chopper CH2, and the first port of the DC blocking capacitor C2 is connected to the second input port of the second chopper CH2. m1 The non-inverting output port is connected. The first output port of the second chopper CH2 is connected to the second-stage amplifier G. m2 The non-inverting input terminal is connected, and the second output port is connected to the second-stage amplifier G. m2 The inverting input terminal is connected to the second-stage amplifier G. m2The non-inverting output port of the amplifier is connected to the inverting input port VIN of the low-pass filter, and the second-stage amplifier G... m2 The inverting output port is connected to the non-inverting input port VIP of the low-pass filter. Common-mode bias resistor R b1 First port and second stage amplifier G m2 Connected to the non-inverting input terminal, common-mode bias resistor R b1 The second port is connected to the common-mode feedback signal V. CMFB Common-mode bias resistor R b2 First port and second stage amplifier G m2 The inverting input terminal is connected to the common-mode bias resistor R. b2 The second port is connected to the common-mode feedback signal V. CMFB Zero-adjustment resistor R C1 First port and second stage amplifier G m2 Connect the non-inverting input terminal to the zero-adjustment resistor R. C1 The second port is connected to the Miller compensation capacitor C. C1 The second port is connected to the Miller compensation capacitor C. C1 The first port and the second stage amplifier G m2 Connect the inverting output port to the zero-adjustment resistor R. C2 First port and second stage amplifier G m2 Connect the inverting input terminal to the zero-adjustment resistor R. C2 The second port is connected to the Miller compensation capacitor C. C2 The second port is connected to the Miller compensation capacitor C. C2 The first port and the second stage amplifier G m2 The non-inverting output port is connected. The first input port of the third chopper CH3 is connected to the second-stage amplifier G. m2 The inverting output port is connected to the second input port of the third chopper CH3, and the second input port of the second-stage amplifier G is connected to the second-stage amplifier G. m2 The positive output port of the third chopper CH3 is connected to the feedback capacitor C. fb1 The second port is connected to the third chopper CH3, and the second output port is connected to the feedback capacitor C. fb2 The second port is connected to the feedback capacitor C. fb1 The first port and the first stage amplifier G m1 The inverting input port is connected, and the feedback capacitor C is connected. fb2 The first port and the first stage amplifier G m1 Connect to the positive input port.

[0007] The positive feedback loop includes: positive feedback capacitor C pf1 The first port and the input capacitor C in1 The second port is connected to the positive feedback capacitor C. pf1的The second port is connected to the first output port of the third chopper CH3, and the positive feedback capacitor C pf2 The first port and the input capacitor C in2 The second port is connected to the positive feedback capacitor C. pf2 The second port is connected to the second output port of the third chopper CH3.

[0008] The pre-charge circuit includes: a first chopper CH1, a fifth chopper CH5, a sixth chopper CH6, a seventh chopper CH7, buffers Buf1 and Buf2, logic control switches S1 and S2, and a charging capacitor C. aux1 and C aux2 The non-inverting input pin V of the instrumentation amplifier inp Connected to the first input ports of the first chopper CH1 and the fifth chopper CH5, the inverting input pin V of the instrumentation amplifier inn It is connected to the second input ports of the first chopper CH1 and the fifth chopper CH5. The first output port of the first chopper CH1 is connected to the input capacitor C. in1 The second port of the first chopper CH7 is connected to the first output port of the seventh chopper CH7, and the second output port of the first chopper CH1 is connected to the input capacitor C. in2 The second port of the seventh chopper CH7 is connected to the second output port of the seventh chopper CH7. The input port of buffer Buf1 is connected to the first output port of the fifth chopper CH5, and the output port of buffer Buf1 is connected to the first input port of the sixth chopper CH6; the input port of buffer Buf2 is connected to the second output port of the fifth chopper CH5, and the output port of buffer Buf2 is connected to the second input port of the sixth chopper CH6. The first input terminal of the seventh chopper CH7 is connected to the first output terminal of the sixth chopper CH6 and the first port of the logic control switch S1; the second input terminal of the seventh chopper CH7 is connected to the second output terminal of the sixth chopper CH6 and the first port of the logic control switch S2. Charging capacitor C aux1 The first port is connected to the second port of the logic control switch S1, and the charging capacitor C aux1 The second port is connected to ground, and the charging capacitor C aux2 The first port is connected to the second port of the logic control switch S2, and the charging capacitor C aux2 The second port is connected to ground.

[0009] The DC servo loop includes: 2 integrating resistors R int1 and R int2 2 integrating capacitors C int1 and C int2 2 feedback capacitors C dsl1 and C dsl2 Amplifier G m3 And the fourth chopper CH4. Integrating resistor Rint1 First port and second stage amplifier G m2 The inverting output terminal is connected, and the integrating resistor R int2 First port and second stage amplifier G m2 The non-inverting output terminal of amplifier G is connected; m3 The non-inverting input terminal and the integrating resistor R int2 The second port, integrating capacitor C int2 The first port is connected; amplifier G m3 The inverting input terminal and the integrating resistor R int1 The second port, integrating capacitor C int1 The first port is connected; amplifier G m3 The non-inverting output terminal and the integrating capacitor C int1 The second port of the amplifier is connected to the first input port of the fourth chopper CH4; amplifier G m3 The inverting output terminal and the integrating capacitor C int2 The second port of the fourth chopper CH4 is connected to the second input port of the fourth chopper CH4. Feedback capacitor C dsl1 The first port and the first stage amplifier G m1 The non-inverting input port is connected, and the feedback capacitor C is connected. dsl1 The second port is connected to the first output port of the fourth chopper CH4; feedback capacitor C dsl2 The first port and the first stage amplifier G m1 The inverting input port is connected, and the feedback capacitor C is connected. dsl2 The second port is connected to the second output port of the fourth chopper CH4. The integrating resistor R... int1 and R int2 Each resistor is a multi-rate duty cycle resistor consisting of two polysilicon resistors R1 and R2, two logic control switches S3 and S4, and two capacitors C3 and C4. The first port of R1 is connected to the input pin V of the multi-rate duty cycle resistor. in Connect the following: the second port of R1 is connected to the first port of S3; the first port of C3 is connected to the second port of S3 and the first port of R2; the second port of C3 is connected to ground. The first port of S4 is connected to the second port of R2; the first port of C4 is connected to the second port of S4; and the output pin V of the multi-rate duty cycle resistor is connected to ground. out Connected, the second port of C4 is connected to ground.

[0010] The low-pass filter includes: two amplifiers A1 and A2, eight resistors R1 to R8, and four capacitors C1 to C4. The non-inverting input port VIP of the low-pass filter is connected to the first port of R1, and the second port of R1 is connected to the non-inverting input port of A1, the first port of C1, the first port of R3, and the first port of R7. The inverting input port VIN of the low-pass filter is connected to the first port of R2, and the second port of R2 is connected to the inverting input port of A1, the first port of C2, the first port of R4, and the first port of R8. The inverting output port of A1 is connected to the second port of C1, the second port of R3, and the first port of R5. The non-inverting output port of A1 is connected to the second port of C2, the second port of R4, and the first port of R6. The second port of R5 is connected to the inverting input port of A2 and the first port of C4, and the second port of R6 is connected to the non-inverting input port of A2 and the first port of C3. The inverting output of A2 is connected to the non-inverting output port VOP of the low-pass filter, the second port of C3, and the second port of R7. The non-inverting output of A2 is connected to the inverting output port VON of the low-pass filter, the second port of C4, and the second port of R8.

[0011] Preferably, the first-stage amplifier G m1 Amplifiers employing a common-source, common-gate structure based on inverters can achieve current multiplexing, reduce current branches, and lower power consumption.

[0012] First stage amplifier G m1 It includes: 5 PMOS transistors MP0 to MP4 and 5 NMOS transistors MN0 to MN4. The source of MP0 is connected to the power supply VDD, and the gate of MP0 is connected to the bias voltage V. BP1 The drain of MP0 is connected to the source of MP1 and MP2, G m1 The non-inverting input port V inp1 G is connected to the gates of MP1 and MN1. m1 Inverting input port V inn1 The gates of MP2 and MN2 are connected, and the gates of MP3 and MP4 are connected to the bias voltage V. BP2 Connected. G m1 The non-inverting output port V outp1 The drain of MP1 is connected to the drain of MP4 and MN4, the drain of MP1 is connected to the source of MP3, and the drain of MP2 is connected to the source of MP4. m1 The inverting output port V outn1 The drains of MN3 and MN4 are connected to the bias voltage VBN2. The source of MN3 is connected to the drain of MN1. The source of MN4 is connected to the drain of MN2. The sources of MN1 and MN2 are connected to the drain of MN0. The source of MN0 is connected to ground. The gate of MN0 is connected to the common-mode negative feedback voltage V.CMFB1 Connected.

[0013] Preferably, the second-stage amplifier G m2 Using a common-source amplifier with a current-source load can improve the amplifier's output swing.

[0014] Second stage amplifier G m2 Includes: 4 PMOS transistors MP5, MP6, MP7 and MP8; 5 NMOS transistors MN5, MN6, MN7, MN8 and MN9; and 2 common-mode negative feedback sampling resistors R. M1 and R M2 The source of MP5, MP6, MP7, and MP8 is connected to the power supply VDD, and the gate of MP5 and MP6 is connected to the bias voltage V. BP1 MP5 drain, R M1 The first port, the drain of MN5, and the second stage amplifier G m2 The inverting output port V outn2 Connected; the drain of MP6, R M2 The first port, the drain of MN6, and the second stage amplifier G m2 The non-inverting output port V outp2 Connected. R M1 R M2 The second port is connected to the gate of MN8; the sources of MN5, MN6, and MN7 are connected to ground GND; the gate of MN5 is connected to the gate of the second-stage amplifier G. m2 The non-inverting input port V inp2 Connected, the gate of MN6 is connected to the second-stage amplifier G. m2 Inverting input port V inn2 Connected, the gate of MN7 is connected to the bias voltage V BN1 The sources of MN8 and MN9 are connected to the drain of MN7; the drain and gate of MP7 are connected, and the gate of MP8 is connected to the drain of MN8; the gate of MN9 is connected to the reference voltage V. REF The drains of MN9 and MP8 are connected to the common-mode voltage output port V. CMFB .

[0015] Preferably, a symmetrical pseudo-resistor structure with MOSFETs in series is used, which can increase the resistance and reduce nonlinearity.

[0016] The feedback resistor R f1 and R f2 and common-mode bias resistor R b1 and R b2Each pseudo-resistor is composed of four PMOS transistors, M1 to M4. Pin 1 of the pseudo-resistor is connected to the gate and source of M1. The substrates of M1, M2, M3, and M4 are all connected to the drain of M2 and the source of M3. The gate and source of M2 are connected to the drain of M1. The gate and drain of M3 are connected to the source of M4. The gate and source of M4 are connected to pin 2 of the pseudo-resistor.

[0017] Technical features and effects of this utility model:

[0018] 1. Employing positive feedback loop and pre-charging technology, current compensation is used to reduce the signal source's current to the input capacitor C. in The incoming current increases the input impedance.

[0019] 2. In the positive feedback loop, through the positive feedback capacitor C pf1 With C pf2 The output signal is fed back to the input terminal directly through the third chopper CH3. The positive feedback loop and the negative feedback loop share the third chopper CH3, reducing the use of one chopper and reducing the layout area.

[0020] 3. Add capacitor C to the pre-charging circuit. aux1 and C aux2 And logic switches S1 and S2, when the first amplifier CH3 is in the chopper dead zone, switches S1 and S2 conduct to the input capacitor C. in1 and C in2 Charging can be performed by using a lower-power amplifier as a buffer, thereby reducing the system's power consumption.

[0021] 4. In the DC servo loop, the large resistor of the integrator adopts a multi-rate duty cycle resistor, which uses the time averaging effect to reduce the equivalent flicker noise of the MOS switch. This structure, together with the large resistor composed of a low-noise polysilicon resistor, can further reduce the contribution of noise. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the circuit structure of this utility model;

[0023] Figure 2 This is a schematic diagram of the pre-charging circuit in this utility model;

[0024] Figure 3 This is a schematic diagram of the control timing waveform of the pre-charging circuit in this utility model;

[0025] Figure 4 This is a schematic diagram of the first-stage amplifier provided by this utility model;

[0026] Figure 5 This is a schematic diagram of the second-stage amplifier provided by this utility model;

[0027] Figure 6 This is a schematic diagram of a pseudo-resistor provided by this utility model;

[0028] Figure 7 This is a schematic diagram of the multi-rate duty cycle resistor (MDCR) provided by this utility model;

[0029] Figure 8 This is a schematic diagram of the low-pass filter provided by this utility model;

[0030] Figure 9 This is a simulation diagram of the input impedance of this utility model;

[0031] Figure 10 This is a simulation diagram of the input reference noise of this utility model;

[0032] Figure 11 This is a simulation diagram of the transient output waveform provided by this utility model. Detailed Implementation

[0033] The technical solution of this utility model will now be described in detail with reference to the accompanying drawings and embodiments to facilitate a better understanding.

[0034] Figure 1 This is a schematic diagram of a capacitively coupled chopper instrumentation amplifier provided in an embodiment of the present invention. It mainly includes a main amplifier, a positive feedback loop, a pre-charge circuit, and a DC servo loop. The main amplifier primarily amplifies the input signal and uses chopper modulation technology to suppress signal noise and offset. The positive feedback loop and pre-charge circuit are used to increase the amplifier's input impedance, and the DC servo loop is used to suppress the amplifier's output voltage offset.

[0035] The main amplifier includes amplifier G m1 and G m2 Feedback resistor R f1 and R f2 DC blocking capacitors C1 and C2, second chopper CH2, common-mode bias resistor R b1 and R b2 Zero-adjustment resistor R C1 and R C2 Miller compensation capacitor C C1 and C C2 The third chopper CH3 and the feedback capacitor C fb1 and C fb2 .

[0036] The input signal is modulated by the first chopper CH1 and then passes through the input capacitor C of the main amplifier. in1 and C in2 When input to the first stage amplifier G m1 First stage amplifier G m1The positive output port is connected to the feedback resistor R. f2 Feedback is returned to the inverting input, and the first-stage amplifier G... m1 The inverting output port is connected to the feedback resistor R. f1 Feedback is sent to the non-inverting input. DC blocking capacitors C1 and C2 are connected to the output of the first-stage amplifier to isolate its DC offset voltage, thus suppressing larger signal ripple. After passing through C1 and C2, the signal reaches the second chopper, which modulates it back to a low frequency. This modulates the offset and noise of the first-stage amplifier to near the chopper frequency, achieving spectral separation of offset and noise from the input signal. Finally, only a low-pass filter is needed to remove the noise and offset. Because of the DC blocking capacitors, the second-stage amplifier G... m2 The bias voltage needs to be re-established, therefore a common-mode bias resistor R is applied at the input of the second-stage amplifier. b1 and R b2 Connected to common mode voltage V CMFB For the second stage amplifier G m2 To provide common-mode bias, a zero-adjustment resistor R is required because the instrumentation amplifier uses a two-stage amplification structure. C1 and R C2 and Miller capacitance C C1 and C C2 Compensation is performed to maintain system stability. After the signal exits the output of the second-stage amplifier, it passes through the third chopper CH3 and then through the feedback capacitor C. f1 and C f2 Feedback to the first stage amplifier G m1 The input terminals form a capacitively coupled feedback network, thereby determining the amplifier's gain A. CL In this utility model example, A CL Take 100.

[0037]

[0038] First-stage amplifier G m1 This amplifier comprises five PMOS transistors (MP0-MP4) and five NMOS transistors (MN0-MN4), employing an inverter-based structure. Using NMOS and PMOS transistors as input transistors allows for current multiplexing, improving current utilization. Common-gate NMOS transistors MN3 and MN4, and PMOS transistors MP3 and MP4 are added between the NMOS input transistors MN1 and MN2 and the PMOS input transistors MP1 and MP2 to increase the gain of the first-stage amplifier. Specifically, the source of PMOS transistor MP0 is connected to the power supply VDD, and its gate is connected to the bias voltage V. BP1 The drain is connected to the source of PMOS transistors MP1 and MP2, and the first-stage amplifier G... m1 The non-inverting input port V inp1The first-stage amplifier G is connected to the gates of PMOS transistor MP1 and NMOS transistor MN1. m1 Inverting input port V inn1 The gates of PMOS transistors MP2 and NMOS transistor MN2 are connected, and the gates of PMOS transistors MP3 and MP4 are connected to the bias voltage V. BP2 Connected, the non-inverting output port V of the first-stage amplifier outp1 The drains of PMOS transistor MP4 and NMOS transistor MN4 are connected; the drain of PMOS transistor MP1 is connected to the source of PMOS transistor MP3; and the drain of PMOS transistor MP2 is connected to the source of PMOS transistor MP4. The inverting output port V of the first-stage amplifier is connected to the source of PMOS transistor MP4. outn1 The drains of PMOS transistor MP3 and NMOS transistor MN3 are connected; the gates of NMOS transistors MN3 and MN4 are connected to the bias voltage VBN2; the source of NMOS transistor MN3 is connected to the drain of NMOS transistor MN1; the source of NMOS transistor MN4 is connected to the drain of NMOS transistor MN2; the sources of NMOS transistors MN1 and MN2 are connected to the drain of NMOS transistor MN0; the source of each NMOS transistor is connected to ground; and the gate is connected to the common-mode negative feedback voltage V. CMFB1 Connected.

[0039] The noise of the first-stage amplifier Gm1 mainly comes from the input transistors. Assuming that the transconductance of the two types of input transistors is equal, the equivalent input reference noise of the amplifier is:

[0040]

[0041] In the formula g mp1 and g mn1 The transconductances of input transistors MP1 and MN1 are respectively, K n and K p It is a process-related constant, (WL) p1 and (WL) n1 This is the product of the length and width of the two types of input transistors. The derivation shows that to achieve low noise, a sufficiently large W / L ratio is needed to keep the transistors operating in the subthreshold region, obtaining a larger gm / id. Simultaneously, increasing the transistor area can reduce amplifier flicker noise and offset.

[0042] Second-stage amplifier G m2 A common-source amplifier with a current-source load is used to improve the amplifier's output swing. NMOS transistors MN5 and MN6 and PMOS transistors MP5 and MP6 form the common-source amplifier. The sampling resistor for common-mode negative feedback is R. M1 and R M2The NMOS transistors MN7, MN8, and MN9, and the PMOS transistors MP7 and MP8 together form a common-mode negative feedback operational amplifier. The sources of the PMOS transistors MP5, MP6, MP7, and MP8 are connected to the power supply VDD, and the gates of the PMOS transistors MP5 and MP6 are connected to the bias voltage V. BP1 The drain of PMOS transistor MP5 and the common-mode negative feedback sampling resistor R M1 The first port and the drain of NMOS transistor MN5 are connected to the second stage amplifier G. m2 The inverting output port V outn2 Connected to the drain of PMOS transistor MP6 and the common-mode negative feedback sampling resistor R. M2 The first port and the drain of NMOS transistor MN6 are connected to the second stage amplifier G. m2 The non-inverting output port V outp2 Connected, common-mode negative feedback sampling resistor R M1 and R M2 The second port is connected to the gate of NMOS transistor MN8. The sources of NMOS transistors MN5, MN6, and MN7 are connected to ground GND. The gate of NMOS transistor MN5 is connected to the gate of the second-stage amplifier GND. m2 The non-inverting input port V inp2 The gate of NMOS transistor MN6 is connected to the gate of the second-stage amplifier G. m2 Inverting input port V inn2 Connected, the gate of NMOS transistor MN7 is connected to the bias voltage V. BN1 The sources of NMOS transistors MN8 and MN9 are connected to the drain of NMOS transistor MN7. The drain of NMOS transistor MN8 is connected to the drain and gate of PMOS transistor MP7 and the gate of PMOS transistor MP8. The gate of NMOS transistor MN9 is connected to the reference voltage V. REF The drain of the MP8 is connected to the common-mode voltage output port V. CMFB .

[0043] Positive feedback loop, through positive feedback capacitor C pf1 With C pf2 The output signal is directly fed back to the input terminal via the third chopper CH3. Here, the third chopper CH3 is multiplexed in both the positive and negative feedback loops, reducing the number of choppers and thus reducing the layout area. The positive feedback capacitor C... pf1 The first port and the input capacitor C in1 The second port is connected to the second output port of the third chopper CH3, and the positive feedback capacitor C is connected to the second port. pf2 The first port and the input capacitor C in2 The second port is connected to the second output port of the third chopper CH3.

[0044] The principle of positive feedback to increase input impedance:

[0045] Ideally, the current injected by the signal source is I. S =0, the amplifier's input impedance should be infinite. To obtain a higher input impedance, the current drawn from the signal source should be reduced; therefore, a positive feedback loop is added, introducing a positive feedback current I. pf1,2 Compensation Is. If I pf1,2 =I fb1,2 Then Is = 0, where I fb1,2 Given the current in the negative feedback loop, we obtain the following relationship:

[0046] I fb1,2 =2V out f ch C fb1,2 ;

[0047] I pf1,2 =2(V out -V in )f ch C pf1,2 ;

[0048]

[0049] To improve matching, let C pf1,2 =C fb1,2 Then the input impedance after adding the positive feedback loop is:

[0050]

[0051] The derivation results show that introducing a positive feedback loop can increase the input impedance by 100 times.

[0052] Pre-charge circuit, such as Figure 1 and Figure 2 As shown, it includes a first chopper CH1, a fifth chopper CH5, a sixth chopper CH6, a seventh chopper CH7, buffers Buf1 and Buf2, logic control switches S1 and S2, and a charging capacitor C. aux1 and C aux2 The pre-charge circuit is connected in parallel with the first chopper, and is connected from the input pin of the instrumentation amplifier through the first chopper CH1 to the input capacitor C. in1 and C in2 The path is the main path, and the path through the buffer is the auxiliary path. The timing diagram of the pre-charge circuit is as follows: Figure 3As shown, clk1 and clk2 are the control timing sequences for the first chopper, φ1 and φ2 are the control timing sequences for the seventh chopper in the pre-charge circuit, φ3 is the control timing sequence for logic control switches S1 and S2, and the control timing sequence for the remaining choppers (CH2 to CH6) is fch. T1 is the dead-time voltage of the first chopper. When the first chopper CH1 is operating in the chopper dead-time, the seventh chopper CH7 in the pre-charge circuit is turned on, supplying power to the input capacitor C. in1 and C in2 Charging reduces the signal source's charge to the input capacitor C. in1 and C in2 Charging increases the input impedance. Assuming the pre-charge time is T1, the DC input impedance is:

[0053]

[0054] In the formula, f ch Let be the chopping frequency, α be the static error of the buffer, and the exponential term represent the dynamic error caused by the limited bandwidth. Improving the impact of these two errors requires greater power consumption. Therefore, a capacitor C is introduced. aux The capacitor C is placed at the output of the buffer to reduce the requirements for the buffer's static and dynamic errors. During chopper operation on the main path, the buffer supplies capacitor C. aux When charging, C is charged when φ1 and φ2 are high and S1 and S2 are closed. aux Immediately inject charge into the input capacitor C in In this process, after the injection is complete, the buffer only needs to replenish the residual voltage, thereby reducing the power consumption requirements of the buffer.

[0055] DC servo loop, including integrating resistor R int1 and R int2 Amplifier G m3 and integrating capacitor C int1 and C int2 The integrator, fourth chopper CH4, and feedback capacitor C are composed of... dsl1 and C dsl2 The integrating resistor uses a multi-rate duty cycle resistor to achieve a large resistance, thereby reducing noise. The output offset of the instrumentation amplifier, after passing through the integrator, is modulated by the fourth chopper CH4, and then passes through the feedback capacitor C. dsl1 and C dsl2 Feedback to the first stage amplifier G m1 The virtual end.

[0056] Working principle of DC servo loop:

[0057] Typically, a DC servo loop suppresses output voltage offset by constructing a high-pass filter, assuming the high-pass angle is f. hpIf the high-pass cutoff frequency of the integrator is f0, then the relationship between the two is:

[0058]

[0059] Let f ph =0.5Hz. To ensure sufficient margin, the frequency needs to be below 0.5Hz. This requires a very large time constant for the integrator, which means the integrating resistor R... int The requirement is large, so this utility model embodiment uses a multi-rate duty cycle resistor as the integrating resistor R. int .

[0060] Feedback resistor R f1 and R f2 and common-mode bias resistor R b1 and R b2 Its structure is as follows Figure 6 As shown, the structure includes PMOS transistors M1 to M4, employing a symmetrical pseudo-resistor structure with series connection to increase resistance and reduce nonlinearity, achieving a resistance of approximately 70 GΩ. Pin 1 of the pseudo-resistor is connected to the gate and source of PMOS transistor M1. The substrates of PMOS transistors M1 to M4 are connected to the drain of M2 and the source of M3. The source of PMOS transistor M2 is connected to the drain of M1. The gate of PMOS transistor M3 is connected to the drain of M3 and the source of M4. The gate of PMOS transistor M4 is connected to the source of M4 and pin 2 of the pseudo-resistor.

[0061] Integrating resistor R int1 and R int2 ,like Figure 7 The multi-rate duty cycle resistor shown includes two polysilicon resistors R1 and R2, two logic control switches S3 and S4, and two capacitors C3 and C4. A multi-rate duty cycle resistor (MDCR) is used to reduce the noise contributed by the integrating resistor. The first port of the polysilicon resistor R1 is connected to the input pin V of the multi-rate duty cycle resistor. in The first port of capacitor C3 is connected to the second port of logic control switch S3, and the second port of polysilicon resistor R2 is connected to the second port of logic control switch S4 and ground. The first port of logic control switch S4 is connected to the second port of polysilicon resistor R2, and the first port of capacitor C4 is connected to the second port of logic control switch S4 and the output pin V of multi-rate duty cycle resistor. out Connected to the ground via the second port.

[0062] Working principle of multi-rate duty cycle resistors:

[0063] A multi-rate duty cycle resistor is obtained by connecting a low-pass filter consisting of a duty cycle resistor (DCR) and a capacitor in series with another duty cycle resistor, such as... Figure 7 As shown. The low-pass filter composed of resistor R1, logic control switch S3, and capacitor C3 has a cutoff frequency slightly higher than the target cutoff frequency of 0.5Hz. This filter is called an anti-aliasing filter (AAF). Here, f1 needs to be greater than twice the signal frequency to avoid aliasing. After the first stage of AAF, the signal bandwidth flowing into the second low-pass filter is reduced, bypassing the limitation of the minimum required switching frequency f2. This increases the maximum realizable resistance of DCR (composed of R2 and logic control switch C4) by f1 / f2 times, with an equivalent resistance of R. eq :

[0064]

[0065] Where D is the duty cycle.

[0066] Noise optimization principle of DC servo loop:

[0067] Introducing a DC servo loop will increase the overall noise of the instrumentation amplifier. The increased noise is as follows:

[0068]

[0069] V noise,DSL V represents the reference noise introduced by the DSL. noise,Gm3 The amplifier G is an integrator. m3 Introduced reference noise, V noise,Rint The integrator has a large resistor R. int noise, ω int =1 / R int C int From the above analysis, we can see that G can be reduced. m3 and large resistance R int The noise contributed by amplifier Gm3 can be optimized by increasing the tube area and the integrating resistor R. int A new structure is needed to improve it.

[0070] The noise of resistive devices mainly includes thermal noise and flicker noise. Thermal noise is generated due to the thermal motion of charge carriers, and its voltage noise power spectral density is:

[0071] S v (f) = 4kTR;

[0072] Where k is the Boltzmann constant, T is the absolute temperature, and R is the resistance. This noise is white noise and is independent of frequency. Flicker noise, on the other hand, is caused by material defects or interface traps, and its power spectral density is inversely proportional to frequency.

[0073]

[0074] K is a process-related parameter. Flicker noise mainly affects low-frequency signals, which significantly impacts the detection of weak biological signals. Among common resistors, both metal resistors and polysilicon resistors follow the laws of thermal noise. Metal resistors have very low flicker noise, while polysilicon resistors introduce some flicker noise due to grain boundary defects, but this is less than that of MOSFETs. Using a MOSFET as a pseudo-resistor, operating in the subthreshold region, its noise power spectral density is:

[0075]

[0076] Where γ = 2 / 3, V T Where W is the thermal voltage, and L is the width and length of the MOSFET, respectively. ox The first term represents the gate oxide capacitance per unit area. The second term represents the thermal noise contributed by the MOSFET, which is inversely proportional to the current. The third term represents the flicker noise, which dominates the low-frequency noise. Overall, the noise contributed by using the MOSFET as a pseudo-resistor is greater than that of metal resistors and polysilicon resistors.

[0077] In the embodiments of this utility model, a multi-rate duty cycle resistor is used as the large resistor R of the integrator. int1 and R int2 By periodically controlling the MOS transistor with pulses of different duty cycles, the equivalent flicker noise can be reduced using the time averaging effect, thus solving the problem of significant noise contribution from the MOS transistor. By controlling logic control switches S3 and S4 with pulses of different duty cycles, and using polysilicon resistors with low noise contribution as R1 and R2, a low-noise-contribution integrating resistor R can be achieved. int Its advantages include a smaller area than large resistors achieved entirely with polysilicon resistors, and superior noise performance compared to pseudo-resistors.

[0078] Because chopper modulation technology is used to suppress amplifier noise and offset, the noise and offset are modulated to high frequencies. Furthermore, the chopper switch itself suffers from charge injection and clock feedthrough issues, which can cause spikes and glitches in the output signal during two-phase non-overlapping clock switching. Therefore, a low-pass filter is introduced to filter out high-frequency noise and offset, as well as spikes and glitches, resulting in a clean signal.

[0079] The structure of a low-pass filter is as follows: Figure 8As shown, the second-order active low-pass filter used in this embodiment of the invention is a second-order active low-pass filter, where R1 = R2 = R5 = R6 = R7 = R8, R3 = R4, C1 = C2 = C3 = C4, and its transfer function is:

[0080]

[0081] By analogy with the standard transfer function expression of a second-order low-pass filter, the characteristic frequency ω0 and the quality factor Q can be obtained:

[0082]

[0083] Based on the determined characteristic frequency ω0 and quality factor Q, appropriate resistor and capacitor values ​​can be selected.

[0084] The technical effects of this invention can be further illustrated through simulation experiments:

[0085] 1. Simulation conditions:

[0086] Under a power supply voltage of 1.8V, this utility model... Figure 1 The circuit shown is modeled using a 180nm BCD process and simulated using the Cadence simulation tool.

[0087] 2. Simulation content:

[0088] Simulation 1: Under the above conditions, the input impedance of the circuit is simulated, and the simulation results are as follows. Figure 9 As shown, a high input impedance is achieved, with an input impedance of 9 GΩ at low frequencies and an input impedance of nearly 1.59 GΩ at 100 Hz.

[0089] Simulation 2: Under the above conditions, the input reference noise of the circuit is simulated, and the simulation results are as follows. Figure 10 As shown in the figure, there are two curves. The solid line represents the simulation result of the input reference noise using a pseudo-resistor as the large resistor of the integrator, with an input equivalent noise of 2.39 μVrms (integration range of 0.5–200 Hz). The dashed line represents the simulation result of using a multi-rate duty cycle resistor as the large resistor of the integrator, with an input equivalent noise of 0.282 μVrms (integration range of 0.5–200 Hz). The comparison shows that the dashed line is below the solid line, indicating that using a multi-rate duty cycle resistor as the large resistor of the integrator results in a better noise contribution.

[0090] Simulation 3: Under the above conditions, a transient simulation of the circuit is performed. The simulation results are as follows. Figure 11As shown, the input signal is the waveform at the top, the waveform in the middle is the waveform output by the main amplifier, which contains many spikes and glitches, and the waveform at the bottom is the waveform after filtering, where ripples and glitches are filtered out, resulting in a cleaner amplified signal.

Claims

1. A capacitor-coupled chopper instrumentation amplifier, comprising a main amplifier, a positive feedback loop, a pre-charge circuit, a DC servo loop, and a low-pass filter; characterized in that: The main amplifier includes: an input capacitor C in1 and C in2 First stage amplifier G m1 DC blocking capacitors C1 and C2, second-stage amplifier G m2 Feedback resistor R f1 and R f2 Common-mode bias resistor R b1 and R b2 Second chopper CH2, zero-adjustment resistor R C1 and R C2 Miller compensation capacitor C C1 and C C2 The third chopper CH3, and the feedback capacitor C fb1 and C fb2 Among them, the first output port of the first chopper CH1 is connected to the input capacitor C. in1 The second port is connected to the input capacitor C. The second output port of the first chopper CH1 is connected to the input capacitor C. in2 The second port is connected to the input capacitor C. in1 The first port and the first stage amplifier G m1 Connected to the non-inverting input port, input capacitor C in2 The first port and the first stage amplifier G m1 The inverting input port is connected, and the feedback resistor R f1 The first port and the first stage amplifier G m1 The non-inverting input terminal is connected, and the feedback resistor R f1 The second port is connected to the first stage amplifier G. m1 The inverting output port is connected, and the feedback resistor R f2 The first port and the first stage amplifier G m1 The inverting input terminal is connected, and the feedback resistor R f2 The second port is connected to the first stage amplifier G. m1 The positive output port of the DC blocking capacitor C1 is connected to the first input port of the second chopper CH2, and the second port of the DC blocking capacitor C1 is connected to the first stage amplifier G. m1 The inverting output port of the first stage amplifier G is connected to the second input port of the second chopper CH2, and the first port of the DC blocking capacitor C2 is connected to the second input port of the second chopper CH2. m1 The non-inverting output port of the second chopper CH2 is connected to the first output port of the second stage amplifier G. m2 The non-inverting input terminal is connected, and the second output port is connected to the second-stage amplifier G. m2 The inverting input terminal is connected to the second-stage amplifier G. m2 The non-inverting output port of the amplifier is connected to the inverting input port VIN of the low-pass filter, and the second-stage amplifier G... m2 The inverting output port is connected to the non-inverting input port VIP of the low-pass filter, and the common-mode bias resistor R... b1 First port and second stage amplifier G m2 Connected to the non-inverting input terminal, common-mode bias resistor R b1 The second port is connected to the common-mode feedback signal V. CMFB Common-mode bias resistor R b2 First port and second stage amplifier G m2 The inverting input terminal is connected to the common-mode bias resistor R. b2 The second port is connected to the common-mode feedback signal V. CMFB Zero-adjustment resistor R C1 First port and second stage amplifier G m2 Connect the non-inverting input terminal to the zero-adjustment resistor R. C1 The second port is connected to the Miller compensation capacitor C. C1 The second port is connected to the Miller compensation capacitor C. C1 The first port and the second stage amplifier G m2 Connect the inverting output port to the zero-adjustment resistor R. C2 First port and second stage amplifier G m2 Connect the inverting input terminal to the zero-adjustment resistor R. C2 The second port is connected to the Miller compensation capacitor C. C2 The second port is connected to the Miller compensation capacitor C. C2 The first port and the second stage amplifier G m2 The non-inverting output port is connected, and the first input port of the third chopper CH3 is connected to the second-stage amplifier G. m2 The inverting output port is connected to the second input port of the third chopper CH3, and the second input port of the second-stage amplifier G is connected to the second-stage amplifier G. m2 The positive output port of the third chopper CH3 is connected to the feedback capacitor C. fb1 The second port is connected to the third chopper CH3, and the second output port is connected to the feedback capacitor C. fb2 The second port is connected to the feedback capacitor C. fb1 The first port and the first stage amplifier G m1 The inverting input port is connected, and the feedback capacitor C is connected. fb2 The first port and the first stage amplifier G m1 Connected to the non-inverting input port; The positive feedback loop includes: a positive feedback capacitor C pf1 The first port and the input capacitor C in1 The second port is connected to the positive feedback capacitor C. pf1的 The second port is connected to the first output port of the third chopper CH3, and the positive feedback capacitor C pf2 The first port and the input capacitor C in2 The second port is connected to the positive feedback capacitor C. pf2 The second port is connected to the second output port of the third chopper CH3; The pre-charging circuit includes: a first chopper CH1, a fifth chopper CH5, a sixth chopper CH6, a seventh chopper CH7, buffers Buf1 and Buf2, logic control switches S1 and S2, and a charging capacitor C. aux1 and C aux2 The non-inverting input pin V of the instrumentation amplifier inp Connected to the first input ports of the first chopper CH1 and the fifth chopper CH5, the inverting input pin V of the instrumentation amplifier inn The first chopper CH1 and the fifth chopper CH5 are connected to their second input ports; the first output port of the first chopper CH1 is connected to the input capacitor C. in1 The second port of the first chopper CH7 is connected to the first output port of the seventh chopper CH7, and the second output port of the first chopper CH1 is connected to the input capacitor C. in2 The second port of the seventh chopper CH7 is connected to the second output port of the seventh chopper CH7; the input port of buffer Buf1 is connected to the first output port of the fifth chopper CH5, and the output port of buffer Buf1 is connected to the first input port of the sixth chopper CH6; the input port of buffer Buf2 is connected to the second output port of the fifth chopper CH5, and the output port of buffer Buf2 is connected to the second input port of the sixth chopper CH6; the first input terminal of the seventh chopper CH7 is connected to the first output terminal of the sixth chopper CH6 and the first port of logic control switch S1, and the second input terminal of the seventh chopper CH7 is connected to the second output terminal of the sixth chopper CH6 and the first port of logic control switch S2; the charging capacitor C aux1 The first port is connected to the second port of the logic control switch S1, and the charging capacitor C aux1 The second port is connected to ground, and the charging capacitor C aux2 The first port is connected to the second port of the logic control switch S2, and the charging capacitor C aux2 The second port is connected to ground; The DC servo loop includes: an integrating resistor R int1 First port and second stage amplifier G m2 The inverting output terminal is connected, and the integrating resistor R int2 First port and second stage amplifier G m2 The non-inverting output terminal of amplifier G is connected; m3 The non-inverting input terminal is connected to the second port of the integrating resistor Rint2 and the integrating capacitor C. int2 The first port is connected; amplifier G m3 The inverting input terminal and the integrating resistor R int1 The second port, integrating capacitor C int1 The first port is connected; amplifier G m3 The non-inverting output terminal and the integrating capacitor C int1 The second port of the amplifier is connected to the first input port of the fourth chopper CH4; amplifier G m3 The inverting output terminal and the integrating capacitor C int2 The second port of the fourth chopper CH4 is connected to the second input port of the fourth chopper CH4; feedback capacitor C dsl1 The first port and the first stage amplifier G m1 The non-inverting input port is connected, and the feedback capacitor C is connected. dsl1 The second port is connected to the first output port of the fourth chopper CH4; feedback capacitor C dsl2 The first port and the first stage amplifier G m1 The inverting input port is connected, and the feedback capacitor C is connected. dsl2 The second port is connected to the second output port of the fourth chopper CH4; The integrating resistor R int1 and R int2 Each resistor is a multi-rate duty cycle resistor consisting of two polysilicon resistors R1 and R2, two logic control switches S3 and S4, and two capacitors C3 and C4; the first port of R1 is connected to the input pin V of the multi-rate duty cycle resistor. in Connect R1's second port to S3's first port; connect C3's first port to S3's second port and R2's first port; connect C3's second port to ground; connect S4's first port to R2's second port; connect C4's first port to S4's second port; and connect the multi-rate duty cycle resistor's output pin V. out Connect C4 to ground via its second port. The low-pass filter includes: two amplifiers A1 and A2, eight resistors R1~R8, and four capacitors C1~C4; the non-inverting input port VIP of the low-pass filter is connected to the first port of R1, and the second port of R1 is connected to the non-inverting input port of A1, the first port of C1, the first port of R3, and the first port of R7; the inverting input port VIN of the low-pass filter is connected to the first port of R2, and the second port of R2 is connected to the inverting input port of A1, the first port of C2, the first port of R4, and the first port of R8; the inverting output port of A1 is connected to the second port of C1, ... The second port of R3 and the first port of R5 are connected. The non-inverting output port of A1 is connected to the second port of C2, the second port of R4, and the first port of R6. The second port of R5 is connected to the inverting input port of A2 and the first port of C4. The second port of R6 is connected to the non-inverting input port of A2 and the first port of C3. The inverting output of A2 is connected to the non-inverting output port VOP of the low-pass filter, the second port of C3, and the second port of R7. The non-inverting output of A2 is connected to the inverting output port VON of the low-pass filter, the second port of C4, and the second port of R8.

2. The capacitively coupled chopper instrumentation amplifier according to claim 1, characterized in that, First stage amplifier G m1 Includes: 5 PMOS transistors MP0~MP4 and 5 NMOS transistors MN0~MN4; the source of MP0 is connected to the power supply VDD, and the gate of MP0 is connected to the bias voltage V. BP1 The drain of MP0 is connected to the source of MP1 and MP2, G m1 The non-inverting input port V inp1 G is connected to the gates of MP1 and MN1. m1 Inverting input port V inn1 The gates of MP2 and MN2 are connected, and the gates of MP3 and MP4 are connected to the bias voltage V. BP2 Connected, G m1 The non-inverting output port V outp1 The drain of MP1 is connected to the drain of MP4 and MN4, the drain of MP1 is connected to the source of MP3, and the drain of MP2 is connected to the source of MP4. G m1 The inverting output port V outn1 The drains of MN3 and MN4 are connected to the bias voltage VBN2. The source of MN3 is connected to the drain of MN1. The source of MN4 is connected to the drain of MN2. The sources of MN1 and MN2 are connected to the drain of MN0. The source of MN0 is connected to ground. The gate of MN0 is connected to the common-mode negative feedback voltage V. CMFB1 Connected.

3. The capacitively coupled chopper instrumentation amplifier according to claim 1, characterized in that, Second stage amplifier G m2 Includes: 4 PMOS transistors MP5, MP6, MP7 and MP8; 5 NMOS transistors MN5, MN6, MN7, MN8 and MN9; and 2 common-mode negative feedback sampling resistors R. M1 and R M2 The source of MP5, MP6, MP7, and MP8 is connected to the power supply VDD, and the gate of MP5 and MP6 is connected to the bias voltage V. BP1 MP5 drain, R M1 The first port, the drain of MN5, and the second stage amplifier G m2 The inverting output port V outn2 Connected; the drain of MP6, R M2 The first port, the drain of MN6, and the second stage amplifier G m2 The non-inverting output port V outp2 Connected, R M1 R M2 The second port is connected to the gate of MN8; the sources of MN5, MN6, and MN7 are connected to ground GND; the gate of MN5 is connected to the gate of the second-stage amplifier G. m2 The non-inverting input port V inp2 Connected, the gate of MN6 is connected to the second-stage amplifier G. m2 Inverting input port V inn2 Connected, the gate of MN7 is connected to the bias voltage V BN1 The sources of MN8 and MN9 are connected to the drain of MN7; the drain and gate of MP7 are connected, and the gate of MP8 is connected to the drain of MN8; the gate of MN9 is connected to the reference voltage V. REF The drains of MN9 and MP8 are connected to the common-mode voltage output port V. CMFB .

4. The capacitively coupled chopper instrumentation amplifier according to claim 1, characterized in that, The feedback resistor R f1 and R f2 and common-mode bias resistor R b1 and R b2 Each of the pseudo resistors consists of four PMOS transistors, M1 to M4. Pin 1 of the pseudo resistor is connected to the gate and source of M1. The substrates of M1, M2, M3, and M4 are all connected to the drain of M2 and the source of M3. The gate and source of M2 are connected to the drain of M1. The gate and drain of M3 are connected to the source of M4. The gate and source of M4 are connected to pin 2 of the pseudo resistor.

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