An ultra-wideband bias circuit and an integrated structure implementing the same
Patent Information
- Application Number
- CN202522138538.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-10
- Publication Date
- 2026-10-23
- Estimated Expiration
- 2035-10-10
AI Technical Summary
然而，现有技术中的许多Bias-Tee产品在高频段容易出现信号衰减过大、直流与射频端口隔离效果不佳导致信号干扰等问题，难以满足这些复杂且严苛的应用需求
[0008]本实用新型有效实现了超高频超宽带的特性，且具有低损耗、高隔离度、高可靠性、低成本和适合于大规模的生产等优点，另外还适应了新的电子元件集成化、小型化的发展趋势。
Smart Images
Figure CN224890612U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of radio frequency and microwave communication technology, specifically relating to a low insertion loss bias circuit device (Bias-Tee) suitable for high frequency, broadband and high isolation scenarios, especially suitable for 5G base stations, millimeter wave radar, high-speed optical communication and next-generation wireless communication systems. Background Technology
[0002] In modern communication systems, bias-tees, as a key three-port network device, are widely used in various RF and microwave circuits to inject DC bias voltage and transmit RF signals on the same transmission line. However, traditional bias-tees are increasingly revealing limitations when facing growing demands for high frequency, wide bandwidth, and high isolation. For example, in advanced communication base stations, radar systems, optical communications, and high-speed data transmission links, bias-tees need to maintain low insertion loss, high isolation, and stable performance over a wider frequency range. However, many existing bias-tee products are prone to excessive signal attenuation and poor DC-RF port isolation leading to signal interference at high frequencies, making it difficult to meet these complex and demanding application requirements. Utility Model Content
[0003] The purpose of this technology is to address the shortcomings of the existing technologies mentioned above by designing an ultra-wideband bias circuit that can effectively improve the low insertion loss and high isolation of Bias-Tee products at high frequencies and wide bandwidths, as well as the integrated structure for implementing this circuit.
[0004] The objective of this technology can be achieved through the following technical solution: an ultra-wideband bias circuit and an integrated structure for implementing the circuit, characterized in that the circuit consists of signal input terminals P1 and P3, a signal output terminal P2, inductors L1 and L2, and capacitors C1, C2, C3, and C4; capacitor C2 is connected in series between the signal input terminal P1 and the signal output terminal P2; one end of inductors L1 and L2 connected in series is connected to the signal input terminal P3, and the other end is connected to the signal output terminal P2; the series terminals of inductors L1 and L2 are respectively connected to one end of capacitors C2 and C3; the other ends of capacitors C2 and C3 are grounded; one end of capacitor C4 is connected to the signal input terminal P3, and the other end is grounded; wherein C1 forms the coupling node of the main path of the radio frequency signal and the blocking node of the DC signal, forming the first transmission point of the radio frequency path; inductor L1 and capacitors C2 and C3 form the main path of the DC signal, which is the first blocking node of the radio frequency signal to the DC port; inductor L2 and capacitor C4 form the main path of the DC signal, which is the second blocking node of the radio frequency signal to the DC port; The integrated structure consists of an external electrode surface layer and an internal circuit structure layer. The surface layer includes an input terminal A1 for DC signals, an input terminal A3 for RF signals, a mixed output terminal for DC and RF signals, and a ground terminal A7, A2, A4, A5, A6, A8, A9, A10, A11, and A12. The internal circuit structure layer has three layers. The first layer has metal patterns 1a, 1b, 1c, 1d, 1f, 1g, and 1h printed on a resin substrate. Capacitors C1, C2, C3, and C4, and inductors L1 and L2 are surface-mount capacitors and inductors, attached to the first layer. The second layer has metal patterns 2a, 2b, 2c, 2d, and 2e printed on the resin substrate. The copper area at position 2e of inductor L1 in the second layer is cut off, while the remaining area is fully copper-plated. The third layer has a metal pattern 3a printed on the resin substrate, serving as a PAD layer. The metal PAD A1 (3a) is connected to the metal pattern 2b in the second layer. The central post is connected to 1c of the first layer; 1c and 1d of the first layer are connected to capacitor C4 and inductor L2; in the surface layer, metal PADs A2, A4, A5, A6, A8, A9, A10, A11, and A12 are connected to 1f and 1e of the first layer through the second layer 2c, and are then connected to capacitors C3, C2, and inductor L1; 1c and 1f of the first layer are connected to the two ends of inductor L2 respectively; 1f and 1g of the first layer are connected to the two ends of inductor L1 respectively; 1f and 1h of the first layer are connected to the two ends of capacitor C2 respectively; in the surface layer, metal PAD A3 is connected to 1a and 1g of the first layer through the second layer 2a, and then connected to the two ends of capacitor C1 respectively; in the surface layer, metal PAD A7 is connected to 1g and 1f of the first layer and inductor L1 through the second layer 2d.
[0005] Furthermore, in the integrated structure of the ultra-wideband paralysis circuit, the thickness of the metal pattern conductor layer printed on the first, second, and third resin dielectric substrates is 0.02 mm, and the linewidth of the conductor layer is 0.075 mm.
[0006] Furthermore, in the integrated structure of the ultra-wideband paralysis circuit, the thickness of the first, second, and third resin dielectric substrates is 0.08±0.05mm, and the substrate dielectric constant is 4.4±0.2.
[0007] Furthermore, the integrated structure of the ultra-wideband bias circuit, with its first, second, and third layers together with discrete capacitors and inductors, achieves insertion loss <0.6 dB@DC-10 GHz, isolation >40 dB@DC-10 GHz, and standing wave ratio <1.5@DC-10 GHz.
[0008] This invention effectively realizes the characteristics of ultra-high frequency and ultra-wideband, and has the advantages of low loss, high isolation, high reliability, low cost and suitability for large-scale production. In addition, it also adapts to the new development trend of electronic component integration and miniaturization. Attached image description: Figure 1 This is a schematic diagram of the equivalent circuit of the bias circuit of this utility model; Figure 2 This is a three-dimensional schematic diagram of the surface structure of the bias circuit of this utility model; Figure 3 This is a schematic diagram of the internal structure of the bias circuit of this utility model; Figure 4 This is a schematic diagram of the component layout of this utility model; Figure 5 This is a schematic diagram of the first layer circuit planar structure of this utility model; Figure 6 This is a schematic diagram of the point-column connection planar structure between the first and second layers of this utility model; Figure 7 This is a schematic diagram of the second-layer circuit planar structure of this utility model; Figure 8 This is a schematic diagram of the point-column connection planar structure between the second and third layers of this utility model; Figure 9 This is a schematic diagram of the third layer circuit planar structure of this utility model. Detailed implementation method: like Figure 1 The diagram shown is the equivalent circuit diagram of the ultra-wideband bias circuit of this invention. Signals enter through ports P1 and P3 and are output through port P2. The bias circuit consists of inductors L1 and L2 and capacitors C1, C2, C3, and C4. C1 forms the coupling node of the main path for the RF signal and also the blocking node for the DC signal, forming the first transmission point of the RF path. L1, C2, and C3 form the main path for the DC signal, the first blocking node from the RF signal to the DC port. L2 and C4 form the main path for the DC signal, the second blocking node from the RF signal to the DC port. This effectively reduces the loss of both the RF and DC signals and improves the isolation between the RF and DC ports.
[0009] like Figure 2 The diagram shows the external surface structure of the ultra-wideband bias circuit. It represents the external input / output interfaces at the bottom of the substrate, with signal inputs and outputs connected to the components in the schematic via internal traces. A1 is the DC signal input, A3 is the RF signal input, A7 is the mixed DC and RF signal output, and A2, A4, A5, A6, A8, A9, A10, A11, and A12 are grounding ports.
[0010] like Figure 3 The diagram shows the internal structure of the ultra-wideband bias circuit, which is distributed inside the substrate; the circuit structure has three layers. The first layer, as shown... Figure 5 As shown, metal patterns 1a, 1b, 1c, 1d, 1f, 1g, and 1h are printed on a resin dielectric substrate. The width of the RF main path metal trace is precisely designed to be 0.075 mm. Especially in the 1g metal pattern, the trace width must be strictly controlled to achieve ultra-wideband impedance matching, optimize high-frequency impedance continuity, improve insertion loss to <0.6 dB@DC-10 GHz, and its isolation to >40 dB@DC-10 GHz.
[0011] Its second layer, such as Figure 7 As shown, metal patterns 2a, 2b, 2c, 2d, and 2e are printed on a resin dielectric substrate. The copper plating area at position 2e of the second layer of the L1 inductor is cut off, while the remaining area is fully copper-plated. This significantly improves the parasitic effects of the components and the electrical performance at high frequencies, increasing insertion loss to <0.6 dB@DC-10 GHz, isolation to >40 dB@DC-10 GHz, and VSWR to <1.5@DC-10 GHz. Its third layer is as follows... Figure 9 As shown, metal patterns such as 3a are printed on a resin dielectric substrate, which belong to the PAD layer; like Figure 4 The diagram shows the component layout of this utility model. Due to the large capacitance and inductance values in the schematic diagram, it is difficult to integrate this utility model onto the substrate. Capacitors C1, C2, C3, and C4, and inductors L1 and L2 are surface-mount capacitors and inductors. In this layout, C1, C2, C3, and C4 are capacitors, and L1 and L2 are inductors, all corresponding to the circuit schematic. C5 is an NC (non-conductive) capacitor. This component layout is a three-dimensional orthogonal distributed LC network. Inductors L1 and L2 are orthogonally arranged, reducing mutual coupling effects through magnetic field direction decoupling. Capacitors C1 and C4 are symmetrically distributed, arranged along the main RF path on both sides of the inductors, forming a distributed filter network to suppress high-frequency parasitic resonance and significantly reduce parasitic effects between the components and the substrate.
[0012] This utility model Figure 6 for Figure 5 The first layer shown is Figure 7 The diagram shows the connection point between the upper and lower layers of the second layer. Figure 8 for Figure 7 The second layer shown is Figure 9 The diagram shows the connection point between the upper and lower layers of the third layer.
Claims
1. An ultra-wideband bias circuit and an integrated structure for implementing the circuit, characterized in that, The circuit consists of signal input terminals P1 and P3, signal output terminal P2, inductors L1 and L2, and capacitors C1, C2, C3, and C4. Capacitor C2 is connected in series between signal input terminal P1 and signal output terminal P2. One end of inductors L1 and L2, connected in series, is connected to signal input terminal P3, and the other end is connected to signal output terminal P2. The series connection of inductors L1 and L2 is connected to one end of capacitors C2 and C3, respectively. The other ends of capacitors C2 and C3 are grounded. One end of capacitor C4 is connected to signal input terminal P3, and the other end is grounded. C1 forms the coupling node of the main RF signal path and the blocking node of the DC signal, forming the first transmission point of the RF path. Inductor L1 and capacitors C2 and C3 form the main DC signal path, serving as the first blocking node from the RF signal to the DC port. Inductor L2 and capacitor C...
4. The main path for DC signals is formed, serving as the second blocking node from the RF signal to the DC port. The integrated structure consists of an external electrode surface layer and an internal circuit structure layer. The surface layer includes an input terminal A1 for DC signals, an input terminal A3 for RF signals, a mixed output terminal for DC and RF signals, and a ground terminal A7, A2, A4, A5, A6, A8, A9, A10, A11, and A12. The internal circuit structure layer consists of three layers. The first layer has metal patterns 1a, 1b, 1c, 1d, 1f, 1g, and 1h printed on a resin dielectric substrate. The capacitors C1, C2, C3, and C4, and the inductors L1 and L2 are surface-mount capacitors and inductors, and are attached to the first layer. The second layer has metal patterns 2a, 2b, 2c, 2d, and 2e printed on a resin dielectric substrate. The copper area at position 2e of the inductor L1 in the second layer is cut off, while the rest is fully copper-plated. The third layer is a PAD layer with a metal pattern 3a printed on the resin substrate. Metal PAD A1 (3a) is connected to layer 1c of the first layer via a central hole in the second layer metal pattern 2b. Layers 1c and 1d of the first layer are connected to capacitor C4 and inductor L2. Metal PADs A2, A4, A5, A6, A8, A9, A10, A11, and A12 in the surface layer are connected to layers 1f and 1e of the first layer via layer 2c, and then connected to capacitors C3, C2, and inductor L1. Layers 1c and 1f of the first layer are connected to the two ends of inductor L2, 1f and 1g of the first layer are connected to the two ends of inductor L1, and 1f and 1h of the first layer are connected to the two ends of capacitor C2. Metal PAD A3 in the surface layer is connected to layers 1a and 1g of the first layer via layer 2a, and then connected to the two ends of capacitor C1. Metal PAD A7 in the surface layer is connected to layers 1g and 1f of the first layer and inductor L1 via layer 2d.
2. The ultra-wideband bias circuit and the integrated structure for implementing the circuit according to claim 1, characterized in that, The thickness of the metal pattern conductor layer printed on the first, second, and third resin dielectric substrates is 0.02 mm, and the line width of the conductor layer is 0.075 mm.
3. The ultra-wideband bias circuit and the integrated structure for implementing the circuit according to claim 1, characterized in that, The thickness of the first, second, and third resin dielectric substrate layers is 0.08±0.05mm, and the substrate dielectric constant is 4.4±0.
2.
4. The ultra-wideband bias circuit and the integrated structure for implementing the circuit according to claim 1, characterized in that, The first, second, and third layers, together with discrete capacitors and inductors, achieve an insertion loss of <0.6 dB@DC-10 GHz, an isolation of >40 dB@DC-10 GHz, and a standing wave ratio of <1.5@DC-10 GHz.