A novel high-precision phase discriminator circuit

Abstract

The utility model belongs to analog signal processing field, concretely relates to a novel high accuracy phase -sensitive circuit, include: current pump circuit, resistance -capacity network and field effect tube drive circuit, current pump circuit input end is connected with digital circuit output end, and current pump circuit is used for according to the phase difference of digital circuit output signal injects or draws out fixed current to resistance -capacity network, resistance -capacity network input end is connected with current pump circuit output end, and resistance -capacity network is used for converting the fixed current that current pump circuit injects or draws out into voltage, and input to field effect tube drive circuit, field effect tube drive circuit input end is connected with resistance -capacity network output end, and field effect tube drive circuit drives luminous tube according to input voltage, when this phase -sensitive circuit injects, draws out current to resistance -capacity network, the time difference of injection or draw out current acts on resistance -capacity network, causes and resistance -capacity network and the gate voltage of connected field effect tube to change, and after field effect tube amplification, output phase -sensitive result, and phase -sensitive sensitivity is high.

Description

Technical Field

[0001] This invention belongs to the field of analog signal processing, and specifically relates to a novel high-precision phase detection circuit. Background Technology

[0002] In analog signal processing, phase holding, or phase-locked loop (PLL), is often required. The prerequisite for PLL is phase detection, or phase measurement. Due to the technical difficulty of phase detection, it is difficult to achieve high-precision detection of small-angle phase differences. Therefore, the accuracy of previous phase detection processes was not high. In fact, it was sufficient to keep the phase difference within a certain range, which met the requirements of most PLL applications. For example, some PLLs are actually for frequency locking, i.e., keeping up with the frequency. However, some applications require high phase detection accuracy, and existing phase detection technologies cannot meet the high-precision detection requirements. Summary of the Invention

[0003] To address the problem of low accuracy in existing phase detection circuits, a novel high-precision phase detection circuit is proposed.

[0004] A novel high-precision phase detection circuit includes:

[0005] Current pump circuit, RC network and MOSFET drive circuit;

[0006] The input terminal of the current pump circuit is connected to the output terminal of the digital circuit. The current pump circuit is used to inject or pull a fixed current into the resistor-capacitor network according to the phase difference of the output signal of the digital circuit.

[0007] The input terminal of the RC network is connected to the output terminal of the current pump circuit. The RC network is used to convert the fixed current injected or pulled out by the current pump circuit into voltage and input it to the field-effect transistor drive circuit.

[0008] The input terminal of the field-effect transistor (FET) driver circuit is connected to the output terminal of the resistor-capacitor (RC) network. The FET driver circuit drives the LED according to the input voltage.

[0009] The beneficial effects of this invention are as follows: This invention proposes a novel high-precision phase detection circuit with high phase detection accuracy and no dead zone. When current is injected into or pulled out of the RC network, the time difference between the injected and pulled current acting on the RC network causes a change in the gate voltage of the RC network and the connected MOSFET. The phase detection result is amplified by the MOSFET and output, achieving good results in practical applications. Utilizing current pump (charge pump) technology and unique phase detection logic and circuitry, the circuit achieves high phase detection sensitivity and accuracy, and the output exhibits integral characteristics. Attached Figure Description

[0010] Figure 1 A circuit diagram of a novel high-precision phase detection circuit according to a specific embodiment of this application;

[0011] Figure 2A waveform diagram of a novel high-precision phase detection circuit according to a specific embodiment of this application;

[0012] Figure 3 This is a modified circuit diagram of a novel high-precision phase detection circuit according to a specific embodiment of this application. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the embodiments and accompanying drawings. Here, the illustrative embodiments and descriptions of this invention are used to explain the invention, but are not intended to limit the invention.

[0014] A novel high-precision phase detection circuit includes:

[0015] Current pump circuit, RC network and MOSFET drive circuit;

[0016] The input terminal of the current pump circuit is connected to the output terminal of the digital circuit. The current pump circuit is used to inject or pull a fixed current into the resistor-capacitor network according to the phase difference of the output signal of the digital circuit.

[0017] The input terminal of the RC network is connected to the output terminal of the current pump circuit. The RC network is used to convert the fixed current injected or pulled out by the current pump circuit into voltage and input it to the field-effect transistor drive circuit.

[0018] The input terminal of the field-effect transistor (FET) driver circuit is connected to the output terminal of the resistor-capacitor (RC) network. The FET driver circuit drives the LED according to the input voltage.

[0019] Specifically, in analog signal processing, phase holding, i.e. phase-locked loop, is often required. The prerequisite for phase locking is phase detection, and there are many ways to detect phase. This invention proposes a high-precision phase detection circuit that uses current pumping technology to achieve high phase detection accuracy and high gain, and has integral characteristics. It has achieved good results in practical project applications.

[0020] In a high-precision inductive synchro angle measurement system, it is necessary to keep the phases (electrical angle 0.01°) of the sine and cosine (2kHz) output signals of the dual-phase excitation power supply constant. Since the distortion error of both signals must be small, multi-stage filtering is required, including bandpass filtering. The combined effect of various factors and filtering stages causes the two-phase signals to drift with time and temperature, and the phases of the two-phase sine waves also undergo uncontrollable changes. The phase detection stage (phase detector) detects the difference in phase angle between the two phases, i.e., the original phase angle... Two sinusoidal waves with a 90° phase difference, namely sine and cosine signals, experience phase drift. Their phase angles are no longer 90° apart, but rather around 90°. The phase detection result drives an amplifier with a controllable phase shift and constant gain to shift the phases of the two sinusoidal signals, so that the two phases still maintain a 90° phase difference. The phase detection accuracy is within 0.01° (2kHz electrical phase). Practical applications of this invention show that no phase difference wave is detected between the two phase waveforms, that is, the two phase waveform outputs are very close to the standard 90° phase difference, approximately 0° (2kHz electrical angle).

[0021] In the above applications, phase difference detection, i.e. phase discrimination, is an important step. The integral characteristic combined with the phase shifting circuit ensures that the static phase difference with the reference is 0° (2KHz electrical angle).

[0022] Furthermore, the current pump circuit includes capacitor C1, resistor R1, transistor G1, transistor G2, resistor R3, Zener diode D1, capacitor C3, capacitor C2, resistor R2, transistor G3, transistor G4, resistor R4, Zener diode D2, capacitor C4, and resistor R5.

[0023] Transistors G1 and G4 are NPN type transistors, while transistors G2 and G3 are PNP type transistors;

[0024] One end of capacitor C1 and one end of resistor R1 are connected to the first output terminal of the digital circuit. The other end of capacitor C1 and the other end of resistor R1 are connected to the base of transistor G1. The emitter of transistor G1 is connected to ground. The collector of transistor G1 is connected to one end of resistor R3 and the emitter of transistor G2. The other end of resistor R3, one end of Zener diode D1, and one end of capacitor C3 are connected to the positive terminal of the voltage. The other end of Zener diode D1 and the other end of capacitor C3 are connected to the base of transistor G2.

[0025] One end of capacitor C2 and one end of resistor R2 are connected to the second output terminal of the digital circuit. The other end of capacitor C2 and the other end of resistor R2 are connected to the emitter of transistor G3. The base of transistor G3 is connected to ground. The collector of transistor G3 is connected to the emitter of transistor G4 and one end of resistor R4. The other end of resistor R4, the other end of Zener diode D2, and the other end of capacitor C4 are connected to the negative terminal of the voltage. One end of Zener diode D2 and one end of capacitor C4 are connected to the base of transistor G4.

[0026] The other end of capacitor C3 is connected to one end of resistor R5, and the other end of resistor R5 is connected to one end of capacitor C4; the collector of transistor G2 is connected to the collector of transistor G2.

[0027] Furthermore, the RC network includes resistor R6, capacitor C5, capacitor C6 and resistor R8;

[0028] One end of resistor R6 and one end of capacitor C5 are connected to the collector of transistor G2. The other end of resistor R6 is connected to one end of capacitor C6 and resistor R8. The other ends of capacitor C5, capacitor C6 and resistor R8 are connected to ground.

[0029] Furthermore, the field-effect transistor driving circuit includes: LED D3, field-effect transistor G5, and resistor R7;

[0030] The gate of the field-effect transistor G5 is connected to one end of the resistor R8, the drain of the field-effect transistor G5 is connected to the cathode of the light-emitting diode, the anode of the light-emitting diode is connected to the positive terminal of the voltage, the source of the field-effect transistor G5 is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to ground.

[0031] Specifically, refer to Figure 1 The part in dashed box 1 is the current pump circuit, the part in dashed box 2 is the RC network, and the part in dashed box 3 is the field-effect transistor drive circuit.

[0032] Considering the specific inputs from the first and second output terminals of the digital circuit to points A and B of the current pump circuit, respectively, the current pump circuit injects or pulls a fixed current into or out of the RC network. At the point where the RC network corresponds to the gate of the MOSFET G5, the voltage will change. Phase detection information is contained in the relative time changes of the injected or pulled current. However, for the circuit to function properly, the injection or pull current time must be very short. Therefore, in... Figure 1 The linear segment of the phase detection circuit has a range.

[0033] exist Figure 1In the above, when the capacitance of capacitor C6 is greater than that of capacitor C5, and the resistance of resistor R6 is not very large, for example, capacitor C6 = 1μF, capacitor C5 = 0.1μF, and resistor R = 2KΩ, without going into detailed derivation, the current entering the RC network and the gate voltage of the MOSFET G5 have low-pass characteristics. Capacitor C6 and resistor R8 determine the time constant of this low-pass circuit.

[0034] exist Figure 1 In the process, because the gate input resistance of the field-effect transistor G5 is large, the load of the RC network is almost infinite. For the RC network 2, the gate voltage output to the field-effect transistor G5 has almost no load effect.

[0035] In the field-effect transistor (FET) driver circuit, during phase detection, the current generated by the current pump circuit is injected and pulled out by the RC network. The resulting node voltage is used as the gate input voltage of the FET in the driver circuit. This voltage drives the LED D3, causing a change in the photoresistor in the optocoupler resistor containing D3. This, in turn, shifts the phase of the signal in the phase-shifting circuit, achieving phase locking. It should be noted that the phase-shifting circuit is not included in the... Figure 1 middle.

[0036] Furthermore, when the first output terminal of the digital circuit outputs a high level and the second output terminal outputs a low level, transistor G2 is turned off and transistor G4 is turned on. The fixed current pulled out by the current pump circuit from the RC network is... ;

[0037] ,in, This is the regulated voltage value of Zener diode D2. This is the voltage between the base and emitter of the NPN transistor G4. This is the current amplification factor of transistor G4, and the value is very large.

[0038] Specifically, when the first output terminal of the digital circuit inputs a high level to point A of the current pump circuit, and the second output terminal of the digital circuit inputs a low level to point B of the current pump circuit, transistor G1 saturates, causing transistor G2 to be in reverse-biased cutoff state. At the same time, B is at a low level, transistor G3 is cut off, and transistor G4 is working. If this process is quite short, a fixed current is pulled out from the RC network. .

[0039] Furthermore, when the first output terminal of the digital circuit outputs a low level and the second output terminal outputs a high level, transistor G2 is turned on and transistor G4 is turned off. The fixed current injected into the RC network by the current pump circuit is... ;

[0040] ,in, This is the regulated voltage value of Zener diode D1. This is the voltage between the base and emitter of the PNP transistor G2. This is the current amplification factor of transistor G2, and the value is very large.

[0041] Specifically, when the first output terminal of the digital circuit inputs a low level to point A of the current pump circuit, and the second output terminal of the digital circuit inputs a high level to point B of the current pump circuit, transistor G1 is cut off, causing transistor G2 to be in the working state. At the same time, B is at a high level, and transistor G3 is in the cut-off state. If this process is relatively short, transistor G2 injects a fixed current into the RC network 2. .

[0042] When the first output terminal of the digital circuit inputs a high level to point A of the current pump circuit, and the second output terminal of the digital circuit inputs a high level to point B of the current pump circuit... Figure 1 The entire circuit exhibits high impedance to the RC network, remaining unchanged. The first output of the digital circuit inputs a low level to point A of the current pump circuit, and the second output of the digital circuit inputs a low level to point B of the current pump circuit. Figure 1 A logic state that is prohibited in a circuit.

[0043] Furthermore, the voltage between the base and emitter of the NPN transistor G4 .

[0044] Furthermore, the voltage between the base and emitter of the PNP transistor G2 .

[0045] Specifically, refer to Figure 2 , Figure 2 Waveforms A and B represent respectively Figure 1 Input waveforms at points A and B of the medium current pump circuit. Figure 2 In the diagram, C represents the phase detection square wave; I is the rising or falling edge of the signal square wave; and II and III are reference signals. During phase detection, edge I changes, serving as the reference for II and III, and these changes occur over time intervals, leading to… Figure 1 The injection and extraction times of the medium-resistance-capacitor network are different, resulting in different gate voltages of the field-effect transistor G5 and thus different drain currents. This causes the brightness of the LED D3 to change. In the actual circuit, D3 is the LED in the optocoupler resistor. By changing the brightness of D3, the resistance value of the optocoupler is changed, thereby changing the phase and achieving the purpose of phase locking.

[0046] Figure 1 The circuit shown and Figure 2 The logic input shown can form an integral operation of the phase difference by injecting or pulling a fixed current into or out of the RC network 2, i.e., current pumping technology, and combined with the phase shifting stage, achieve the purpose of phase locking.

[0047] Figure 1 The circuit shown has high phase detection accuracy, theoretically has no dead zone, and the switching process of the devices does not affect the phase detection result; because Figure 1 In the process of injecting and extracting current into and from the RC network 2, combined with Figure 2 A change in the position of signal I will inevitably lead to a change in the time span of II-I and I-III. This change will affect the injected or pulled current. Figure 1 The duration of the RC network in the circuit ultimately causes a change in the gate voltage of the field-effect transistor G5, resulting in the output phase detection result.

[0048] Example:

[0049] This application discloses a novel high-precision phase detection circuit that can also be used... Figure 3 The circuit shown demonstrates that, in this case, the phase detection result voltage output is represented by the gate voltage of the field-effect transistor G5, exhibiting low-pass characteristics.

[0050] Figure 3 In the diagram, the part enclosed by dashed box 1 is the current pump circuit, the part enclosed by dashed box 2 is the RC network, and the part enclosed by dashed box 3 is the field-effect transistor drive circuit.

[0051] The current pump circuit includes capacitor C1, resistor R1, transistor G1, transistor G2, resistor R3, Zener diode D1, capacitor C3, capacitor C2, resistor R2, transistor G3, transistor G4, resistor R4, Zener diode D2, capacitor C4, and resistor R5.

[0052] Transistors G1 and G4 are NPN type transistors, while transistors G2 and G3 are PNP type transistors;

[0053] One end of capacitor C1 and one end of resistor R1 are connected to the first output terminal of the digital circuit. The other end of capacitor C1 and the other end of resistor R1 are connected to the base of transistor G1. The emitter of transistor G1 is connected to ground. The collector of transistor G1 is connected to one end of resistor R3 and the emitter of transistor G2. The other end of resistor R3, one end of Zener diode D1, and one end of capacitor C3 are connected to the positive terminal of the voltage. The other end of Zener diode D1 and the other end of capacitor C3 are connected to the base of transistor G2.

[0054] One end of capacitor C2 and one end of resistor R2 are connected to the second output terminal of the digital circuit. The other end of capacitor C2 and the other end of resistor R2 are connected to the emitter of transistor G3. The base of transistor G3 is connected to ground. The collector of transistor G3 is connected to the emitter of transistor G4 and one end of resistor R4. The other end of resistor R4, the other end of Zener diode D2, and the other end of capacitor C4 are connected to the negative terminal of the voltage. One end of Zener diode D2 and one end of capacitor C4 are connected to the base of transistor G4.

[0055] The other end of capacitor C3 is connected to one end of resistor R5, and the other end of resistor R5 is connected to one end of capacitor C4; the collector of transistor G2 is connected to the collector of transistor G2.

[0056] The RC network includes resistor R6, capacitor C5, and capacitor C6;

[0057] One end of resistor R6 and one end of capacitor C5 are connected to the collector of transistor G2. The other end of resistor R6 is connected to one end of capacitor C6. The other ends of capacitor C5 and capacitor C6 are connected to ground.

[0058] The field-effect transistor driver circuit includes: LED D3, field-effect transistor G5, and resistor R7;

[0059] The gate of the field-effect transistor G5 is connected to one end of the resistor R8, the drain of the field-effect transistor G5 is connected to the cathode of the light-emitting diode, the anode of the light-emitting diode is connected to the positive terminal of the voltage, the source of the field-effect transistor G5 is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to ground.

[0060] When the capacitance of capacitor C6 is greater than that of capacitor C5, and the resistance of resistor R6 is not very large, for example, capacitor C6 = 1μF, capacitor C5 = 0.1μF, and resistor R = 2KΩ, then the Laplace transform transfer function between the current entering the RC network and the gate voltage of the field-effect transistor G5 is:

[0061] ,in, This is the gate voltage of the field-effect transistor G5. For the current entering the RC network, Let C6 be the capacitance value, and S be the Laplace transform operator.

[0062] Therefore, Figure 3 The process shown has integral properties.

[0063] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.

Claims

1. A novel high-precision phase detection circuit, characterized in that, include: Current pump circuit, RC network and MOSFET drive circuit; The input terminal of the current pump circuit is connected to the output terminal of the digital circuit. The current pump circuit is used to inject or pull a fixed current into the resistor-capacitor network according to the phase difference of the output signal of the digital circuit. The input terminal of the RC network is connected to the output terminal of the current pump circuit. The RC network is used to convert the fixed current injected or pulled out by the current pump circuit into voltage and input it to the field-effect transistor drive circuit. The input terminal of the field-effect transistor (FET) driver circuit is connected to the output terminal of the resistor-capacitor (RC) network. The FET driver circuit drives the LED according to the input voltage.

2. The novel high-precision phase detection circuit according to claim 1, characterized in that: The current pump circuit includes capacitor C1, resistor R1, transistor G1, transistor G2, resistor R3, Zener diode D1, capacitor C3, capacitor C2, resistor R2, transistor G3, transistor G4, resistor R4, Zener diode D2, capacitor C4, and resistor R5. Transistors G1 and G4 are NPN type transistors, while transistors G2 and G3 are PNP type transistors; One end of capacitor C1 and one end of resistor R1 are connected to the first output terminal of the digital circuit. The other end of capacitor C1 and the other end of resistor R1 are connected to the base of transistor G1. The emitter of transistor G1 is connected to ground. The collector of transistor G1 is connected to one end of resistor R3 and the emitter of transistor G2. The other end of resistor R3, one end of Zener diode D1, and one end of capacitor C3 are connected to the positive terminal of the voltage. The other end of Zener diode D1 and the other end of capacitor C3 are connected to the base of transistor G2. One end of capacitor C2 and one end of resistor R2 are connected to the second output terminal of the digital circuit. The other end of capacitor C2 and the other end of resistor R2 are connected to the emitter of transistor G3. The base of transistor G3 is connected to ground. The collector of transistor G3 is connected to the emitter of transistor G4 and one end of resistor R4. The other end of resistor R4, the other end of Zener diode D2, and the other end of capacitor C4 are connected to the negative terminal of the voltage. One end of Zener diode D2 and one end of capacitor C4 are connected to the base of transistor G4. The other end of capacitor C3 is connected to one end of resistor R5, and the other end of resistor R5 is connected to one end of capacitor C4; the collector of transistor G2 is connected to the collector of transistor G2.

3. The novel high-precision phase detection circuit according to claim 1, characterized in that: The RC network includes resistor R6, capacitor C5, capacitor C6 and resistor R8; One end of resistor R6 and one end of capacitor C5 are connected to the collector of transistor G2. The other end of resistor R6 is connected to one end of capacitor C6 and resistor R8. The other ends of capacitor C5, capacitor C6 and resistor R8 are connected to ground.

4. The novel high-precision phase detection circuit according to claim 1, characterized in that: The field-effect transistor driver circuit includes: LED D3, field-effect transistor G5, and resistor R7; The gate of the field-effect transistor G5 is connected to one end of the resistor R8, the drain of the field-effect transistor G5 is connected to the cathode of the light-emitting diode, the anode of the light-emitting diode is connected to the positive terminal of the voltage, the source of the field-effect transistor G5 is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to ground.

5. A novel high-precision phase detection circuit according to claim 2, characterized in that: When the first output terminal of the digital circuit outputs a high level and the second output terminal of the digital circuit outputs a low level, transistor G2 is turned off and transistor G4 is turned on, and the current pump circuit pulls a fixed current from the RC network.

6. A novel high-precision phase detection circuit according to claim 2, characterized in that: When the first output terminal of the digital circuit outputs a low level and the second output terminal of the digital circuit outputs a high level, transistor G2 is turned on and transistor G4 is turned off, and the current pump circuit injects a fixed current into the RC network.

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