Wireless receiving device

Abstract

The wireless receiving device comprises a master chip and a plurality of wireless receiving modules; the wireless receiving module comprises a signal processing circuit, the signal processing circuit comprises a first voltage follower unit, a second voltage follower unit, a voltage division unit and a first comparison unit, the first voltage follower unit is used for outputting a first voltage based on a peak value of a radio frequency signal, the second voltage follower unit is used for outputing a second voltage based on a valley value of the radio frequency signal, the voltage division unit is connected between the first voltage and the second voltage and has a voltage division node, and the first comparison unit is connected with the voltage division node and is used for generating a trigger signal based on a voltage on the voltage division node and a reference voltage; the wireless receiving module outputs a CMOS level signal based on the radio frequency signal and the voltage on the voltage division node; and after the master chip receives the trigger signal, the high level width and the low level width of the CMOS level signal are acquired. The utility model can receive radio frequency signals of two frequencies, filter out noise signals and only display data of effective signals.

Description

Technical Field

[0001] This utility model belongs to the field of data processing technology, and specifically relates to a wireless receiving device. Background Technology

[0002] Wireless remote control is similar to infrared remote control. It can be summarized as follows: the code is modulated in a certain way to form a radio frequency signal and transmitted through an antenna. The wireless signal receiving chip receives the radio frequency signal and demodulates the original data signal.

[0003] However, wireless reception has a problem: regardless of whether the transmitter is transmitting a signal, the receiver chip will always receive a waveform, i.e., noise signal. This noise signal interferes with normal signals, and typical RF receiving solutions cannot filter it out.

[0004] Therefore, in view of the above-mentioned technical problems, it is necessary to provide a wireless receiving device. Utility Model Content

[0005] The purpose of this invention is to provide a wireless receiving device that can receive radio frequency signals of two frequencies, filter out noise signals, and display only the data of valid signals.

[0006] To achieve the above objectives, the technical solution provided by a specific embodiment of this utility model is as follows:

[0007] A wireless receiving device, the wireless receiving device comprising a main control chip and several wireless receiving modules;

[0008] The wireless receiving module includes a signal processing circuit, which includes a first voltage follower unit, a second voltage follower unit, a voltage divider unit, and a first comparison unit. The first voltage follower unit is connected between the radio frequency signal and a first terminal of the voltage divider unit, and is used to output a first voltage based on the peak value of the radio frequency signal. The second voltage follower unit is connected between the radio frequency signal and a second terminal of the voltage divider unit, and is used to output a second voltage based on the valley value of the radio frequency signal. The voltage divider unit has a voltage divider node and is connected between the first voltage and the second voltage. The first comparison unit is connected to the voltage divider node and is used to generate a trigger signal based on the voltage on the voltage divider node and a reference voltage.

[0009] The wireless receiving module is used to compare the radio frequency signal and the voltage on the voltage divider node and demodulate and output a CMOS level signal.

[0010] The main control chip is connected to the wireless receiving module and is used to determine a valid radio frequency signal based on the trigger signal, and after receiving the trigger signal, to obtain the high-level width and low-level width of the CMOS level signal.

[0011] In one or more embodiments of the present invention, the first voltage follower unit includes a first operational amplifier, a second operational amplifier, a first resistor, and a first MOSFET. The first input terminal of the first operational amplifier receives a radio frequency signal, the second input terminal is connected to the second terminal of the first MOSFET, and the output terminal is connected to the control terminal of the first MOSFET. The first terminal of the first MOSFET is connected to the power supply voltage, and the second terminal is connected to the first input terminal of the second operational amplifier. The second input terminal of the second operational amplifier is connected to the output terminal and outputs a first voltage. The first terminal of the first resistor is connected to the output terminal of the second operational amplifier, and the second terminal is connected to the second voltage follower unit.

[0012] The second voltage follower unit includes a third operational amplifier, a fourth operational amplifier, a second resistor, and a second MOSFET. The first input terminal of the third operational amplifier receives a radio frequency signal, the second input terminal is connected to the second terminal of the second MOSFET, and the output terminal is connected to the control terminal of the second MOSFET. The first terminal of the second MOSFET is connected to ground potential, and the second terminal is connected to the first input terminal of the fourth operational amplifier. The second input terminal of the fourth operational amplifier is connected to the output terminal and outputs a second voltage. The first terminal of the second resistor is connected to the output terminal of the fourth operational amplifier, and the second terminal is connected to the first voltage follower unit.

[0013] In one or more embodiments of this utility model, the voltage divider unit includes a third resistor and a fourth resistor. The first end of the third resistor is connected to a first voltage, and the second end is connected to the first end of the fourth resistor to form the voltage divider node. The second end of the fourth resistor is connected to a second voltage, and the resistance values ​​of the third resistor and the fourth resistor are the same.

[0014] In one or more embodiments of this utility model, the first comparison unit includes a fifth resistor, a sixth resistor, and a first comparator. The first end of the fifth resistor is connected to the input voltage, the second end of the fifth resistor is connected to the first end of the sixth resistor and the second input end of the first comparator, the second end of the sixth resistor is connected to ground potential, the first input end of the first comparator is connected to the voltage divider node, and the output end generates a trigger signal.

[0015] In one or more embodiments of this utility model, the main control chip includes STC8H8K64U.

[0016] In one or more embodiments of the present invention, the wireless receiving device includes two wireless receiving modules, one of which receives a radio frequency signal with a frequency of 315MHz, and the other of which receives a radio frequency signal with a frequency of 433MHz.

[0017] In one or more embodiments of this utility model, the wireless receiving module further includes:

[0018] An ultra-high frequency downconverter is used to receive the radio frequency signal and convert the ultra-high frequency radio frequency signal into an intermediate frequency radio frequency signal;

[0019] The OOK demodulator includes a first filter unit and a second comparator. The input of the first filter unit receives an intermediate frequency radio frequency signal, and its output is connected to the first input of the second comparator. The second input of the second comparator is connected to the voltage divider node, and the output of the second comparator is used to output a CMOS level signal.

[0020] In one or more embodiments of this utility model, the ultra-high frequency downconverter includes:

[0021] Radio frequency amplifiers are used to amplify radio frequency signals;

[0022] Programmable synthesizers are used to generate frequency-controllable local oscillator signals;

[0023] A mixer is used to mix the amplified radio frequency signal with the local oscillator signal to output an intermediate frequency radio frequency signal.

[0024] The first intermediate frequency amplifier, connected to the mixer, is used to amplify the intermediate frequency radio frequency signal generated after mixing.

[0025] A bandpass filter, connected to the first intermediate frequency amplifier, is used for filtering;

[0026] The second intermediate frequency amplifier is connected to the bandpass filter and is used to amplify the filtered intermediate frequency radio frequency signal.

[0027] A peak detector is used to detect the peak envelope of an intermediate frequency signal.

[0028] In one or more embodiments of the present invention, the wireless receiving module includes a receiving antenna, and the wireless receiving module further includes a second filtering unit connected between the antenna and the ultra-high frequency downconverter.

[0029] In one or more embodiments of this utility model, the wireless receiving module further includes a first capacitor connected between the voltage divider node and the ground potential.

[0030] Compared with the prior art, the wireless receiving device of this utility model receives radio frequency signals of at least two frequencies by setting up several wireless receiving modules. By setting up a signal processing circuit, the peak and valley values ​​of the radio frequency signals received by the wireless receiving device are averaged and compared with a reference voltage. If the received signal is a noise signal, no trigger signal is generated; otherwise, a corresponding trigger signal is generated. The main control chip will only acquire the high-level width and low-level width of the CMOS level signal after receiving the signal to be triggered, thus realizing the display of only valid signal data.

[0031] The circuit structure of this invention is simple and can be improved upon existing wireless receiver detection chip circuits. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a structural block diagram of a wireless receiving device according to an embodiment of the present invention;

[0034] Figure 2 This is a schematic diagram of the structure of the wireless receiving module in one embodiment of the present invention;

[0035] Figure 3 for Figure 2 The diagram shows a partial circuit structure of the wireless receiver module.

[0036] Figure 4 This is a circuit diagram of the signal processing circuit in one embodiment of the present invention;

[0037] Figure 5 This is a circuit diagram of the main control chip in one embodiment of the present invention. Detailed Implementation

[0038] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0039] As mentioned in the background technology, commonly used wireless coding schemes include 1527 and 2240, etc. These schemes have significantly different encoding formats, making it difficult to achieve a unified identification of their formats. Traditional decoders require acquiring the voltage level width and determining if the actual voltage level width matches a specific voltage level of a particular coding scheme. Only after a complete match across all voltage levels of the coding scheme can the remote control be identified as transmitting the correct coding scheme, thus successfully decoding the various parts of the code.

[0040] In typical RF receiving solutions, clutter signals cannot be filtered out. This means that the main control chip also needs to acquire the level width of the clutter signal, which increases the additional data processing burden and makes decoding more difficult.

[0041] To address the aforementioned issues, this disclosure provides a wireless receiving device, including a main control chip and several wireless receiving modules.

[0042] The wireless receiving module includes a signal processing circuit, which includes a first voltage follower unit, a second voltage follower unit, a voltage divider unit, and a first comparison unit. The first voltage follower unit is connected between the radio frequency signal and the first terminal of the voltage divider unit, and is used to output a first voltage based on the peak value of the radio frequency signal. The second voltage follower unit is connected between the radio frequency signal and the second terminal of the voltage divider unit, and is used to output a second voltage based on the valley value of the radio frequency signal. The voltage divider unit has a voltage divider node and is connected between the first voltage and the second voltage. The first comparison unit is connected to the voltage divider node and is used to generate a trigger signal based on the voltage on the voltage divider node and a reference voltage.

[0043] The wireless receiver module is used to compare the radio frequency signal and the voltage on the voltage divider node and demodulate the output CMOS level signal;

[0044] The main control chip is connected to the wireless receiving module and is used to determine the valid radio frequency signal based on the trigger signal. After receiving the trigger signal, it acquires the high-level width and low-level width of the CMOS level signal.

[0045] By setting up several wireless receiving modules to receive radio frequency signals of at least two frequencies, and by setting up a signal processing circuit to average the peak and valley values ​​of the radio frequency signals received by the wireless receiving device and compare them with a reference voltage, if the received signal is a noise signal, no trigger signal is generated; otherwise, a corresponding trigger signal is generated. The main control chip will only acquire the high-level width and low-level width of the CMOS level signal after receiving the signal to be triggered, thus realizing the display of only valid signal data.

[0046] The present disclosure will be further described below with reference to specific embodiments.

[0047] Example 1:

[0048] Combination Figures 1-5 As shown, the wireless receiving device includes a main control chip 20 and two wireless receiving modules 10, one of which receives a radio frequency signal with a frequency of 315MHz, and the other receives a radio frequency signal with a frequency of 433MHz.

[0049] The wireless receiver module 10 includes a receiving antenna ANTENNA, a second filtering unit 15, an ultra-high frequency downconverter 13, an OOK demodulator 12, a control circuit 14, a signal processing circuit 11, and a first capacitor C1.

[0050] It is understandable that the receiving antenna ANTENNA is used to receive radio frequency signals. The ultra-high frequency downconverter 13, OOK demodulator 12, control circuit 14 and part of the signal processing circuit 11 (including the first voltage follower unit 111, the second voltage follower unit 112, and the voltage divider unit 113) are integrated inside the receiving chip U1. The second filter unit 15, the first capacitor C1 and the remaining part of the signal processing circuit 11 (i.e. the first comparison unit 114) serve as the peripheral circuit of the receiving chip U1.

[0051] Combination Figure 2 and Figure 3 As shown, a second filter unit 15 is provided between the receiving antenna ANTENNA and the UHF downconverter 13. The second filter unit 15 includes a second capacitor C2, a third capacitor C3, a first inductor L1, and a second inductor L2. The first ends of the second capacitor C2, the second inductor L2, and the third capacitor C3 are connected to the receiving antenna ANTENNA. The second ends of the second capacitor C2, the second inductor L2, and the first inductor L1 are connected to ground potential. The second end of the third capacitor C3 and the first inductor L1 are connected to the ANT pin 2 of the receiving chip U1 (i.e., the input terminal of the UHF downconverter 13).

[0052] Furthermore, the ultra-high frequency downconverter 13 is used to receive the radio frequency signal filtered by the second filtering unit 15. It can be understood that the radio frequency signal filtered by the second filtering unit 15 is an ultra-high frequency radio frequency signal at this time. In this embodiment, the ultra-high frequency radio frequency signal is converted into an intermediate frequency radio frequency signal by the ultra-high frequency downconverter 13.

[0053] It is understood that UHF downconverters are well known in the prior art, so their working principle will not be described in detail here. Any known or unknown UHF downconverter or UNF downconverter can be used here without restriction.

[0054] Combination Figure 3 As shown, exemplarily, the ultra-high frequency downconverter in this embodiment is used to preprocess radio frequency signals, specifically including:

[0055] RF amplifier 131 is used to amplify RF signals;

[0056] Programmable synthesizer 138 is used to generate a frequency-controllable local oscillator signal f. LO ;

[0057] Mixer 132 is used to convert the amplified radio frequency signal f RX With the local oscillator signal f LO Frequency mixing outputs intermediate frequency radio frequency signals to achieve "downconversion";

[0058] The first intermediate frequency amplifier 133 is connected to the mixer 132 and is used to amplify the intermediate frequency radio frequency signal generated after mixing.

[0059] The bandpass filter 134 is connected to the first intermediate frequency amplifier 133 and performs filtering. In this embodiment, the bandpass filter 134 is a fifth-order second-order filter.

[0060] The second intermediate frequency amplifier 135 is connected to the bandpass filter 134 and is used to amplify the filtered intermediate frequency radio frequency signal.

[0061] Peak detector 136 is used to detect the peak envelope of intermediate frequency signal (extract the envelope of amplitude-modulated signal and convert the modulated intermediate frequency signal into baseband envelope signal).

[0062] Automatic gain control (AGC) unit 137 is used to adjust the gain of the RF amplifier 131 and the first or second intermediate frequency amplifier of the mixer 132 based on the signal amplitude output after filtering by the first filter unit 121, so that the receiver can work stably under different signal strengths (avoiding saturation of strong signals and distortion of weak signals).

[0063] It should be noted that those skilled in the art can customize the specific circuit composition of the ultra-high frequency downconverter according to actual needs.

[0064] Furthermore, the control circuit 14 in this embodiment includes a reference oscillator 141 and a control logic unit 142. The reference oscillator 141 is connected to an external crystal Y1 via the REFOSC pin of the receiving chip U1 and generates a reference clock to provide a time reference for the entire system. The control logic unit 142 is used to coordinate the operation of modules such as the programmable synthesizer 138, the resettable counter, and the first filter unit 121, and to realize function configuration and state management so that the programmable synthesizer 138 generates a local oscillator signal f with a controllable frequency. LO .

[0065] It should be noted that the control circuit 14 is well known in the prior art, so its working principle will not be described in detail here. Any known or unknown reference oscillator and control logic unit can be used here without restriction.

[0066] like Figure 4 As shown, the signal processing circuit 11 includes a first voltage follower unit 111, a second voltage follower unit 112, a voltage divider unit 113, and a first comparison unit 114. The first voltage follower unit 111 is connected between the radio frequency signal and the first terminal C of the voltage divider unit, and is used to output a first voltage V based on the peak value of the radio frequency signal. C The second voltage follower unit 112 is connected between the preprocessed radio frequency signal and the second terminal D of the voltage divider unit 113, and is used to output a second voltage V based on the valley value of the radio frequency signal. D The voltage divider unit 113 has a voltage divider node Pv and is connected to the first voltage V. C Second voltage V D Between them, the first comparison unit 114 is connected to the voltage divider node Pv and is used to generate a trigger signal Output1 based on the voltage Vout on the voltage divider node and the reference voltage Vf.

[0067] Further, in this embodiment, the first voltage follower unit 111 includes a first operational amplifier OP1, a second operational amplifier OP2, a first resistor R1, and a first MOSFET MP1. The first input terminal of the first operational amplifier OP1 receives a pre-processed radio frequency signal ANT2 (here, the pre-processed radio frequency signal ANT2 is an intermediate frequency radio frequency signal filtered by the second filtering unit 121). The second input terminal is connected to the second terminal of the first MOSFET MP1, and the output terminal is connected to the control terminal of the first MOSFET MP1. The first terminal of the first MOSFET is connected to the power supply voltage VDD, and the second terminal is connected to the first input terminal of the second operational amplifier OP2. The second input terminal of the second operational amplifier OP2 is connected to the output terminal of the second operational amplifier OP2 and outputs a first voltage V. C (i.e., the voltage on the first terminal C of the voltage divider unit), the first terminal of the first resistor R1 is connected to the output terminal of the second operational amplifier OP2, and the second terminal is connected to the second voltage follower unit 112.

[0068] In this embodiment, the first terminal of the first MOS transistor MP1 is the source, the second terminal is the drain, and the control terminal is the gate.

[0069] The second voltage follower unit 112 includes a third operational amplifier OP3, a fourth operational amplifier OP4, a second resistor R2, and a second MOSFET MN2. The first input terminal of the third operational amplifier OP3 receives the pre-processed radio frequency signal ANT2 (here, the pre-processed radio frequency signal ANT2 is the intermediate frequency radio frequency signal filtered by the second filtering unit 121). The second input terminal is connected to the second terminal of the second MOSFET MN2, and the output terminal is connected to the control terminal of the second MOSFET MN2. The first terminal of the second MOSFET MN2 is connected to ground potential, and the second terminal is connected to the first input terminal of the fourth operational amplifier OP4. The second input terminal of the fourth operational amplifier OP4 is connected to the output terminal of the fourth operational amplifier OP4 and outputs the second voltage V. D (i.e., the voltage on the second terminal D of the voltage divider unit), the first terminal of the second resistor R2 is connected to the output terminal of the fourth operational amplifier OP4, and the second terminal of the second resistor R2 is connected to the first voltage follower unit 111.

[0070] In this embodiment, the first terminal of the second MOS transistor MN2 is the source, the second terminal is the drain, and the control terminal is the gate.

[0071] Voltage divider unit 113 includes a third resistor R3 and a fourth resistor R4. The first terminal of the third resistor R3 is connected to the first voltage V. C The second terminal is connected to the first terminal of the fourth resistor R4, forming a voltage divider node Pv. The second terminal of the fourth resistor R4 is connected to the second voltage V. D They are connected together, and the resistance values ​​of the third resistor R3 and the fourth resistor R4 are the same.

[0072] Understandably, the voltage at node A theoretically follows the pre-processed RF signal ANT2. However, the strong pull-up capability of the first MOSFET MP1 and the weak pull-down capability of the second resistor R2 cause the voltage at node A to rise rapidly but fall slowly. Therefore, the voltage at node A will remain close to the peak voltage of Vin for a long time. Based on the connection of the second operational amplifier OP2, the voltage at the first terminal C of the voltage divider unit is equal to the voltage at node A. Similarly, the strong pull-down capability of the second MOSFET MN2 and the weak pull-up capability of the first resistor R1 cause the voltage at node B to be approximately equal to the valley voltage of Vin. Based on the connection of the fourth operational amplifier OP4, the voltage at the second terminal D of the voltage divider unit is equal to the voltage at node B.

[0073] Since the resistance of the third resistor R3 is equal to that of the fourth resistor R4, the voltage Vout at the voltage divider node is approximately equal to the average of the peak voltage and valley voltage of the preprocessed RF signal ANT2.

[0074] The first comparison unit 114 includes a fifth resistor R5, a sixth resistor R6, and a first comparator Comp1. The first end of the fifth resistor R5 is connected to the input voltage, and the second end is connected to the first end of the sixth resistor R6 and the second input end of the first comparator Comp1 to generate a reference voltage Vf. The second end of the sixth resistor R6 is connected to ground potential. The first input end of the first comparator Comp1 is connected to the voltage divider node Pv, and the output end of the first comparator Comp1 generates a trigger signal Output1.

[0075] For example, in this embodiment, the input voltage is 5V. The first comparison unit 114 compares the voltage Vout on the voltage divider node with the reference voltage Vf. When the voltage Vout on the voltage divider node is greater than the reference voltage Vf, a trigger signal Output1 is generated; otherwise, no trigger signal Output1 is generated.

[0076] The OOK demodulator 12 in this embodiment includes a first filter unit 121 and a second comparator Comp2. The input of the first filter unit 121 receives the intermediate frequency radio frequency signal ANT1 (i.e., the radio frequency signal processed by the ultra-high frequency downconverter), and the output is connected to the first input of the second comparator Comp2 and outputs the pre-processed radio frequency signal ANT2. The second input of the second comparator Comp2 is connected to the voltage divider node. The second comparator is used to compare the pre-processed radio frequency signal ANT2 with the voltage on the voltage divider node and demodulate and output the CMOS level signal DATA1.

[0077] Furthermore, the wireless receiving module also includes a first capacitor C1, which is connected between the voltage divider node Pv and the ground potential.

[0078] It is understood that the above content only describes one of the wireless receiving modules 10 in detail. In fact, the two wireless receiving modules 10 have the same structure, with only some resistance values ​​and frequency settings being different, so as to receive radio frequency signals of different frequencies respectively.

[0079] The main control chip 20 is connected to the output of the first comparator Comp1 and receives the trigger signal Output1, and is also connected to the output of the second comparator Comp2 and receives the CMOS level signal DATA1.

[0080] The trigger signal Output1 is used to trigger the main control chip 20 to start working. Specifically, the main control chip 20 determines a valid radio frequency (RF) signal based on the trigger signal Output1. That is, when the main control chip 20 receives the trigger signal Output1, it indicates that the RF signal is not noise, and the main control chip 20 begins to receive and acquire CMOS level signals, and analyzes the high-level and low-level widths of the CMOS level signals. When the main control chip 20 does not receive the trigger signal Output1, it indicates that the RF signal is noise, and the main control chip 20 does not receive and acquire CMOS level signals.

[0081] like Figure 5 As shown, the main control chip 20 in this embodiment includes an STC8H8K64U and its peripheral circuitry. It is understood that the STC8H8K64U is well-known in the prior art. This embodiment utilizes common functions of MCUs such as the STC8H8K64U and does not involve any improvement to the method. Therefore, its working principle will not be described in detail here, and any known or unknown MCU can be used without restriction.

[0082] In this embodiment, pin P3.6 of the STC8H8K64U is connected to the output of the first comparator Comp1 of one of the wireless receiver modules to receive the corresponding trigger signal, and pin P3.7 is connected to the output of the first comparator Comp1 of another wireless receiver module to receive the corresponding trigger signal. Pin P3.4 of the STC8H8K64U is connected to the output of the second comparator Comp2 of one of the wireless receiver modules to receive the corresponding CMOS level signal, and pin P3.5 is connected to the output of the second comparator Comp2 of another wireless receiver module to receive the corresponding CMOS level signal.

[0083] As can be seen from the above technical solutions, this utility model has the following beneficial effects:

[0084] By setting up several wireless receiving modules to receive radio frequency signals of at least two frequencies, and by setting up a signal processing circuit to average the peak and valley values ​​of the radio frequency signals received by the wireless receiving device and compare them with a reference voltage, if the received signal is a noise signal, no trigger signal is generated; otherwise, a corresponding trigger signal is generated. The main control chip will only acquire the high-level width and low-level width of the CMOS level signal after receiving the signal to be triggered, thus realizing the display of data of only valid signals.

[0085] The circuit structure of this invention is simple and can be improved upon existing wireless receiver detection chip circuits.

[0086] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0087] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A wireless receiving device, characterized in that, The wireless receiving device includes a main control chip and several wireless receiving modules; The wireless receiving module includes a signal processing circuit, which includes a first voltage follower unit, a second voltage follower unit, a voltage divider unit, and a first comparison unit. The first voltage follower unit is connected between the radio frequency signal and a first terminal of the voltage divider unit, and is used to output a first voltage based on the peak value of the radio frequency signal. The second voltage follower unit is connected between the radio frequency signal and a second terminal of the voltage divider unit, and is used to output a second voltage based on the valley value of the radio frequency signal. The voltage divider unit has a voltage divider node and is connected between the first voltage and the second voltage. The first comparison unit is connected to the voltage divider node and is used to generate a trigger signal based on the voltage on the voltage divider node and a reference voltage. The wireless receiving module is used to compare the radio frequency signal and the voltage on the voltage divider node and demodulate and output a CMOS level signal. The main control chip is connected to the wireless receiving module and is used to determine a valid radio frequency signal based on the trigger signal, and after receiving the trigger signal, to obtain the high-level width and low-level width of the CMOS level signal.

2. The wireless receiving device according to claim 1, characterized in that, The first voltage follower unit includes a first operational amplifier, a second operational amplifier, a first resistor, and a first MOSFET. The first input terminal of the first operational amplifier receives a radio frequency signal, its second input terminal is connected to the second terminal of the first MOSFET, and its output terminal is connected to the control terminal of the first MOSFET. The first terminal of the first MOSFET is connected to a power supply voltage, and its second terminal is connected to the first input terminal of the second operational amplifier. The second input terminal of the second operational amplifier is connected to its output terminal and outputs a first voltage. The first terminal of the first resistor is connected to the output terminal of the second operational amplifier, and its second terminal is connected to the second voltage follower unit; and / or, The second voltage follower unit includes a third operational amplifier, a fourth operational amplifier, a second resistor, and a second MOSFET. The first input terminal of the third operational amplifier receives a radio frequency signal, the second input terminal is connected to the second terminal of the second MOSFET, and the output terminal is connected to the control terminal of the second MOSFET. The first terminal of the second MOSFET is connected to ground potential, and the second terminal is connected to the first input terminal of the fourth operational amplifier. The second input terminal of the fourth operational amplifier is connected to the output terminal and outputs a second voltage. The first terminal of the second resistor is connected to the output terminal of the fourth operational amplifier, and the second terminal is connected to the first voltage follower unit.

3. The wireless receiving device according to claim 1, characterized in that, The voltage divider unit includes a third resistor and a fourth resistor. The first end of the third resistor is connected to a first voltage, and the second end is connected to the first end of the fourth resistor to form the voltage divider node. The second end of the fourth resistor is connected to a second voltage. The resistance values ​​of the third resistor and the fourth resistor are the same.

4. The wireless receiving device according to claim 1, characterized in that, The first comparison unit includes a fifth resistor, a sixth resistor, and a first comparator. The first end of the fifth resistor is connected to the input voltage, and the second end is connected to the first end of the sixth resistor and the second input end of the first comparator to generate a reference voltage. The second end of the sixth resistor is connected to ground potential. The first input end of the first comparator is connected to the voltage divider node, and the output end generates a trigger signal.

5. The wireless receiving device according to claim 1, characterized in that, The main control chip includes STC8H8K64U.

6. The wireless receiving device according to claim 1, characterized in that, The wireless receiving device includes two wireless receiving modules, one of which receives radio frequency signals at a frequency of 315MHz, and the other of which receives radio frequency signals at a frequency of 433MHz.

7. The wireless receiving device according to claim 1, characterized in that, The wireless receiving module further includes: An ultra-high frequency downconverter is used to receive the radio frequency signal and convert the ultra-high frequency radio frequency signal into an intermediate frequency radio frequency signal; The OOK demodulator includes a first filter unit and a second comparator. The input of the first filter unit receives an intermediate frequency radio frequency signal, and its output is connected to the first input of the second comparator. The second input of the second comparator is connected to the voltage divider node, and the output of the second comparator is used to output a CMOS level signal.

8. The wireless receiving device according to claim 7, characterized in that, The ultra-high frequency downconverter includes: Radio frequency amplifiers are used to amplify radio frequency signals; Programmable synthesizers are used to generate frequency-controllable local oscillator signals; A mixer is used to mix the amplified radio frequency signal with the local oscillator signal to output an intermediate frequency radio frequency signal. The first intermediate frequency amplifier, connected to the mixer, is used to amplify the intermediate frequency radio frequency signal generated after mixing. A bandpass filter, connected to the first intermediate frequency amplifier, is used for filtering; The second intermediate frequency amplifier, connected to the bandpass filter, is used to amplify the filtered intermediate frequency radio frequency signal.

9. The wireless receiving device according to claim 7, characterized in that, The wireless receiving module has a receiving antenna, and the wireless receiving module also includes a second filtering unit, which is connected between the antenna and the ultra-high frequency downconverter.

10. The wireless receiving device according to claim 1, characterized in that, The wireless receiving module further includes a first capacitor, which is connected between the voltage divider node and the ground potential.

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