Wireless transceiver and wireless base station

Abstract

The application discloses a wireless transceiver and a wireless base station, and belongs to the technical field of wireless communication, which comprises a processing module and a radio frequency transceiver module connected with each other, the processing module comprises an integrated processor and a field programmable gate array; the field programmable gate array comprises a first low-voltage differential signal interface, the processor comprises a first serial peripheral interface, and the radio frequency transceiver module comprises a second low-voltage differential signal interface and a second serial peripheral interface; the first low-voltage differential signal interface is connected with the second low-voltage differential signal interface, and the first low-voltage differential signal interface and the second low-voltage differential signal interface are used for transmitting first baseband data between the field programmable gate array and the radio frequency transceiver module; and the first serial peripheral interface is connected with the second serial peripheral interface. By adopting the integrated processing module to replace traditional discrete digital devices, the application realizes the integration of functions such as digital signal processing, waveform algorithm, protocol and interface processing, and significantly reduces the hardware cost of the system.

Description

Technical Field

[0001] This application relates to the field of wireless communication technology, and more specifically, to a wireless transceiver and a wireless base station. Background Technology

[0002] With the rapid development of wireless communication technology, transceivers play a crucial role in wireless communication systems. Through functions such as power amplification, image rejection, filtering, and frequency conversion, they convert the radio frequency signals received by the antenna into low-frequency signals for digital processing at the back end, or up-convert and amplify baseband signals to convert them into radio frequency signals transmitted by the antenna. However, traditional wireless communication systems are typically designed with different hardware platforms based on specific user needs to support different frequency bands, standards, and data formats. Their relatively limited functionality leads to difficulties in interoperability and poor compatibility among various systems. Furthermore, some transceiver systems often employ complex hardware methods to implement multiple service functions, which are not only costly, bulky, and energy-intensive, but also have poor scalability.

[0003] In areas such as intermediate frequency digital signal processing, waveform algorithms, protocols, and interface processing, the architecture is usually based on Advanced Reduced Instruction Set Machine (ARM) + Digital Signal Processor (DSP) + Field-Programmable Gate Array (FPGA). Although this approach can meet the functional requirements of generalization, standardization, and reconfigurability, it suffers from high hardware overhead and high power consumption, making it difficult to meet the power consumption, size, and cost requirements of portable devices. Utility Model Content

[0004] This application proposes a wireless transceiver and a wireless base station to improve the above-mentioned defects.

[0005] In a first aspect, this application provides a wireless transceiver, comprising: a processing module and a radio frequency transceiver module interconnected thereto; the processing module including an integrated processor and a field-programmable gate array (FPGA); the FPGA including a first low-voltage differential signal interface (LDSA); the processor including a first serial peripheral interface (SPI); and the FPGA including a second LDSA and a second SPI; the first LDSA and the second LDSA are connected and used to transmit first baseband data between the FPGA and the FPGA; the first SPI and the second SPI are connected and used to transmit first configuration data of the FPGA between the processor and the FPGA.

[0006] Optionally, in one possible implementation, the processor includes a network interface for connecting to a host, the network interface for transmitting second configuration data of the RF transceiver module between the host and the processor, the first configuration data and the second configuration data having a first preset conversion relationship; the field-programmable gate array includes a peripheral component interconnect (PCI) interface for connecting to a host, the PCI interface for transmitting second baseband data between the host and the PCI, the first baseband data and the second baseband data having a second preset conversion relationship.

[0007] Optionally, in one possible implementation, the peripheral component interconnect expansion interface is a PCIe Gen3x8 interface.

[0008] Optionally, in one possible implementation, the radio frequency transceiver module includes a transmitting submodule and a receiving submodule, wherein the input terminal of the transmitting submodule is connected to the second low-voltage differential signal interface, and the output terminal of the receiving submodule is connected to the second low-voltage differential signal interface.

[0009] Optionally, in one possible implementation, the receiving submodule includes a first antenna, a low-noise amplifier, a first mixer, a second mixer, a first low-pass filter, a second low-pass filter, a first analog-to-digital converter, a second analog-to-digital converter, a phase-locked loop (PLL), and a phase divider; the output terminal of the PLL is connected to the input terminal of the phase divider for outputting a first clock signal, the first output terminal of the phase divider is connected to the first input terminal of the first mixer for outputting the first clock signal, and the second output terminal of the phase divider is connected to the first input terminal of the second mixer for outputting a second clock signal, wherein the phase difference between the second clock signal and the first clock signal is a non-zero preset value; The first antenna is connected to the input terminal of the low-noise amplifier. The output terminal of the low-noise amplifier is connected to the second input terminal of the first mixer and the second input terminal of the second mixer. The output terminal of the first mixer is connected to the input terminal of the first low-pass filter. The output terminal of the first low-pass filter is connected to the input terminal of the first analog-to-digital converter (ADC). The output terminal of the first ADC is connected to the second low-voltage differential signal interface. The output terminal of the second mixer is connected to the input terminal of the second low-pass filter. The output terminal of the second low-pass filter is connected to the input terminal of the second ADC. The output terminal of the second ADC is connected to the second low-voltage differential signal interface.

[0010] Optionally, in one possible implementation, the transmitting submodule includes a second antenna, a signal combiner, a power amplifier, a third low-pass filter, a fourth low-pass filter, a third mixer, a fourth mixer, a first digital-to-analog converter (DAC), and a second DAC; the first output terminal of the phase divider is connected to the first input terminal of the third mixer, and the second output terminal of the phase divider is connected to the first input terminal of the fourth mixer; the second low-voltage differential signal interface is connected to the input terminal of the first DAC for outputting a first baseband signal, and the second low-voltage differential signal interface is connected to the input terminal of the second DAC for outputting a second baseband signal; the first baseband data includes the first baseband signal and the second baseband signal. The signal is configured as follows: the output of the first digital-to-analog converter is connected to the input of the third low-pass filter, the output of the third low-pass filter is connected to the second input of the third mixer, and the output of the third mixer is connected to the first input of the signal combiner, for outputting a first radio frequency signal; the output of the second digital-to-analog converter is connected to the input of the fourth low-pass filter, the output of the fourth low-pass filter is connected to the second input of the fourth mixer, and the output of the fourth mixer is connected to the second input of the signal combiner, for outputting a second radio frequency signal; the output of the signal combiner is connected to the input of the power amplifier, for outputting the combined radio frequency signal; and the output of the power amplifier is connected to the second antenna.

[0011] Optionally, in one possible implementation, it further includes: a clock module, connected to both the processing module and the radio frequency transceiver module, for providing a synchronization clock signal to both the processing module and the radio frequency transceiver module.

[0012] Optionally, in one possible implementation, it further includes: a power supply module, connected to the processing module and the radio frequency transceiver module respectively, for providing power to the processing module and the radio frequency transceiver module.

[0013] Optionally, in one possible implementation, it further includes: a temperature sensor, a heat sink, and a thermal management module; the temperature sensor and the heat sink are respectively connected to the thermal management module; the temperature sensor is disposed on the processing module and the radio frequency transceiver module for collecting the temperature of the processing module and the radio frequency transceiver module; the heat sink is disposed on the processing module and the radio frequency transceiver module for reducing the temperature of the processing module and the radio frequency transceiver module.

[0014] Secondly, this application also provides a wireless base station, including: a host, a baseband unit, and the aforementioned wireless transceiver; the peripheral component interconnection expansion interface of the wireless transceiver is connected to the host, the peripheral component interconnection expansion interface is used to transmit second baseband data between the host and the wireless transceiver, the task corresponding to the second baseband data is a non-real-time task; the wireless transceiver is connected to the baseband unit and is used to transmit third baseband data between the wireless transceiver and the baseband unit, the task corresponding to the third baseband data includes a real-time task, the first baseband data and the third baseband data have a third preset conversion relationship, and the baseband unit is used to perform digital signal processing on the third baseband data.

[0015] This application provides a wireless transceiver, comprising: a processing module and a radio frequency transceiver module interconnected thereto. The processing module includes an integrated processor and a field-programmable gate array (FPGA). The FPGA includes a first low-voltage differential signal interface (LDSA). The processor includes a first serial peripheral interface (SPI). The FPGA includes a second LDSA and a second SPI. The first LDSA and the second LDSA are connected and used to transmit first baseband data between the FPGA and the FPGA. The first SPI and the second SPI are connected and used to transmit first configuration data of the FPGA between the processor and the FPGA.

[0016] Compared to the traditional ARM+DSP+FPGA architecture for communication, this approach suffers from high hardware overhead and power consumption. However, in this embodiment, the processing module includes an integrated processor and a field-programmable gate array (FPGA). By replacing traditional discrete digital devices with an integrated processing module, it achieves the integration of digital signal processing, waveform algorithms, and protocol and interface processing functions, significantly reducing system hardware overhead and solving the problem of hardware complexity in the existing ARM+DSP+FPGA architecture. This effectively meets the requirements of portable devices in terms of power consumption, size, and cost.

[0017] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of the transceiver provided in an embodiment of this application is shown; Figure 2 A schematic diagram of the transceiver provided in another embodiment of this application is shown; Figure 3 This paper illustrates a schematic diagram of the workflow of the transceiver provided in an embodiment of this application; Figure 4 A schematic diagram illustrating the workflow of a transceiver provided in another embodiment of this application is shown; Figure 5 A schematic diagram of the transceiver provided in another embodiment of this application is shown; Figure 6 A schematic diagram of an existing superheterodyne radio frequency architecture is shown. Figure 7 A schematic diagram of the receiving submodule provided in an embodiment of this application is shown; Figure 8 This paper shows a schematic diagram of the structure of the transmitting submodule provided in an embodiment of this application; Figure 9 A schematic diagram of the structure of a wireless base station provided in an embodiment of this application is shown. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of them. The components of the embodiments of the present application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without inventive effort are within the scope of protection of the present application.

[0021] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] With the rapid development of wireless communication technology, transceivers play a crucial role in wireless communication systems. Through functions such as power amplification, image rejection, filtering, and frequency conversion, they convert the radio frequency signals received by the antenna into low-frequency signals for digital processing at the back end, or up-convert and amplify baseband signals to convert them into radio frequency signals transmitted by the antenna. However, traditional radio communication systems are typically designed with different hardware platforms based on specific user needs to support different frequency bands, standards, and data formats. Their relatively limited functionality leads to difficulties in interoperability and poor compatibility among various systems. Furthermore, some transceiver systems often employ complex hardware methods to implement multiple service functions, which are not only costly, bulky, and energy-intensive, but also have poor scalability.

[0023] In areas such as intermediate frequency digital signal processing, waveform algorithms, protocols, and interface processing, the architecture is usually based on ARM+DSP+FPGA. Although this approach can meet the functional requirements of generalization, standardization, and reconfigurability, it suffers from high hardware overhead and high power consumption, making it difficult to meet the requirements of portable devices in terms of power consumption, size, and cost.

[0024] Therefore, in this application embodiment, a wireless transceiver and a wireless base station are provided to solve or partially solve the above problems.

[0025] Please see Figure 1 The diagram shows a schematic of the structure of a wireless transceiver 100 provided in an embodiment of this application, including: a processing module 110 and a radio frequency transceiver module 120 connected to each other. The processing module 110 includes an integrated processor 111 and a field programmable gate array 112.

[0026] The field-programmable gate array 112 includes a first low-voltage differential signal interface, the processor 111 includes a first serial peripheral interface, and the radio frequency transceiver module 120 includes a second low-voltage differential signal interface and a second serial peripheral interface.

[0027] The first low-voltage differential signal interface is connected to the second low-voltage differential signal interface, and the first low-voltage differential signal interface and the second low-voltage differential signal interface are used to transmit the first baseband data between the field programmable gate array 112 and the radio frequency transceiver module 120.

[0028] The first serial peripheral interface is connected to the second serial peripheral interface, and the first serial peripheral interface and the second serial peripheral interface are used to transmit the first configuration data of the radio frequency transceiver module 120 between the processor 111 and the radio frequency transceiver module 120.

[0029] It should be noted that the RF transceiver module 120 can convert baseband signals into RF signals for transmission, and can also convert received RF signals into baseband signals. The processing module 110 can process the baseband signals received from the RF transceiver module 120 and transmit the processed signals to the control device, or process the baseband signals received from the control device and transmit the processed signals to the RF transceiver module 120. The processing module 110 can also process configuration information received from the RF transceiver module 120 and transmit the processed signals to the control device, or process configuration data received from the control device and transmit the processed data to the RF transceiver module 120.

[0030] Understandably, Low Voltage Differential Signaling (LVDS) is also called an LVDS interface. An LVDS interface can implement simplex, half-duplex, or full-duplex communication, depending on the specific requirements. Similarly, a Serial Peripheral Interface (SPI) is also called an SPI interface. An SPI interface can also implement simplex, half-duplex, or full-duplex communication, depending on the specific requirements.

[0031] In one implementation scenario of configuring the radio frequency transceiver module 120, the processor 111 transmits first configuration data to the radio frequency transceiver module 120 through the first serial peripheral interface. The radio frequency transceiver module 120 performs parameter configuration based on the received first configuration data. After completing the parameter configuration, the radio frequency transceiver module 120 can transmit and receive radio frequency data.

[0032] In one data transmission scenario, the field-programmable gate array 112 transmits the first baseband data to the radio frequency transceiver module 120 through the first low-voltage differential signal interface. Based on the received first baseband data, the radio frequency transceiver module 120 up-converts the data to obtain the transmitted radio frequency signal. The radio frequency transceiver module 120 then transmits the acquired radio frequency signal in the form of radio waves.

[0033] In one data receiving scenario, the radio frequency transceiver module 120 down-converts the received radio frequency signal into first baseband data. Then, the radio frequency transceiver module 120 transmits the first baseband data to the field programmable gate array 112 through the second low-voltage differential signal interface. The field programmable gate array 112 then processes the first baseband data and transmits the processed data to other control devices.

[0034] Compared to the traditional ARM+DSP+FPGA architecture for communication, this approach suffers from high hardware overhead and power consumption. However, in this embodiment, the processing module includes an integrated processor and a field-programmable gate array (FPGA). By replacing traditional discrete digital devices with an integrated processing module, it achieves the integration of digital signal processing, waveform algorithms, and protocol and interface processing functions, significantly reducing system hardware overhead and solving the problem of hardware complexity in the existing ARM+DSP+FPGA architecture. This effectively meets the requirements of portable devices in terms of power consumption, size, and cost.

[0035] Please see Figure 2 It shows a schematic diagram of another wireless transceiver 100 provided in an embodiment of this application. The processor 111 includes a network interface for connecting to a host 130. The network interface is used to transmit second configuration data of the radio frequency transceiver module between the host 130 and the processor 111. The first configuration data and the second configuration data have a first preset conversion relationship.

[0036] The field-programmable gate array 112 includes a peripheral component interconnection expansion interface, which is used to connect to the host 130. The peripheral component interconnection expansion interface is used to transmit second baseband data between the host 130 and the field-programmable gate array 112. The first baseband data and the second baseband data have a second preset conversion relationship.

[0037] It should be noted that network interfaces include Ethernet interfaces or fiber optic interfaces, which can be used to transmit data between the processor and the host.

[0038] For example, the Ethernet interface can be a Gigabit Ethernet (GE) interface, and the Peripheral Component Interconnect Express (PCIE) interface is called a PCIE interface.

[0039] In one alternative embodiment, the host can be a Linux host, a Windows host, or a macOS host, and the processing module can be a heterogeneous chip of a processor and a programmable gate array. The processing module can also be a system-on-chip field-programmable gate array (SOC FPGA) device. The peripheral component interconnection expansion interface is a PCIe Gen3x8 interface, which is a third-generation high-speed serial expansion component interface with eight channels.

[0040] Compared to traditional GE network interfaces for transmitting baseband data, this application uses a PCIe Gen3x8 interface to transmit second-band baseband data between the host and the field-programmable gate array, achieving efficient data transmission. The uplink and downlink single-sided data bandwidth of PCIe Gen3x8 is 64Gbps without considering slight encoding overhead, which can meet the bandwidth requirements of the fronthaul interface with 4 channels for transmission and 4 channels for reception, improving the overall processing efficiency and real-time performance of the system and meeting the ever-increasing demand for high bandwidth.

[0041] It is understood that the first baseband data and the second baseband data have a second preset conversion relationship. During the transmission of radio frequency data, the host transmits the second baseband data to the peripheral component interconnection expansion interface. The field-programmable gate array (FPGA) converts the second baseband data (including baseband data processing and forwarding) into the first baseband data according to the second preset conversion relationship, and transmits the first baseband data to the radio frequency transceiver module through the LVDS interface. During the reception of radio frequency data, the radio frequency transceiver module transmits the first baseband data to the FPGA through the LVDS interface. The FPGA then converts the first baseband data (including baseband data processing and forwarding) into the second baseband data according to the second preset conversion relationship.

[0042] An example, such as Figure 3 The diagram illustrates the workflow of the transceiver provided in this embodiment. The host is a Linux host, the RF transceiver module is a CX9450 RF transceiver, and the processing module is a SOC FPGA device, specifically a Kosmo2 series PG2K400 device. The PG2K400 device includes a dual-core Cortex-A53 processor unit, a 28nm programmable logic array, and abundant input / output (IO) peripherals. The field-programmable gate array is the PG2K400 FPGA logic. The PG2K400 FPGA logic side realizes data transmission with the Linux host through a PCIe Gen3x8 interface and communicates with the CX9450 RF transceiver through an LVDS interface.

[0043] Specifically, the Linux host can execute "protocol stack software processing," including implementing the higher-level communication protocol stack and performing non-real-time processing tasks such as encapsulation / decapsulation, encryption / decryption, etc., of user data. The Linux host sends downlink baseband data to the PCIe Gen3x8 hard core interface on the PG2K400 FPGA logic side via the PCIe interface. After receiving the downlink baseband data, the PG2K400 FPGA logic side sends the baseband data to the RF transceiver via the LVDS interface. The RF transceiver performs up-conversion and other processing before finally transmitting the signal wirelessly. Conversely, for uplink reception, the RF transceiver's receiving channel mixes the received RF signal to baseband, then digitizes it via analog-to-digital conversion before transmitting it through the LVDS interface to the PCIe Gen3x8 hard core interface on the PG2K400 FPGA logic side, sending the baseband data to the Linux host. The Linux host then performs subsequent demodulation and other baseband data processing.

[0044] Specifically, the PG2K400 FPGA logic side includes Direct Memory Access (DMA), AXIInterconnect bus matrix, and baseband data processing and forwarding operations. The main function of DMA is to detect the arrival of PCIe interface data, move the data to the specified address on the AXI bus, and then trigger an interrupt notification logic unit. The main function of AXIInterconnect is to receive the data moved by DMA and distribute the data to the baseband processing unit according to the address mapping. In the downlink direction (transmitting RF data), the main function of baseband data processing and forwarding is to receive the baseband data distributed by the AXI bus, add physical layer encapsulation such as synchronization headers and CRC checks, and send it to the RF module through the LVDS interface. In the uplink direction (receiving RF data), the main function of baseband data processing and forwarding is to receive the LVDS baseband data stream from the RF module, complete preprocessing such as frame synchronization and symbol demapping, and push the data to the AXI bus for PCIe upload to the Linux host.

[0045] It is understood that the first configuration data and the second configuration data have a first preset conversion relationship. During the transmission of radio frequency data, the host transmits the second configuration data to the processor through the network interface. The processor converts the second configuration data (including format conversion, etc.) into the first configuration data according to the first preset conversion relationship, and transmits the first configuration data to the radio frequency transceiver module through the SPI interface. During the reception of radio frequency data, the radio frequency transceiver module transmits the first configuration data to the processor through the SPI interface. The processor converts the first configuration data (including format conversion, etc.) into the second configuration data according to the first preset conversion relationship.

[0046] It should be noted that the internal structure of an RF transceiver module is quite complex, and the number of configuration parameters required for its operation is substantial. Some devices alone have thousands of registers in their Automatic Gain Control (AGC) unit. Therefore, the processor of the processing module can handle the reading and writing of these parameters. The host computer can send parameters such as the center frequency, bandwidth, gain, filter, and clock settings required for the RF transceiver module's operation to the processor via an Ethernet interface. The processor, upon receiving the parameter configuration information, then writes it back to the RF transceiver module via the SPI port. Conversely, the host computer can also read back the required parameter configuration information from the RF transceiver module through the provided parameter configuration pathway.

[0047] An example, such as Figure 4 The diagram illustrates the workflow of a transceiver provided in another embodiment of this application. The host is a Linux host, the RF transceiver module is an RF transceiver CX9450, and the processing module is a SOC FPGA device, specifically a Kosmo2 series PG2K400 device. The PG2K400 device includes a dual-core Cortex-A53 processor unit, a 28nm programmable logic array, and abundant input / output (IO) peripherals. The processor is a PG2K400 ARM Cortex-A53, which communicates with the host's network interface card (NIC) and network interface via a network interface, and communicates with the RF transceiver CX9450 via an SPI interface.

[0048] Specifically, the Linux host can perform "software parameter configuration", which includes user setting parameters and software encapsulation into network packets, and then sending the network packets to the PG2K400 ARMCortex-A5 side through the network card NIC and network interface.

[0049] The PG2K400 ARM Cortex-A5 includes network interface card (NET) drivers, a Linux kernel, and RF transceiver drivers (CX9450 drivers). NET drivers manage resources and schedule tasks. The Linux kernel is the driver for network devices, acting as a bridge between the Linux kernel and Ethernet hardware, enabling the operating system to control network devices. The CX9450 drivers parse configuration commands from the Linux host (such as setting the filter bandwidth to 100MHz) and convert them into first configuration data in register binary. The CX9450 drivers then transmit this first configuration data to the RF transceiver.

[0050] Please see Figure 5 The diagram shows a schematic of another wireless transceiver provided in an embodiment of this application. The radio frequency transceiver module 120 includes a transmitting submodule 121 and a receiving submodule 122. The input terminal of the transmitting submodule 121 is connected to the second low-voltage differential signal interface, and the output terminal of the receiving submodule 122 is connected to the second low-voltage differential signal interface.

[0051] Understandably, superheterodyne structures have long dominated traditional RF architectures. (See also: [link to relevant documentation]). Figure 6 This paper illustrates an existing superheterodyne RF architecture that achieves signal frequency conversion through multi-stage mixing. First, the received RF signal is mixed with the local oscillator signal to a fixed intermediate frequency (IF). Then, after IF filtering and amplification, it is mixed again to the baseband for digital processing. The advantage of this structure is that the IF filter can effectively suppress image interference. However, it requires multiple independent local oscillators, mixers, and filters, resulting in high hardware complexity and redundant circuit board area. Furthermore, the phase noise accumulation caused by multi-stage frequency conversion degrades receiver sensitivity, and the fixed bandwidth of the IF filter limits the system's compatibility with multi-band signals.

[0052] The application utilizes a zero-IF architecture to directly down-convert RF signals to baseband via a single-stage mixer, eliminating the traditional intermediate frequency (IF) processing step. Its core advantages are: 1) Hardware simplification: Eliminating components such as IF filters and secondary mixers significantly reduces the number of analog devices; 2) Spectral flexibility: Bandwidth can be dynamically adjusted via digital filters, supporting seamless switching between multiple signal standards; 3) Enhanced integration: Modern zero-IF transceivers, such as the CX9450, integrate RF transceiver and baseband signal processing functions. Their operating frequency range is 30MHz to 6GHz, with a tunable bandwidth of 52kHz to 100MHz. Employing a direct conversion architecture, they consist of attenuators, mixers, programmable gain amplifiers, bandwidth-adjustable filters, and a high-speed, high-precision 16-bit analog-to-digital converter (ADC). Secondary conversion can be performed in the digital section, significantly reducing reliance on external components and eliminating the need for complex IF calibration procedures. Although early zero-IF technology had drawbacks such as DC offset and I / Q imbalance, the current CX9450 device features local oscillator leakage calibration and I / Q quadrature calibration, enabling better local oscillator leakage and image suppression.

[0053] In one alternative embodiment, please refer to Figure 7 The diagram shows a schematic of a receiving submodule 122 provided in an embodiment of this application. The receiving submodule 122 includes a first antenna 1221, a low-noise amplifier 1222, a first mixer 1223, a second mixer 1224, a first low-pass filter 1225, a second low-pass filter 1226, a first analog-to-digital converter 1227, a second analog-to-digital converter 1228, a phase-locked loop 1229, and a phase divider 1230.

[0054] The output terminal of the phase-locked loop 1229 is connected to the input terminal of the phase divider 1230 for outputting a first clock signal. The first output terminal of the phase divider 1230 is connected to the first input terminal of the first mixer 1223 for outputting a first clock signal. The second output terminal of the phase divider 1230 is connected to the first input terminal of the second mixer 1224 for outputting a second clock signal. The phase difference between the second clock signal and the first clock signal is a non-zero preset value.

[0055] The first antenna 1221 is connected to the input terminal of the low-noise amplifier 1222. The output terminal of the low-noise amplifier 1222 is connected to the second input terminal of the first mixer 1223 and the second input terminal of the second mixer 1224, respectively. The output terminal of the first mixer 1223 is connected to the input terminal of the first low-pass filter 1225. The output terminal of the first low-pass filter 1225 is connected to the input terminal of the first analog-to-digital converter 1227. The output terminal of the first analog-to-digital converter 1227 is connected to the second low-voltage differential signal interface.

[0056] The output of the second mixer 1224 is connected to the input of the second low-pass filter 1226, the output of the second low-pass filter 1226 is connected to the input of the second analog-to-digital converter 1228, and the output of the second analog-to-digital converter 1228 is connected to the second low-voltage differential signal interface.

[0057] It should be noted that a phase-locked loop (PLL) is used to generate a local oscillation signal. The PLL generates an oscillation signal through an internal voltage-controlled oscillator (VCO) and uses a feedback mechanism to ensure that the frequency and phase of the signal are consistent with the reference signal, thereby providing a stable and adjustable local oscillator signal. PLL is a known technology and will not be described in detail here.

[0058] In one example, the preset value is 90 degrees. The phase divider is used to divide the local oscillator signal into two signals with a phase difference of 90 degrees, which are used to generate two signals, I (In-phase) and Q (Quadrature), to achieve quadrature demodulation of the signal. The first clock signal is the I signal and the second clock signal is the Q signal.

[0059] In addition, the first antenna is used to receive radio frequency (RF) signals, and the low-noise amplifier is used to amplify the weak RF signals while minimizing noise introduction to ensure signal quality. The mixer multiplies the RF signal with either the first or second clock signal to perform frequency conversion, down-converting the RF signal to baseband for subsequent processing. The low-pass filter filters out high-frequency noise and unwanted signal components, allowing only low-frequency signals to pass through, protecting the subsequent ADC from high-frequency interference. The analog-to-digital converter (ADC) converts the analog signal into a digital signal.

[0060] The main process of the radio frequency transceiver module 120 receiving data is as follows: the first antenna 1221 receives the radio frequency signal and transmits it to the low noise amplifier 1222. The low noise amplifier 1222 amplifies and filters the received radio frequency signal to obtain the initial radio frequency signal, thereby improving the quality of the radio frequency signal. The low noise amplifier 1222 then transmits the initial radio frequency signal to the first mixer 1223 and the second mixer 1224 respectively.

[0061] The first mixer 1223 multiplies the initial radio frequency signal with the first clock signal to obtain a first signal and transmits it to the first low-pass filter 1225. The first low-pass filter 1225 filters the received first signal to obtain a second signal and transmits it to the first analog-to-digital converter 1227. The first analog-to-digital converter 1227 converts the second signal into a third signal of digital signal type (I-channel baseband signal). The first analog-to-digital converter 1227 is used to transmit the third signal to the second low-voltage differential signal interface.

[0062] The second mixer 1224 multiplies the initial radio frequency signal with the second clock signal to obtain a fourth signal and transmits it to the second low-pass filter 1226. The second low-pass filter 1226 filters the received second signal to obtain a fifth signal and transmits it to the second analog-to-digital converter 1228. The second analog-to-digital converter 1228 converts the fifth signal into a sixth signal (Q-channel baseband signal) of digital signal type. The second analog-to-digital converter 1228 is used to transmit the sixth signal to the second low-voltage differential signal interface.

[0063] It should be noted that during the data reception process, the output of the first analog-to-digital converter 1227 is connected to the second low-voltage differential signal interface of the radio frequency transceiver module 120, and the output of the second analog-to-digital converter 1228 is connected to the second low-voltage differential signal interface of the radio frequency transceiver module 120. That is, the second low-voltage differential signal interface of the radio frequency transceiver module 120 can transmit multiple baseband signals in parallel.

[0064] In one alternative embodiment, please refer to Figure 8 The illustration shows a schematic diagram of a transmitting submodule 121 provided in an embodiment of this application. The transmitting submodule 121 includes a second antenna 1211, a signal combiner 1212, a power amplifier 1213, a third low-pass filter 1214, a fourth low-pass filter 1215, a third mixer 1216, a fourth mixer 1217, a first digital-to-analog converter 1218, and a second digital-to-analog converter 1219.

[0065] The first output terminal of the phase divider 1230 is connected to the first input terminal of the third mixer 1216, and the second output terminal of the phase divider 1230 is connected to the first input terminal of the fourth mixer 1217.

[0066] The second low-voltage differential signal interface is connected to the input terminal of the first digital-to-analog converter 1218 and is used to output a first baseband signal. The second low-voltage differential signal interface is connected to the input terminal of the second digital-to-analog converter 1219 and is used to output a second baseband signal. The first baseband data includes the first baseband signal and the second baseband signal.

[0067] The output of the first digital-to-analog converter 1218 is connected to the input of the third low-pass filter 1214. The output of the third low-pass filter 1214 is connected to the second input of the third mixer 1216. The output of the third mixer 1216 is connected to the first input of the signal combiner 1212, for outputting a first radio frequency signal.

[0068] The output of the second digital-to-analog converter 1219 is connected to the input of the fourth low-pass filter 1215. The output of the fourth low-pass filter 1215 is connected to the second input of the fourth mixer 1217. The output of the fourth mixer 1217 is connected to the second input of the signal combiner 1212 for outputting a second radio frequency signal. The output of the signal combiner 1212 is connected to the input of the power amplifier 1213 for outputting a combined radio frequency signal. The output of the power amplifier 1213 is connected to the second antenna 1211.

[0069] It should be noted that the digital-to-analog converter is used to convert digital baseband signals into analog signals (radio frequency signals), the second antenna is used to transmit radio frequency data, the power amplifier is used to amplify the power of the radio frequency signal to make it sufficient to drive the antenna to transmit, the signal combiner is used to combine the first radio frequency signal and the second radio frequency signal into the radio frequency signal to be transmitted, and the second antenna is used to transmit the radio frequency signal.

[0070] The main process of the RF transceiver module sending data is as follows: The first digital-to-analog converter 1218 receives the first baseband signal (I-channel baseband signal) output by the field programmable gate array and converts it into a third RF signal. The first digital-to-analog converter 1218 transmits the third RF signal to the third low-pass filter 1214. The third RF signal is filtered by the third low-pass filter 1214. Then, the filtered third RF signal is transmitted to the third mixer 1216. The third mixer 1216 multiplies the filtered third RF signal with the first clock signal to obtain the first RF signal and transmits it to the signal combiner 1212.

[0071] The second digital-to-analog converter 1219 receives the first baseband signal (Q-channel baseband signal) output by the field-programmable gate array and converts it into a fourth radio frequency (RF) signal. The second RF converter 1219 transmits the fourth RF signal to the fourth low-pass filter 1215, which filters the fourth RF signal. The filtered fourth RF signal is then transmitted to the fourth mixer 1217, which multiplies the filtered fourth RF signal with the second clock signal to obtain the second RF signal and transmits it to the signal combiner 1212.

[0072] The signal combiner 1212 combines the first radio frequency signal and the second radio frequency signal to obtain the fifth radio frequency signal, and transmits the fifth radio frequency signal to the power amplifier 1213. After the power amplifier 1213 amplifies the fifth radio frequency signal, it is transmitted to the second antenna 1211. The second antenna 1211 is used to transmit the amplified fifth radio frequency signal.

[0073] It should be noted that during data transmission, the second low-voltage differential signal interface of the RF transceiver module can transmit multiple baseband signals in parallel. The first antenna and the second antenna can be the same antenna or different antennas. The transmitting submodules can share a single second low-voltage differential signal interface or use different second low-voltage differential signal interfaces, which will not be elaborated further here.

[0074] This application uses a zero-IF RF transceiver to replace the traditional superheterodyne architecture, which simplifies the design of the IF filter, eliminates additional mixers and filter components, reduces the number of components, further reduces the complexity and cost of the system, and improves the reliability and stability of the system.

[0075] In one optional embodiment, the wireless transceiver further includes a clock module, which is connected to both the processing module and the radio frequency transceiver module, and is used to provide a synchronization clock signal to both the processing module and the radio frequency transceiver module.

[0076] In one optional embodiment, the wireless transceiver further includes a power module, which is connected to the processing module and the radio frequency transceiver module respectively, and is used to provide power to the processing module and the radio frequency transceiver module.

[0077] In one alternative embodiment, the wireless transceiver further includes: a temperature sensor, a heat sink, and a thermal management module; The temperature sensor and the heat sink are respectively connected to the thermal management module. The temperature sensor is disposed in the processing module and the radio frequency transceiver module to collect the temperature of the processing module and the radio frequency transceiver module. The heat sink is disposed in the processing module and the radio frequency transceiver module to reduce the temperature of the processing module and the radio frequency transceiver module.

[0078] Throughout the process, the clock module provides all necessary clock signals, the power module ensures stable system operation, and the thermal management module monitors system temperature in real time and controls heat dissipation. The system adopts a modular design, facilitating maintenance and upgrades.

[0079] The clock module provides various clock signals required by the system, including the local oscillator signal for RF signal processing and the system clock for baseband signal processing, including the PP1S synchronization signal and the 10MHz synchronization clock. This module replaces imported chips with domestically produced ones, achieving complete domestic production of clock signals.

[0080] The thermal management module monitors the internal temperature of the device through a 12-bit resolution ADC and temperature sensor integrated on the PG2K400 chip. It can also monitor voltage and current on the board via the 16 external input channels provided by the on-chip ADC, and dissipates heat through a heatsink and fan, ensuring the SoC FPGA and RF transceiver operate within their normal operating temperature range. This further improves system integration and facilitates overall system miniaturization. The system adopts a modular architecture for easy maintenance and upgrades. Modules communicate via standard interfaces, enabling flexible configuration and scalability of system functions. It uses the Linux operating system and supports multiple communication protocol stacks, including mainstream protocols such as 4G / 5G.

[0081] In one alternative embodiment, please refer to Figure 9 The diagram shows a schematic of the structure of a wireless base station 200 provided in this application embodiment, including: a host 130, a baseband unit 210, and the aforementioned wireless transceiver 100.

[0082] The peripheral component interconnection expansion interface of the wireless transceiver 100 is connected to the host. The peripheral component interconnection expansion interface is used to transmit second baseband data between the host and the wireless transceiver 100. The task corresponding to the second baseband data is a non-real-time task.

[0083] The wireless transceiver 100 is connected to the baseband unit 210 and is used to transmit third baseband data between the wireless transceiver 100 and the baseband unit 210. The task corresponding to the third baseband data includes a real-time task. The first baseband data and the third baseband data have a third preset conversion relationship. The baseband unit 210 is used to perform digital signal processing on the third baseband data.

[0084] As an example, the tasks corresponding to the third baseband data include real-time tasks and non-real-time tasks.

[0085] In one implementation scenario where a wireless base station receives wireless data, the radio frequency transceiver module of the wireless transceiver 100 converts the received radio frequency data into first baseband data and transmits the first baseband data to a field-programmable gate array (FPGA). The FPGA determines whether the task corresponding to the first baseband data is a real-time task. If it is not a real-time task, it can obtain second baseband data based on a second preset conversion relationship and transmit the second baseband data to the host. If the task corresponding to the first baseband data is a real-time task, it obtains third baseband data based on a third preset conversion relationship and transmits the third baseband data to the baseband unit.

[0086] In one optional embodiment, the second preset conversion relationship is the same as the third preset conversion relationship.

[0087] It should be noted that traditional wireless base stations consist of a Remote Radio Head (RRH) and a Baseband Unit (BBU) located at the actual deployment site. The RRH processes incoming and outgoing radio signals, while the BBU facilitates digital signal processing for uplink and downlink data traffic. Data transmission between the RRH and BBU is conducted via optical fiber. The BBU in traditional architectures uses dedicated hardware, making secondary development or functional modifications difficult. Furthermore, subsequent upgrades require replacing the entire hardware platform, resulting in high operating costs and heavy reliance on hardware services provided by equipment manufacturers.

[0088] This solution can offload some non-real-time processing tasks of the BBU baseband unit to a Linux host or server running protocol stack processing software. The Linux host or server then completes baseband data transmission with the SoCFPGA through the PCIe Gen3x8 interface. This approach makes subsequent secondary development and function changes easier, and there is no need to replace expensive proprietary hardware during the upgrade process.

[0089] By optimizing the system architecture and hardware design, the overall size, weight, power consumption, and cost of the system have been reduced, while ensuring high performance and stability, which aligns with the future development trend of miniaturization and high integration of communication equipment.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A wireless transceiver, characterized in that, include: The interconnected processing module and radio frequency transceiver module, wherein the processing module includes an integrated processor and a field-programmable gate array; The field-programmable gate array includes a first low-voltage differential signal interface, the processor includes a first serial peripheral interface, and the radio frequency transceiver module includes a second low-voltage differential signal interface and a second serial peripheral interface. The first low-voltage differential signal interface is connected to the second low-voltage differential signal interface, and the first low-voltage differential signal interface and the second low-voltage differential signal interface are used to transmit the first baseband data between the field programmable gate array and the radio frequency transceiver module; The first serial peripheral interface is connected to the second serial peripheral interface, and the first serial peripheral interface and the second serial peripheral interface are used to transmit the first configuration data of the radio frequency transceiver module between the processor and the radio frequency transceiver module.

2. The wireless transceiver according to claim 1, characterized in that, The processor includes a network interface for connecting to a host, and the network interface is used to transmit second configuration data of the radio frequency transceiver module between the host and the processor. The first configuration data and the second configuration data have a first preset conversion relationship. The field-programmable gate array includes a peripheral component interconnect (PCI) interface for connecting to a host computer. The PCI interface is used to transmit second baseband data between the host computer and the field-programmable gate array. The first baseband data and the second baseband data have a second preset conversion relationship.

3. The wireless transceiver according to claim 2, characterized in that, The peripheral component interconnection and expansion interface is a PCIe Gen3x8 interface.

4. The wireless transceiver according to claim 1, characterized in that, The radio frequency transceiver module includes a transmitting submodule and a receiving submodule. The input terminal of the transmitting submodule is connected to the second low-voltage differential signal interface, and the output terminal of the receiving submodule is connected to the second low-voltage differential signal interface.

5. The wireless transceiver according to claim 4, characterized in that, The receiving submodule includes a first antenna, a low-noise amplifier, a first mixer, a second mixer, a first low-pass filter, a second low-pass filter, a first analog-to-digital converter, a second analog-to-digital converter, a phase-locked loop, and a phase divider. The output terminal of the phase-locked loop is connected to the input terminal of the phase divider for outputting a first clock signal. The first output terminal of the phase divider is connected to the first input terminal of the first mixer for outputting a first clock signal. The second output terminal of the phase divider is connected to the first input terminal of the second mixer for outputting a second clock signal. The phase difference between the second clock signal and the first clock signal is a non-zero preset value. The first antenna is connected to the input terminal of the low-noise amplifier, the output terminal of the low-noise amplifier is connected to the second input terminal of the first mixer and the second input terminal of the second mixer, the output terminal of the first mixer is connected to the input terminal of the first low-pass filter, the output terminal of the first low-pass filter is connected to the input terminal of the first analog-to-digital converter, and the output terminal of the first analog-to-digital converter is connected to the second low-voltage differential signal interface. The output of the second mixer is connected to the input of the second low-pass filter, the output of the second low-pass filter is connected to the input of the second analog-to-digital converter, and the output of the second analog-to-digital converter is connected to the second low-voltage differential signal interface.

6. The wireless transceiver according to claim 5, characterized in that, The transmitting submodule includes a second antenna, a signal combiner, a power amplifier, a third low-pass filter, a fourth low-pass filter, a third mixer, a fourth mixer, a first digital-to-analog converter, and a second digital-to-analog converter. The first output terminal of the phase divider is connected to the first input terminal of the third mixer, and the second output terminal of the phase divider is connected to the first input terminal of the fourth mixer. The second low-voltage differential signal interface is connected to the input terminal of the first digital-to-analog converter and is used to output a first baseband signal. The second low-voltage differential signal interface is connected to the input terminal of the second digital-to-analog converter and is used to output a second baseband signal. The first baseband data includes the first baseband signal and the second baseband signal. The output of the first digital-to-analog converter is connected to the input of the third low-pass filter, the output of the third low-pass filter is connected to the second input of the third mixer, and the output of the third mixer is connected to the first input of the signal combiner, for outputting a first radio frequency signal; The output of the second digital-to-analog converter is connected to the input of the fourth low-pass filter. The output of the fourth low-pass filter is connected to the second input of the fourth mixer. The output of the fourth mixer is connected to the second input of the signal combiner for outputting a second radio frequency signal. The output of the signal combiner is connected to the input of the power amplifier for outputting the combined radio frequency signal. The output of the power amplifier is connected to the second antenna.

7. The wireless transceiver according to claim 1, characterized in that, Also includes: A clock module is connected to both the processing module and the radio frequency transceiver module, and is used to provide a synchronous clock signal for both the processing module and the radio frequency transceiver module.

8. The wireless transceiver according to claim 1, characterized in that, Also includes: A power supply module is connected to both the processing module and the radio frequency transceiver module, and is used to provide power to both the processing module and the radio frequency transceiver module.

9. The wireless transceiver according to claim 1, characterized in that, Also includes: Temperature sensor, heat sink, and thermal management module; The temperature sensor and the heat sink are respectively connected to the thermal management module. The temperature sensor is disposed in the processing module and the radio frequency transceiver module to collect the temperature of the processing module and the radio frequency transceiver module. The heat sink is disposed in the processing module and the radio frequency transceiver module to reduce the temperature of the processing module and the radio frequency transceiver module.

10. A wireless base station, characterized in that, include: The host, the baseband unit, and the wireless transceiver as described in any one of claims 1-9; The peripheral component interconnection expansion interface of the wireless transceiver is connected to the host. The peripheral component interconnection expansion interface is used to transmit second baseband data between the host and the wireless transceiver. The task corresponding to the second baseband data is a non-real-time task. The wireless transceiver is connected to the baseband unit and is used to transmit third baseband data between the wireless transceiver and the baseband unit. The task corresponding to the third baseband data includes a real-time task. The first baseband data and the third baseband data have a third preset conversion relationship. The baseband unit is used to perform digital signal processing on the third baseband data.

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