LED dimming circuit

Abstract

The utility model discloses a kind of LED dimming circuit, including color correction storage module, color correction storage module, for storing the data of different stage lamps and lanterns same color output in a curve for MCU controller module to call up;MC controller module, its data call end is electrically connected with color correction storage module, control signal output end is electrically connected with FPGA module, according to the data converted into control signal output to FPGA module from color correction storage module call up;FPGA module, its PWM output end is electrically connected with LED dimming drive module, clock signal input end is connected with crystal oscillator circuit, clock frequency signal generated by the reception of FPGA module crystal oscillator circuit, by the control signal received clock signal is divided into low frequency PWM and high frequency PWM output to LED dimming drive module;LED dimming drive module, its drive output end is electrically connected with the LED lamp of stage lamps and lanterns, according to the received low frequency PWM and high frequency PWM drive adjust the brightness of LED lamp.

Description

Technical Field

[0001] This utility model relates to the field of stage light dimming circuits, and in particular to an LED dimming circuit. Background Technology

[0002] In the ever-evolving stage lighting industry, the demands on stage lighting fixtures are constantly increasing. Stage lighting fixtures are required to achieve multi-color single-point control, typically involving the control of dozens or even hundreds of individual LEDs. This necessitates a system capable of providing numerous PWM signals to control the dimming circuits. Simultaneously, smoother dimming, higher dimming precision and frequency, good low-brightness consistency, and low noise are also required. This presents a significant challenge for stage lighting fixtures. However, traditional LED dimming circuits control stage lighting fixtures solely through an MCU. When different stage lighting fixtures receive the same MCU control signal, consistent luminous efficacy cannot be achieved, especially in the low-brightness range, resulting in poor visual effects. Utility Model Content

[0003] The purpose of this invention is to provide an LED dimming circuit that can make the light output of different stage lights consistent, so as to improve the visual effect of the stage lights.

[0004] The LED dimming circuit of this utility model includes an FPGA module, an MCU controller module, a color correction storage module, and an LED dimming driver module;

[0005] The color correction storage module is used to store data on the same color output of different stage lights on a curve for the MCU controller module to retrieve.

[0006] The MCU controller module has its data retrieval terminal electrically connected to the color correction storage module and its control signal output terminal electrically connected to the FPGA module. It converts the data retrieved from the color correction storage module into control signals and outputs them to the FPGA module.

[0007] The FPGA module has its PWM output terminal electrically connected to the LED dimming driver module, and its clock signal input terminal connected to a crystal oscillator circuit. The FPGA module receives the clock frequency signal generated by the crystal oscillator circuit and divides the clock signal into low-frequency PWM and high-frequency PWM by the received control signal and outputs them to the LED dimming driver module.

[0008] The LED dimming driver module has its driver output terminal electrically connected to the LED lights of the stage lighting fixture, and adjusts the brightness of the LED lights according to the received low-frequency PWM and high-frequency PWM drives.

[0009] As a preferred embodiment of this utility model, the MCU controller module includes an MCU controller chip, the color correction storage module includes a color correction storage chip, and the TXD4 and RXD4 pins of the data retrieval terminal of the MCU controller chip are electrically connected to the TXD4 and RXD4 pins of the color correction storage chip.

[0010] As a preferred embodiment of this utility model, the FPGA module includes an FPGA first module and an FPGA second module. The TX and RX pins of the FPGA first module are electrically connected to the TXD3 and RXD3 pins of the control signal output terminal of the MCU controller chip.

[0011] As a preferred embodiment of this utility model, the TX pin of the first FPGA module is electrically connected to the TXD3 pin of the MCU controller chip through a first resistor, and the RX pin of the first FPGA module is electrically connected to the RXD3 pin of the MCU controller chip through a second resistor.

[0012] As a preferred embodiment of this utility model, the LED dimming driver module includes a driver chip, a first field-effect transistor (FET), and a second FET. The PWM input pin of the driver chip is electrically connected to the IO1 pin of the PWM output terminal of the first module of the FPGA. The HSG pin of the driver chip is electrically connected to the gate of the first FET. The LX pin of the driver chip is electrically connected to the source of the first FET. The SHUNT pin of the driver chip is electrically connected to the gate of the second FET. The drain of the first FET is electrically connected to the positive terminal of the VDD power supply. The drain of the second FET is electrically connected to the source of the first FET via a first inductor. The source of the second FET is grounded. The positive terminal of the LED lamp of the stage lighting fixture is electrically connected to the drain of the second FET, and the negative terminal is electrically connected to the source of the second FET.

[0013] As a preferred embodiment of this utility model, the PWM input pin of the driver chip is provided with a pull-down resistor and a filter capacitor. One end of the pull-down resistor is electrically connected to the PWM input pin of the driver chip, and the other end is grounded. One end of the filter capacitor is electrically connected to the PWM input pin of the driver chip, and the other end is grounded.

[0014] As a preferred embodiment of this utility model, a sampling resistor for collecting current is provided between the source of the second field-effect transistor and ground. One end of the sampling resistor is grounded, and the other end is electrically connected to the ISNS pin of the driver chip through a three-phase resistor.

[0015] As a preferred embodiment of this utility model, the crystal oscillator circuit includes a crystal oscillator signal chip, and the output terminal F_CLK of the crystal oscillator signal chip is electrically connected to the clock signal input terminal F_CLK of the second module of the FPGA.

[0016] As a preferred embodiment of this utility model, the clock frequency signal generated by the crystal oscillator signal core is 100MHz.

[0017] The LED dimming circuit described in this invention stores data on the same color output curve from different stage lights in a color correction storage module. The crystal oscillator circuit transmits the generated clock frequency signal to the FPGA module. The MCU controller module retrieves the data from the color correction storage module, converts it into a control signal, and sends it to the FPGA module. The FPGA module then divides the clock signal into low-frequency PWM and high-frequency PWM signals and outputs them to the LED dimming driver module. The LED dimming driver module adjusts the brightness of the LED lights based on the received low-frequency and high-frequency PWM signals, thereby ensuring consistent light output from different stage lights and enhancing the visual effect of the stage lights. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the LED dimming circuit of this utility model;

[0019] Figure 2 , 3 This is the circuit diagram of the FPGA module;

[0020] Figure 4 This is the circuit diagram for a crystal oscillator circuit.

[0021] Figure 5 This is the circuit diagram of the MCU controller chip;

[0022] Figure 6 Circuit diagram for a color-corrected memory chip;

[0023] Figure 7 This is the circuit diagram for the LED dimming driver module. Detailed Implementation

[0024] The technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0025] This embodiment provides an LED dimming circuit, such as Figure 1As shown, the system includes an FPGA module, an MCU controller module, a color correction storage module, and an LED dimming driver module. The color correction storage module stores data on the same color output of different stage lights on a curve for MCU controller module retrieval. The MCU controller module's data retrieval terminal is electrically connected to the color correction storage module, and its control signal output terminal is electrically connected to the FPGA module. It converts the data retrieved from the color correction storage module into control signals and outputs them to the FPGA module. The FPGA module's PWM output terminal is electrically connected to the LED dimming driver module, and its clock signal input terminal is connected to a crystal oscillator circuit. The FPGA module receives the clock frequency signal generated by the crystal oscillator circuit and divides the clock signal into low-frequency PWM (pulse width modulation) and high-frequency PWM by the received control signal, outputting them to the LED dimming driver module. The LED dimming driver module's drive output terminal is electrically connected to the LED lights of the stage lights and adjusts the brightness of the LED lights according to the received low-frequency and high-frequency PWM signals.

[0026] like Figure 2 and Figure 3 As shown, the FPGA module includes FPGA module 1 U1A and FPGA module 2 U1C. The TX and RX pins of FPGA module 1 are electrically connected to the TXD3 and RXD3 pins of the control signal output terminal of the MCU controller chip. The model of the FPGA module is GW5A-LV25LQ144.

[0027] like Figure 4 As shown, the crystal oscillator circuit includes a crystal oscillator signal chip Y1, which generates a clock frequency signal of 100MHz. The output terminal F_CLK of the crystal oscillator signal chip is electrically connected to the clock signal input terminal F_CLK of the second module of the FPGA. The FPGA module can realize 18-bit resolution LED dimming through the 100MHz clock frequency signal. The FPGA module decomposes an 18-bit brightness value (e.g., D17-D0) into several bit planes: the high 6 bits (D17-D12) represent coarse adjustment, which changes slowly; the low 12 bits (D11-D0) represent fine adjustment, which changes rapidly. Therefore, the FPGA module divides the 100MHz clock signal into low-frequency PWM and high-frequency PWM based on the received control signal. The low-frequency PWM processes the high 6 bits, and the high-frequency PWM processes the low 12 bits. The high 6 bits of PWM can achieve 2^6 = 64 levels of change, so each change to the least significant value is a change of 1 / 64. The lower 12 bits of PWM can achieve 2*12 = 4096 levels of variation, so each change to the least significant value is a change of 1 / 4096. Since the final dimming output = low-frequency PWM + high-frequency PWM, the final dimming output frequency = system clock / high-frequency PWM (lower 12 bits of PWM) = 100MHz / 4096 = 24.4kHz.

[0028] In addition, a surface-mount ferrite bead L1 and a filter capacitor CB1 are installed between the output terminal F_CLK of the crystal oscillator chip Y1 and the clock signal input terminal F_CLK of the second FPGA module to protect the circuit. One end of the filter inductor L1 is electrically connected to the output terminal F_CLK of the crystal oscillator chip Y1, and the other end is electrically connected to the clock signal input terminal F_CLK of the second FPGA module. One end of the filter capacitor CB1 is electrically connected to the clock signal input terminal F_CLK of the second FPGA module, and the other end is grounded. A 220R surface-mount ferrite bead L2 and filter capacitors C31, C32, and C33 are also installed between the crystal oscillator chip Y1 and the 3.3V power input terminal to protect the circuit. One end of the surface-mount ferrite bead L2 is electrically connected to the 3.3V power supply, and the other end is electrically connected to the power input terminal of the crystal oscillator chip Y1. Filter capacitors C31, C32, and C33 are connected in parallel, with one end grounded and the other end connected to the power input terminal of the crystal oscillator chip Y1. This effectively eliminates the spike-like radiation in the high-frequency range, making it easier for stage lighting fixtures to pass EMI testing.

[0029] like Figure 5 and Figure 6 As shown, the MCU controller module includes an MCU controller chip U4, and the color correction storage module includes a color correction storage chip U6. The TXD4 and RXD4 pins of the data retrieval terminal of the MCU controller chip are electrically connected to the TXD4 and RXD4 pins of the color correction storage chip. The RXD3 pin of the MCU controller chip is electrically connected to the RX pin of the first FPGA module through a second resistor R34, and the TXD3 pin of the MCU controller chip is electrically connected to the TX pin of the first FPGA module through a first resistor R35. The MCU controller chip U4 retrieves data stored in the color correction storage chip showing the same color output of different stage lights on a curve through the TXD4 and RXD4 pins, and then transmits this data to the first FPGA module through the RXD3 and TXD3 pins via the second resistor R34 and the first resistor R35. The MCU controller chip U4 is model APM32F103RET6, and the color correction storage chip U6 is model MF6031.

[0030] like Figure 7As shown, the LED dimming driver module includes a driver chip U7, a first field-effect transistor Q1, and a second field-effect transistor Q2. The PWM input pin of the driver chip is electrically connected to the IO1 pin of the PWM output terminal of the first module of the FPGA. The HSG pin of the driver chip is electrically connected to the gate of the first field-effect transistor. The LX pin of the driver chip is electrically connected to the source of the first field-effect transistor. The SHUNT pin of the driver chip is electrically connected to the gate of the second field-effect transistor. The drain of the first field-effect transistor is electrically connected to the positive terminal of the VDD power supply. The drain of the second field-effect transistor is electrically connected to the source of the first field-effect transistor through a first inductor. The source of the second field-effect transistor is grounded. The positive terminal of the LED lamp of the stage lighting fixture is electrically connected to the drain of the second field-effect transistor, and the negative terminal is electrically connected to the source of the second field-effect transistor.

[0031] When driver chip U7 receives low-frequency and high-frequency PWM outputs from the IO1 pin of the PWM output terminal of the first module of the FPGA, it turns on the first MOSFET Q1 and the second MOSFET Q2. MOSFET Q1 controls the LED driver switching frequency, and MOSFET Q2 controls the LED driver dimming output. Driver chip U7 is model IW380, and MOSFETs Q1 and Q2 are TDM31056 surface-mount MOSFETs.

[0032] In addition, the PWM input pin of the driver chip is equipped with a pull-down resistor R45 and a filter capacitor C55. One end of the pull-down resistor is electrically connected to the PWM input pin of the driver chip, and the other end is grounded. One end of the filter capacitor is also electrically connected to the PWM input pin of the driver chip, and the other end is grounded. The pull-down resistor R45 and the filter capacitor C55 can filter interference from the circuit.

[0033] In addition, a sampling resistor RS is placed between the source of the second field-effect transistor and ground to collect the current. One end of the sampling resistor is grounded, and the other end is electrically connected to the ISNS pin of the driver chip via a three-phase resistor R44. The sampling resistor RS includes four sampling resistors RS1, RS2, RS3, and RS4 connected in parallel. By adjusting the resistance values ​​of these four sampling resistors, the maximum output current of the LED driver can be changed. For example, if the sampling resistors RS1, RS2, RS3, and RS4 are all 0R39 resistors, their resistance after parallel connection is 0R0975. Then, the maximum output current of the LED driver is I = 400mV / 0R975 = 4.102A. The source of the first field-effect transistor is also equipped with a surface-mount capacitor C52 and a surface-mount resistor R42. One end of the surface-mount capacitor C52 is grounded, and the other end is connected to one end of the surface-mount resistor R42. The other end of the surface-mount resistor R42 is connected to the source of the first field-effect transistor. The surface-mount capacitor C52 and the surface-mount resistor R42 play a filtering role, thereby reducing the radiation interference of the LED driver circuit.

[0034] The above embodiments are only used to illustrate the detailed solution of this utility model. This utility model is not limited to the above detailed solution, that is, it does not mean that this utility model must rely on the above detailed solution to be implemented. Those skilled in the art should understand that any improvement to this utility model, equivalent substitution of the raw materials of this utility model product, addition of auxiliary components, selection of specific methods, etc., all fall within the protection scope and disclosure scope of this utility model.

Claims

1. An LED dimming circuit, characterized in that, Includes an FPGA module, an MCU controller module, a color correction storage module, and an LED dimming driver module; The color correction storage module is used to store data on the same color output of different stage lights on a curve for the MCU controller module to retrieve. The MCU controller module has its data retrieval terminal electrically connected to the color correction storage module and its control signal output terminal electrically connected to the FPGA module. It converts the data retrieved from the color correction storage module into control signals and outputs them to the FPGA module. The FPGA module has its PWM output terminal electrically connected to the LED dimming driver module, and its clock signal input terminal connected to a crystal oscillator circuit. The FPGA module receives the clock frequency signal generated by the crystal oscillator circuit and divides the clock signal into low-frequency PWM and high-frequency PWM by the received control signal and outputs them to the LED dimming driver module. The LED dimming driver module has its driver output terminal electrically connected to the LED lights of the stage lighting fixture, and adjusts the brightness of the LED lights according to the received low-frequency PWM and high-frequency PWM drives.

2. The LED dimming circuit according to claim 1, characterized in that, The MCU controller module includes an MCU controller chip (U4), and the color correction storage module includes a color correction storage chip (U6). The TXD4 and RXD4 pins of the data retrieval terminal of the MCU controller chip are electrically connected to the TXD4 and RXD4 pins of the color correction storage chip.

3. The LED dimming circuit according to claim 2, characterized in that, The FPGA module includes FPGA module 1 (U1A) and FPGA module 2 (U1C). The TX and RX pins of FPGA module 1 are electrically connected to the TXD3 and RXD3 pins of the control signal output terminal of MCU controller chip.

4. The LED dimming circuit according to claim 3, characterized in that, The TX pin of the first FPGA module is electrically connected to the TXD3 pin of the MCU controller chip through the first resistor (R35), and the RX pin of the first FPGA module is electrically connected to the RXD3 pin of the MCU controller chip through the second resistor (R34).

5. The LED dimming circuit according to claim 3, characterized in that, The LED dimming driver module includes a driver chip (U7), a first field-effect transistor (Q1), and a second field-effect transistor (Q2). The PWM input pin of the driver chip is electrically connected to the IO1 pin of the PWM output terminal of the first module of the FPGA. The HSG pin of the driver chip is electrically connected to the gate of the first field-effect transistor. The LX pin of the driver chip is electrically connected to the source of the first field-effect transistor. The SHUNT pin of the driver chip is electrically connected to the gate of the second field-effect transistor. The drain of the first field-effect transistor is electrically connected to the positive terminal of the VDD power supply. The drain of the second field-effect transistor is electrically connected to the source of the first field-effect transistor through a first inductor. The source of the second field-effect transistor is grounded. The positive terminal of the LED lamp of the stage lighting fixture is electrically connected to the drain of the second field-effect transistor, and the negative terminal is electrically connected to the source of the second field-effect transistor.

6. The LED dimming circuit according to claim 5, characterized in that, The PWM input pin of the driver chip is equipped with a pull-down resistor (R45) and a filter capacitor (C55). One end of the pull-down resistor is electrically connected to the PWM input pin of the driver chip, and the other end is grounded. One end of the filter capacitor is electrically connected to the PWM input pin of the driver chip, and the other end is grounded.

7. The LED dimming circuit according to claim 5, characterized in that, A sampling resistor (RS) for collecting current is set between the source of the second field-effect transistor and ground. One end of the sampling resistor is grounded, and the other end is electrically connected to the ISNS pin of the driver chip through a three-phase resistor (R44).

8. The LED dimming circuit according to claim 3, characterized in that, The crystal oscillator circuit includes a crystal oscillator signal chip (Y1), and the output terminal F_CLK of the crystal oscillator signal chip is electrically connected to the clock signal input terminal F_CLK of the second module of the FPGA.

9. The LED dimming circuit according to claim 8, characterized in that, The clock frequency signal generated by the crystal oscillator is 100MHz.

Images