Substrate structure, package structure and electronic device

Abstract

The present disclosure relates to a substrate structure, a packaging structure and an electronic device, the substrate structure comprising a body, a plurality of pairs of differential pair vias are arranged on the body, each differential pair via comprises a first via and a second via; in two adjacent pairs of differential pair vias, the center of the via of one pair of differential pair vias and the center of the first via of another pair of differential pair vias closest to the position of the via have a first distance, and the center of the via of one pair of differential pair vias and the center of the second via of another pair of differential pair vias closest to the position of the via have a second distance, the first distance is equal to the second distance. Through the above technical solution, the substrate structure provided by the present disclosure can reduce the crosstalk between the differential pair vias, improve the transmission quality and integrity of the differential signal.

Description

Technical Field

[0001] This disclosure relates to the field of circuit board packaging technology, specifically to a substrate structure, packaging structure, and electronic device. Background Technology

[0002] In related technologies, in order to balance performance and space utilization in high-density interconnect design, multiple vias are usually set on the circuit board to achieve complex high-density interconnects between different structural layers. However, due to the dense arrangement of multiple vias on the circuit board, this design has a serious problem of crosstalk between vias, which affects the transmission quality and integrity of electronic device signals. Utility Model Content

[0003] The purpose of this disclosure is to provide a substrate structure, packaging structure, and electronic device that can reduce crosstalk between differential pair vias and improve the transmission quality and integrity of differential signals.

[0004] To achieve the above objectives, a first aspect of this disclosure provides a substrate structure comprising: a body having a plurality of pairs of differential vias, each of the differential vias including a first via and a second via; in two adjacent pairs of differential vias, the center of one pair of differential vias is at a first distance from the center of the first via of the other pair of differential vias closest to the location of the via, and the center of the via of the other pair of differential vias is at a second distance from the center of the second via of the other pair of differential vias closest to the location of the via, wherein the first distance is equal to the second distance. This arrangement is intended to reduce crosstalk between differential vias and improve the transmission quality and integrity of differential signals.

[0005] In some possible implementations, the multiple pairs of differential vias are spaced apart in a first direction. The multiple pairs of differential vias are arranged such that the two middle vias in each of four adjacent vias in the same row come from the same pair of differential vias, and each of three adjacent vias in two adjacent rows includes two vias from the same pair of differential vias and one via from another pair of differential vias. The center line connecting any three adjacent vias forms a triangle. This arrangement facilitates on-site fabrication and reduces crosstalk between the two closest differential vias when transmitting differential signals, thereby improving the transmission quality and integrity of differential signals.

[0006] In some possible implementations, the multiple pairs of differential vias include multiple pairs of differential signal pair vias and at least one pair of differential clock pair vias. The multiple pairs of differential vias are arranged such that the at least one pair of differential clock pair vias is located outside the multiple pairs of differential signal pair vias, and / or such that the at least one pair of differential clock pair vias is located inside the multiple pairs of differential signal pair vias. This arrangement can ensure that the differential clock pairs have high quality, high integrity, and compact layout.

[0007] In some possible implementations, the signal transmission distance between the first via of the differential pair and the chip is configured to be equal to the signal transmission distance between the second via of the same differential pair and the chip. This arrangement facilitates the wiring design, saves the overall structural size of the substrate, and reduces crosstalk between the two closest differential pairs of vias, for example, when transmitting differential signals.

[0008] In some possible implementations, the inner diameter of the first via in a pair of differential vias is the same as the inner diameter of the second via. This arrangement facilitates on-site fabrication, saves on the overall size of the substrate structure, and reduces crosstalk between the two closest differential vias, for example, when transmitting differential signals.

[0009] In some possible implementations, the body is further provided with a plurality of first grounding vias, and the plurality of first grounding vias are arranged in a circle around the outer periphery of the plurality of differential pair vias; and / or, the body is further provided with a plurality of signal vias, the signal vias being connected to the vias of the differential pair vias. This arrangement can reduce crosstalk between differential pair vias and achieve the purpose of high-density signal interconnection.

[0010] In some possible implementations, the first distance is 0.6mm-0.8mm; and / or, there is a third distance of 0.47mm-0.65mm between the center of the first via and the center of the second via in a pair of differential vias. This arrangement can reduce crosstalk between the two closest differential vias when transmitting differential signals, while ensuring that the overall structural size of the substrate structure is saved, thereby improving the transmission quality and integrity of differential signals.

[0011] A second aspect of this disclosure provides a packaging structure including a first circuit board, the first circuit board including the substrate structure provided in the first aspect.

[0012] In some possible implementations, the package structure further includes an interposer layer through which the substrate structure is connected to the chip or a second circuit board; wherein, the interposer layer is provided with multiple pairs of differential pair pins, each of the differential pair pins including a third via and a fourth via, in two adjacent pairs of differential pair pins, there is a fourth distance between the center of the via of one pair of differential pair pins and the center of the third via of the other pair of differential pair pins closest to the location of the via, and there is a fifth distance between the center of the via of the one pair of differential pair pins and the center of the fourth via of the other pair of differential pair pins closest to the location of the via, the fourth distance being equal to the fifth distance. This arrangement can reduce crosstalk between differential pair pins and improve the transmission quality and integrity of differential signals.

[0013] In some possible implementations, the multiple pairs of differential pins are spaced apart in a first direction. The multiple pairs of differential pins are arranged such that the two middle pins of each of four adjacent pins in the same row come from the same pair of differential pins, and each of three adjacent pins in two adjacent rows includes two pins from the same pair of differential pins and one pin from another pair of differential pins. The center line connecting any three adjacent pins forms a triangle. This arrangement facilitates on-site fabrication and reduces crosstalk between the two closest differential pins, for example, when transmitting differential signals, thereby improving the transmission quality and integrity of the differential signal.

[0014] In some possible implementations, the multiple differential pair pins include multiple differential signal pair pins and at least one differential clock pair pin. The multiple differential pair pins are arranged such that the at least one differential clock pair pin is located outside the multiple differential signal pair pins, and / or such that the at least one differential clock pair pin is located inside the multiple differential signal pair pins. This arrangement can ensure that the differential clock pairs have high quality, high integrity, and compact layout.

[0015] In some possible implementations, the inner diameter of the third via in a pair of differential pins is the same as the inner diameter of the fourth via. This arrangement facilitates on-site fabrication, saves on the overall size of the interposer layer, and reduces crosstalk between the two closest differential pins, for example, when transmitting differential signals.

[0016] In some possible implementations, the interposer layer is further provided with a plurality of second ground vias, and the plurality of second ground vias are arranged in a circle around the outer periphery of the plurality of differential pair pins. This arrangement can reduce crosstalk between differential pair pins and improve the transmission quality and integrity of differential signals.

[0017] In some possible implementations, the fourth distance is 0.55mm-0.6mm; and / or, there is a sixth distance of 0.55mm-0.6mm between the center of the third via and the center of the fourth via in a pair of differential pins. This arrangement can reduce crosstalk between the two closest differential pins when transmitting differential signals, while ensuring that the overall structure size of the interposer is saved, thereby improving the transmission quality and integrity of the differential signal.

[0018] A third aspect of this disclosure provides an electronic device that includes the substrate structure provided in the first aspect, or the packaging structure provided in the second aspect.

[0019] Through the above technical solution, namely the substrate structure provided in this disclosure, the substrate structure constructs multiple pairs of differential vias on the body as including first vias and second vias. In two adjacent pairs of differential vias, the center of one pair of differential vias has a first distance from the center of the first via of the other pair of differential vias closest to the first via, and the center of the aforementioned pair of differential vias has a second distance from the center of the aforementioned pair of differential vias closest to the second via of the other pair of differential vias. The first distance is constructed to be equal to the second distance. By arranging the two pairs of differential vias closest to each other in terms of their positions, the vias (e.g., the first or second via) of one pair of differential vias are at the same distance from the first and second vias of the other pair of differential vias, and the crosstalk can be canceled. This achieves the goal of reducing crosstalk between the two closest differential vias when transmitting differential signals, for example, and helps to improve the transmission quality and integrity of differential signals.

[0020] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0021] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the differential pair via arrangement of the substrate structure provided in the first embodiment of this disclosure; Figure 2 This is a schematic diagram of the differential pair pin arrangement of the interposer layer provided in the first embodiment of this disclosure; Figure 3 This is a schematic diagram of the differential pair via arrangement of the substrate structure provided in the second embodiment of this disclosure; Figure 4 This is a schematic diagram of the differential pair pin arrangement of the intermediary layer provided in the second embodiment of this disclosure; Figure 5 This is a schematic diagram of the differential pair via arrangement of the substrate structure provided in the third embodiment of this disclosure; Figure 6 This is a schematic diagram of the differential pair pin arrangement of the interposer layer provided in the third embodiment of this disclosure; Figure 7 This is a schematic diagram of the differential pair via routing method of the substrate structure provided in the first embodiment of this disclosure; Figure 8 This is a schematic diagram of the differential pair via routing method of the substrate structure provided in the second embodiment of this disclosure; Figure 9 This is the first simulation diagram provided by this disclosure based on the first embodiment; Figure 10 This is the second simulation diagram provided by the first embodiment of the present disclosure; Figure 11 This is the third simulation diagram provided by the first embodiment of the present disclosure; Figure 12 This is the fourth simulation diagram provided by the first embodiment of the present disclosure; Figure 13 This is the first simulation diagram provided by the second embodiment of the present disclosure; Figure 14 This is the second simulation diagram provided by the second embodiment of the present disclosure; Figure 15 This is the third simulation diagram provided by the second embodiment of the present disclosure; Figure 16 This is the fourth simulation diagram provided by the second embodiment of the present disclosure; Figure 17 This is the first simulation diagram provided by this disclosure based on the third embodiment; Figure 18 This is the second simulation diagram provided by the third embodiment of the present disclosure; Figure 19 This is the third simulation diagram provided by the third embodiment of the present disclosure; Figure 20 This is the fourth simulation diagram provided by the third embodiment of the present disclosure; Figure 21 This is a schematic diagram of the packaging structure provided in an exemplary embodiment of this disclosure; Figure 22 This is a simulation diagram based on the design where the via (e.g., the first or second via) of one of the two closest differential via pairs is equidistant from the first and second vias of the other differential via pair. Figure 23 This is a schematic diagram based on the design where the via (e.g., the first via or the second via) of one of the two closest differential via pairs is not at the same distance from the first and second vias of the other differential via pair. Figure 24 This is a simulation diagram based on the design where the vias (e.g., the first or second via) of one of the two closest differential via pairs are not at the same distance from the first and second vias of the other differential via pair. Figure 25 This is a simulation comparison diagram based on two cases where the distance between the via (e.g., the first or second via) of one of the two closest differential via pairs and the first and second vias of the other differential via pair are the same and different.

[0022] Explanation of reference numerals in the attached figures 100 - Substrate structure; 110 - Body; 120 - Differential pair via; 121 - First via; 122 - Second via; 123 - Differential signal pair via; 124 - Differential clock pair via; 130 - First ground via; 140 - Signal via; 150 - Third ground via; 160 - Connecting lead; 200 - Intermediate layer; 210 - Differential pair pin; 211 - Third via; 212 - Fourth via; 213 - Differential signal pair pin; 214 - Differential clock pair pin; 220 - Second ground via; 300 - Chip; 400 - Second circuit board. Detailed Implementation

[0023] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0024] In this disclosure, unless otherwise stated, directional terms such as "upper," "lower," "left," and "right" generally refer to upper and lower within the space of the encapsulated structure when it is in use. "Inner" and "outer" refer to inner and outer relative to the outline of the component or structure itself. Furthermore, it should be noted that terms such as "first" and "second" are used to distinguish one element from another and do not indicate sequence or importance. Additionally, in the description with reference to the accompanying drawings, the same reference numerals in different drawings denote the same elements.

[0025] According to a first aspect of this disclosure, a substrate structure 100 is provided, with reference to... Figures 1 to 21As shown, the substrate structure 100 includes a body 110, on which multiple pairs of differential vias 120 are provided. Each differential via 120 includes a first via 121 and a second via 122. In two adjacent pairs of differential vias 120, the center of the via of one pair of differential vias 120 has a first distance from the center of the first via 121 of the other pair of differential vias 120 that is closest to the via. The center of the via of one pair of differential vias 120 has a second distance from the center of the second via 122 of the other pair of differential vias 120 that is closest to the via. The first distance is equal to the second distance.

[0026] Through the above technical solution, namely the substrate structure 100 provided in this disclosure, the substrate structure 100 constructs multiple pairs of differential vias 120 on the body 110, each including a first via 121 and a second via 122. Furthermore, in two adjacent pairs of differential vias 120, the center of one pair of differential vias 120 has a first distance from the center of the first via 121 of the other pair of differential vias 120 closest to that via. The centers of the second vias 122 are spaced apart by a second distance, wherein the first distance is configured to be equal to the second distance. By arranging the vias (e.g., the first via 121 or the second via 122) of one of the two closest differential via pairs 120 are spaced at the same distance as the first via 121 and the second via 122 of the other differential via pair 120, the crosstalk can be canceled. This achieves the goal of reducing crosstalk between the two closest differential via pairs 120 when transmitting differential signals, for example, and helps to improve the transmission quality and integrity of differential signals.

[0027] It should be noted that, for ease of explanation, in this disclosure, vias ending in, for example, "P" in the differential pair via 120 can be understood as the first via 121, and vias ending in, for example, "M" can be understood as the second via 122. Based on this, refer to... Figure 1As shown, taking the vias (DL0P), (DL2P), and (DL2M) in differential pair via 120 as examples, since the first distance a between the centers of the vias (DL0P and DL2P) is constructed to be equal to the second distance b between the centers of the vias (DL0P and DL2M), the vias (DL2P and DL2M) can be symmetrically arranged about the perpendicular line d passing through the center of the aforementioned via (DL0P). Thus, when signals of equal amplitude and opposite phase are injected into the vias (DL2P and DL2M), the noise coupled from the vias (DL2P and DL2M) to the vias (DL0P) is also approximately equal in amplitude and opposite in phase, and the two paths... The sum of the noise signals is approximately zero. Similarly, the noise from the vias (DL3P) and (DL3M) coupled to the via (DL0M) is also approximately equal in amplitude and opposite in phase. The sum of the two noise signals is approximately zero. In this way, while ensuring area saving and cable routing, the vias (e.g., the first via 121 or the second via 122) of one of the two closest differential via pairs 120 are equidistant from the first via 121 and the second via 122 of the other differential via pair 120. The crosstalk can be canceled out, which reduces the crosstalk between the two closest differential via pairs 120 when transmitting differential signals, thus helping to improve the transmission quality and integrity of differential signals.

[0028] Additionally, refer to Figure 22 As shown, this disclosure is based on the design concept that the vias (e.g., the first via 121 or the second via 122) of one of the two closest pairs of differential vias 120 are equidistant from the first via 121 and the second via 122 of the other pair of differential vias 120. The simulation results are as follows. Figure 22 As shown in Figures (1) and (2), when, for example, 9 GHz sine waves of equal amplitude and opposite phase are injected into vias (DL2P) and (DL2M) respectively, from... Figure 22 As can be seen, vnoise_p and vnoise_m are the noises coupled from the via (DL2P) and via (DL2M) to the via (DL0P), respectively, with amplitudes close to 300mV. v_crosstalk = vnoise_p + vnoise_m, with a peak voltage of 13mV.

[0029] In, for example Figure 23When the vias (e.g., the first via 121 or the second via 122) of one of the two closest pairs of differential vias 120 shown are at different distances from the first via 121 and the second via 122 of the other pair of differential vias 120, that is, for example, when the vias (DL2P) and (DL2M) are not arranged symmetrically about the perpendicular line passing through the center of the aforementioned via (DL0P), and referring to Figure 24 As shown, this disclosure is based on the design concept that the vias (e.g., the first via 121 or the second via 122) of one of the two closest differential via pairs 120 are at different distances from the first via 121 and the second via 122 of the other differential via pair 120. The simulation results are as follows. Figure 24 As shown in Figures (1) and (2), when, for example, 9 GHz sine waves of equal amplitude and opposite phase are injected into vias (DL2P) and (DL2M) respectively, from... Figure 24 As can be seen, vnoise_p and vnoise_m are the noises coupled from the via (DL2P) and via (DL2M) to the via (DL0P), respectively, with amplitudes close to 300mV. v_crosstalk = vnoise_p + vnoise_m, with a peak voltage of 29mV.

[0030] In addition, refer to Figure 25 As shown, this disclosure compares simulations under two scenarios: one where the vias (e.g., the first via 121 or the second via 122) of one of the two closest differential via pairs 120 are constructed with the same distance from the first via 121 and the second via 122 of the other differential via pair 120, and the simulation results are as follows. Figure 25 As shown, from Figure 25 As can be seen from the frequency domain simulation results of crosstalk, at, for example, 9 GHz, the crosstalk is greater when the distance between the vias (e.g., the first via 121 or the second via 122) of one of the two closest differential via pairs 120 is different from that of the first via 121 and the second via 122 of the other differential via pair 120, compared to when the distance between the vias (e.g., the first via 121 or the second via 122) of one of the two closest differential via pairs 120 is the same as that of the other differential via pair 120. That is, the crosstalk difference between the two is 9 dB.

[0031] Therefore, through the above simulation and comparative analysis, it can be seen that by configuring the vias (e.g., the first via 121 or the second via 122) of one of the two closest differential via pairs 120 to be at the same distance from the first via 121 and the second via 122 of the other differential via pair 120, crosstalk can be canceled. This can reduce crosstalk between the two closest differential via pairs 120 when transmitting differential signals, for example, and help improve the transmission quality and integrity of differential signals.

[0032] In some possible implementations, in two adjacent pairs of differential vias 120, the first distance between the center of one differential via 120 and the center of the first via 121 of the other differential via 120 closest to that via can be, but is not limited to, 0.6mm-0.8mm. That is, for example, the first distance a between the lines connecting the centers of vias (DL0P and DL2P) can be, but is not limited to, 0.6mm-0.8mm. Exemplarily, this first distance can be, for example, 0.6mm, 0.65mm, 0.75mm, or 0. The present disclosure is not limited to 0.8mm, etc. In this arrangement, while ensuring space saving and cable routing, the vias (e.g., the first via 121 or the second via 122) of one of the two closest differential via pairs 120 are positioned at the same distance from the first via 121 and the second via 122 of the other differential via pair 120. The principle that crosstalk can be canceled is achieved, which can reduce crosstalk between the two closest differential via pairs 120 when transmitting differential signals, for example, and help improve the transmission quality and integrity of differential signals.

[0033] It can be understood that the second distance between the center of the via of the aforementioned pair of differential vias 120 and the center of the second via 122 of the other pair of differential vias 120 closest to the via position can be adaptively designed according to actual application requirements. That is, for example, the second distance of the line b connecting the center of the via (DL0P) and the center of the via (DL2M) can be adaptively designed according to actual application requirements, as long as it is designed to be the same as the first distance. This disclosure will not elaborate further here.

[0034] Additionally, in some possible implementations, refer to Figure 1As shown, there may be a third distance between the center of the first via 121 and the center of the second via 122 in a pair of differential vias 120. The third distance may be, but is not limited to, 0.47mm-0.65mm. That is, for example, the third distance of the line c connecting the center of the via (DL2P) and the center of the via (DL2M) may be, but is not limited to, 0.47mm-0.65mm. For example, the third distance may be, for example, 0.47mm, 0.55mm, 0.58mm, 0.65mm, etc. This disclosure is not limited to this. Such an arrangement can facilitate the wiring design while ensuring that the overall structural size of the substrate structure 100 is saved.

[0035] Furthermore, in some possible implementations, reference is made to Figure 1 As shown, the inner diameter of the first via 121 in a pair of differential vias 120 can be the same as the inner diameter of the second via 122. This arrangement facilitates on-site fabrication, saves on the overall structural size of the substrate structure 100, and facilitates wiring design. It also helps reduce crosstalk between the two closest differential vias 120 when transmitting differential signals, thus improving the transmission quality and integrity of differential signals.

[0036] In this disclosure, the inner diameters of the first via 121 and the second via 122 in a pair of differential vias 120 are not specifically limited, and those skilled in the art can design them adaptively according to actual application requirements. Furthermore, the inner diameters of the first via 121 and the second via 122 in different pairs of differential vias 120 can also be the same to facilitate processing and fabrication.

[0037] Additionally, in some possible implementations, refer to Figure 7 and Figure 8 As shown, the signal transmission distance between the first via 121 of the differential pair via 120 and the chip 300 (described in detail below) is configured to be equal to the signal transmission distance between the second via 122 of the same differential pair via 120 and the chip 300. That is, it can be understood that the trace length between the first via 121 of the differential pair via 120 and the chip 300 can be configured to be equal to the trace length between the second via 122 of the same differential pair via 120 and the chip 300, so that the signal transmission distances of the two are the same, reducing crosstalk between the two closest differential pair vias 120, for example, when transmitting differential signals, which helps to improve the transmission quality and integrity of differential signals.

[0038] It should be noted that, Figure 7 and Figure 8The diagram only shows a portion of the wiring schematics, specifically, only the wiring design on substrate structure 100 (e.g., connecting lead 160). Furthermore, due to different usage requirements of substrate structure 100, the specific arrangement of the differential pair vias 120 will vary. The specific arrangement of the differential pair vias 120 is as follows: Figure 7 and Figure 8 As shown, although the specific arrangement of the multiple pairs of differential vias 120 on the two substrate structures 100 is different, it is understandable that in both specific embodiments, it is necessary to satisfy the above-mentioned requirement that the signal transmission distance between the first via 121 of the differential via 120 and the chip 300 be constructed to be equal to the signal transmission distance between the second via 122 of the same pair of differential vias 120 and the chip 300.

[0039] For example, such as Figure 7 As shown, based on Figure 7 The specific arrangement of the multiple pairs of differential vias 120 on the substrate structure 100 shown in the figure can maximize the benefits of the via arrangement in this embodiment. The vias can be wound around the same length starting from the exit point of the via to avoid asymmetry within the differential pair caused by winding around the same length later, which would increase crosstalk between differential pairs. This is to make the signal transmission distance between the first via 121 of the differential via 120 and the chip 300 equal to the signal transmission distance between the second via 122 of the same differential via 120 and the chip 300. This ensures that the signal transmission distances of the two are the same, reducing crosstalk between the two closest differential vias 120 when transmitting differential signals, for example, thereby improving the transmission quality and integrity of differential signals.

[0040] In addition, such as Figure 8 As shown, based on Figure 8 The specific arrangement of multiple pairs of differential vias 120 on the substrate structure 100 shown in the figure takes into account that the internal hole spacing of some differential vias 120 is small, which may cause problems such as difficulty in starting to wind equal length from the via. Therefore, in order to facilitate the routing operation, in this embodiment, equal length can be wound in the same layer within the differential pair first, so as to reduce, for example, the change in the routing environment after changing layers, increase the crosstalk between differential pairs, so that the signal transmission distance of the two pairs is the same, reduce the crosstalk between the two closest differential vias 120 when transmitting differential signals, and achieve the purpose of improving the transmission quality and integrity of differential signals.

[0041] It is understood that this disclosure is not limited to the two wiring designs mentioned above. The art can adapt the design according to the actual application requirements, and this disclosure will not elaborate further here.

[0042] In some possible implementations, refer to Figure 1 , Figure 3 as well as Figure 5 As shown, multiple pairs of differential vias 120 can be installed in the first direction (see reference). Figure 1 or Figure 3 or Figure 5 Multiple pairs of differential vias 120 are arranged at intervals on the left and right sides of the drawing, such that the two middle vias in each of four adjacent vias in the same row come from the same pair of differential vias 120, and each of three adjacent vias in two adjacent rows includes two vias from the same pair of differential vias 120 and one via from another pair of differential vias 120. The center line connecting any three adjacent vias forms a triangle. This arrangement facilitates on-site fabrication, saves on the overall structural size of the substrate structure 100, and facilitates wiring design. It also helps reduce crosstalk between the two closest differential vias 120 when transmitting differential signals, thus improving the transmission quality and integrity of differential signals.

[0043] It is understood that the specific design values ​​of the first distance, the second distance, and the third distance can make the center line connecting any three adjacent vias form, for example, an isosceles triangle or an equilateral triangle. That is, when the first distance, the second distance, and the third distance are all equal, the center line connecting any three adjacent vias can form, for example, an equilateral triangle. And when, for example, the first distance and the second distance are equal, the center line connecting any three adjacent vias can form, for example, an isosceles triangle. This disclosure does not make specific limitations in this regard, and the art can adapt the design according to actual application needs.

[0044] Additionally, it should be noted that in some embodiments not shown, the plurality of differential vias 120 spaced apart in the first direction can be understood as a group of differential vias 120, and along a second direction perpendicular to the first direction (see reference...). Figure 1 or Figure 3 or Figure 5 The diagram (up and down direction) can be constructed as multiple sets of the above-mentioned differential pair vias 120. This disclosure does not specifically limit this, and the art can adapt the design according to actual application needs.

[0045] Furthermore, in some possible implementations, reference is made to Figure 1 and Figure 3As shown, the multiple pairs of differential signal pair vias 120 may include multiple pairs of differential signal pair vias 123 and at least one pair of differential clock pair vias 124. The multiple pairs of differential signal pair vias 120 are arranged such that at least one pair of differential clock pair vias 124 is located outside the multiple pairs of differential signal pair vias 123. By arranging the at least one pair of differential clock pair vias 124 outside the multiple pairs of differential signal pair vias 123, the differential clock pairs can be guaranteed to have high clock quality, high integrity, and compact layout.

[0046] It should be noted that the specific embodiment described above, in which at least one pair of differential clock pair vias 124 are disposed outside multiple pairs of differential signal pair vias 123, is exemplary. For example, in some alternative embodiments, refer to... Figure 5 As shown, the multiple pairs of differential vias 120 can also be arranged such that at least one pair of differential clock pair vias 124 are located inside the multiple pairs of differential signal pair vias 123. This arrangement, by placing at least one pair of differential clock pair vias 124 inside the multiple pairs of differential signal pair vias 123, ensures high signal quality and compact layout for the differential clock pairs. This disclosure is not limited thereto; those skilled in the art can adapt the design according to actual application requirements.

[0047] It should be noted that vias beginning with, for example, DL or UL can be understood as the aforementioned differential signal pair vias 123, and vias beginning with, for example, CLK can be understood as the aforementioned differential clock pair vias 124. Furthermore, the specific number of differential clock pair vias 124 can be adaptively designed according to actual application requirements. This disclosure exemplifies the provision of a pair of differential clock pair vias 124, but is not limited to this.

[0048] In some possible implementations, refer to Figure 1 , Figure 3 as well as Figure 5 As shown, the main body 110 may also be provided with a plurality of first grounding vias 130, and the plurality of first grounding vias 130 are arranged in a circle around the outer periphery of the plurality of differential pair vias 120. This arrangement can reduce crosstalk between differential pair vias and improve the transmission quality and integrity of differential signals.

[0049] in, Figure 1 , Figure 3 as well as Figure 5 The large dotted circle shown can be understood as the first grounding via 130 mentioned above, and the first grounding via 130 can be prepared by any processing method in the art, for example, by processing with a mechanical drill bit to form a VSS mechanical via (first grounding via 130) on the substrate structure 100, but this disclosure is not limited thereto.

[0050] in addition, Figure 1 , Figure 3 as well as Figure 5 The dashed small circle shown can be understood as the third grounding via 150, and the third grounding via 150 can be prepared by any processing method in the art, for example, by forming a VSS laser via (third grounding via 150) on the substrate structure 100 by laser drilling, and this disclosure is not limited thereto.

[0051] It should be noted that the aforementioned VSS laser via (third grounding via 150) can be, for example, the corresponding second grounding via 220 on the interposer 200 (if any) (e.g. Figure 2 The VSS mechanical via shown above is connected to the chip 300. Alternatively, the VSS laser via (third ground via 150) can also be connected to the chip 300 (e.g., in the absence of the interposer 200) to enable efficient current collection through the VSS laser via (third ground via 150) and then transmission to the VSS mechanical via (first ground via 130) through the ground plane. The VSS mechanical via (first ground via 130) completes the current collection and transmission. Since the transmission method between the above ground vias can be adaptively designed based on the existing connection method, this disclosure will not elaborate further here.

[0052] In some possible implementations, refer to Figure 1 , Figure 3 as well as Figure 5 As shown, the body 110 may also be provided with a plurality of signal vias 140. The signal vias 140 can be used to connect with the vias of the differential pair vias 120, for example, by connecting leads 160. The signal vias 140 can also be connected to the corresponding differential pair pins 210 on, for example, the intermediate layer 200 (if any). Figure 2 The vias shown above (starting with DL, UL, CLK) are connected, or the signal vias 140 can also be connected to the chip 300 (e.g., in the case of no interposer 200) to achieve, for example, high-density signal interconnection, thereby improving signal transmission quality and integrity.

[0053] in addition, Figure 1 , Figure 3 as well as Figure 5 The solid-lined small circles shown can be understood as signal vias 140, and these signal vias 140 can be fabricated by any processing method within the art, for example, by forming signal laser vias (signal vias 140) on the substrate structure 100 using a laser drill. Furthermore, it should be noted that the multiple pairs of differential vias 120 described above can be fabricated, for example, by using a mechanical drill bit to form signal mechanical vias (differential vias 120, or...) on the substrate structure 100. Figure 1 , Figure 3 as well as Figure 5 (The solid-lined great circle shown in the figure) This disclosure is not limited thereto.

[0054] Furthermore, in some possible implementations, reference is made to Figure 1 , Figure 3 as well as Figure 5 As shown, along a second direction perpendicular to the first direction, the width of the body 110 can be greater than or equal to 2 mm. For example, the width of the body 110 of the substrate structure 100 can be, for example, 2 mm. Furthermore, along the second direction, the VSS mechanical vias (first ground via 130) and signal mechanical vias (differential pair vias 120) can be arranged such that, for example, four rows of vias are arranged on the body 110 of the substrate structure 100. This arrangement facilitates saving the overall structural size of the substrate structure 100 and simplifying wiring design. It also helps reduce crosstalk between the two closest differential pair vias 120 when transmitting differential signals, thus improving the transmission quality and integrity of the differential signals. This disclosure is not limited thereto.

[0055] According to a second aspect of this disclosure, a packaging structure is provided, the packaging structure including a first circuit board, the first circuit board including the substrate structure 100 provided in the first aspect above. Furthermore, this packaging structure also has all the beneficial effects of the substrate structure 100 provided in the first aspect above, and this disclosure is not limited thereto.

[0056] It should be noted that the aforementioned first circuit board (Cavity board) can be understood as any suitable printed circuit board (PCB) or radio frequency circuit board (RF PCB) in the art. This disclosure will not elaborate further here. The art can be adapted to the actual application requirements.

[0057] Additionally, in some possible implementations, refer to Figure 2 , Figure 4 , Figure 6 as well as Figure 21 As shown, the packaging structure may also include an interposer 200. The body 110 of the substrate structure 100 is connected to the chip 300 or the second circuit board 400 through the interposer 200. In this way, by setting the interposer 200, high-density electrical interconnection and signal interaction between, for example, the chip 300 and the substrate structure 100 can be realized, which helps to improve the transmission rate and reduce power consumption. Thus, when the packaging structure is applied to electronic devices such as mobile phones, high transmission efficiency and low power consumption can be guaranteed.

[0058] In this disclosure, no specific limitations are made on the specific structure of the chip 300 (e.g., it may include, but is not limited to, a SOC system-on-a-chip, an SDR chip, or an HDM memory chip), the second circuit board 400 (e.g., it may include, but is not limited to, a main control PCB circuit board), and the interposer 200 (e.g., it may include, but is not limited to, a silicon interposer). The art can adapt the design according to the actual application requirements.

[0059] Additionally, it should be noted that the body 110 of the aforementioned substrate structure 100 is connected to the chip 300 or the second circuit board 400 via the interposer 200. This can be understood as the substrate structure 100 being connected to the chip 300 via the interposer 200, or the substrate structure 100 being connected to the second circuit board 400 on which the chip 300 is disposed via the interposer 200. Both of these arrangements can achieve, for example, high-density electrical interconnection and signal interaction between the chip 300 and the substrate structure 100. Alternatively, the body 110 of the substrate structure 100 may not be connected to the chip 300 via the interposer 200. This disclosure does not specifically limit this, and those skilled in the art can adapt the design according to actual application requirements.

[0060] Furthermore, it is understood that in some embodiments not illustrated, the above-described packaging structure may also include multiple stacked second circuit boards 400, and high-density electrical interconnection and signal interaction between two adjacent second circuit boards 400 are achieved through the above-described substrate structure 100 and / or interposer 200. This disclosure will not elaborate further on this.

[0061] Among them, such as Figure 2 , Figure 4 , Figure 6 as well as Figure 21As shown, multiple pairs of differential pins 210 can be provided on the interposer layer 200. Each differential pin 210 includes a third via 211 and a fourth via 212. In two adjacent pairs of differential pins 210, there is a fourth distance between the center of the via of one pair of differential pins 210 and the center of the third via 211 of the other pair of differential pins 210 that is closest to the via. Furthermore, there is a fourth distance between the center of the via of one pair of differential pins 210 and the center of the fourth via 212 of the other pair of differential pins 210 that is closest to the via. With a fifth distance, and the fourth distance being equal to the fifth distance, this arrangement utilizes the principle that crosstalk can be canceled by placing the vias (e.g., the third via 211 or the fourth via 212) of one of the two closest differential pair pins 210 at the same distance from the third via 211 and the fourth via 212 of the other differential pair pins 210. This achieves the goal of reducing crosstalk between the two closest differential pair pins 210 when transmitting differential signals, thus helping to improve the transmission quality and integrity of differential signals.

[0062] It should be noted that, as Figure 2 , Figure 4 , Figure 6 The vias in the differential pair pin 210 shown can be understood as the third via 211 if they end with, for example, P, and as the fourth via 212 if they end with, for example, M. Based on this, refer to Figure 2As shown, taking the vias (DL0P), (DL2P), and (DL2M) in the differential pair pin 210 as examples, since the fourth distance e between the centers of the vias (DL0P) and (DL2P) is constructed to be equal to the fifth distance f between the centers of the vias (DL0P) and (DL2M), the vias (DL2P) and (DL2M) can be arranged symmetrically about the perpendicular line passing through the center of the aforementioned via (DL0P). Thus, when signals of equal amplitude and opposite phase are injected into the vias (DL2P) and (DL2M), the noise coupled from the vias (DL2P) and (DL2M) to the via (DL0P) is also approximately equal in amplitude and opposite in phase, and the two noise paths are... The summation of the acoustic signals is approximately zero. Similarly, the noise coupled from the via (DL3P) and via (DL3M) to the via (DL0M) is also approximately equal in amplitude and opposite in phase. The summation of the two noise signals is approximately zero. In this way, while ensuring area saving and the ability to output cables, the vias (e.g., the third via 211 or the fourth via 212) of one of the two closest differential pair pins 210 are equidistant from the third via 211 and the fourth via 212 of the other differential pair pins 210. The principle that crosstalk can be canceled is achieved, which reduces crosstalk between the two closest differential pair pins 210 when transmitting differential signals, thus helping to improve the transmission quality and integrity of differential signals.

[0063] The specific principle of crosstalk cancellation and the effectiveness in reducing crosstalk between the two closest differential pair pins 210 during differential signal transmission can be verified by referring to the simulation and comparative analysis described above (e.g. Figures 22 to 25 The simulation results shown are not elaborated here.

[0064] In some possible implementations, in two adjacent pairs of differential pair pins 210, the fourth distance between the center of the via of one pair of differential pair pins 210 and the center of the third via 211 of the other pair of differential pair pins 210 closest to that via can be, but is not limited to, 0.55mm-0.6mm. That is, for example, the fourth distance of the line e connecting the centers of vias (DL0P) and (DL2P) can be, but is not limited to, 0.55mm-0.6mm. Exemplarily, this fourth distance can be, for example, 0.55mm, 0.58mm, or 0.6mm. mm, etc., this disclosure is not limited to this. Such an arrangement can save area and allow for cable routing. It can also utilize the principle that crosstalk can be canceled by arranging the vias (e.g., the third via 211 or the fourth via 212) of one of the two closest differential pair pins 210 at the same distance from the third via 211 and the fourth via 212 of the other differential pair pin 210. This achieves the goal of reducing crosstalk between the two closest differential pair pins 210 when transmitting differential signals, and helps to improve the transmission quality and integrity of differential signals.

[0065] It can be understood that the fifth distance between the center of the via of the aforementioned pair of differential pair pins 210 and the center of the fourth via 212 of the aforementioned other pair of differential pair pins 210 that is closest to the via position can be adaptively designed according to actual application requirements. That is, for example, the fifth distance of the line f connecting the center of the via (DL0P) and the center of the via (DL2M) can be adaptively designed according to actual application requirements, as long as it can be designed to be the same as the fourth distance. This disclosure will not elaborate further here.

[0066] Additionally, in some possible implementations, refer to Figure 2 As shown, there may be a sixth distance between the center of the third via 211 and the center of the fourth via 212 in a pair of differential pins 210. The sixth distance may be, but is not limited to, for example, 0.55mm-0.6mm. That is, for example, the sixth distance of the line g connecting the center of the via (DL2P) and the center of the via (DL2M) may be, but is not limited to, 0.55mm-0.6mm. For example, the sixth distance may be, for example, 0.55mm, 0.58mm, 0.6mm, etc. This disclosure is not limited to this. Such an arrangement can facilitate the wiring design while ensuring that the overall structural size of the interposer layer 200 is saved.

[0067] Furthermore, in some possible implementations, reference is made to Figure 2As shown, the inner diameter of the third via 211 located in a pair of differential pins 210 can be the same as the inner diameter of the fourth via 212. For example, the inner diameter of the third via 211 can be, but is not limited to, 0.35mm-0.4mm, such as 0.35mm, 0.37mm, 0.4mm, etc. This disclosure is not limited to this. Such arrangement facilitates on-site processing and fabrication, saves the overall structural size of the interposer layer 200 and facilitates wiring design, and helps reduce crosstalk between the two closest differential pins 210 when transmitting differential signals, thereby improving the transmission quality and integrity of differential signals.

[0068] It should be noted that the inner diameters of the third via 211 and the fourth via 212 in different differential pair pins 210 can also be the same to facilitate processing and fabrication.

[0069] In some possible implementations, refer to Figure 2 , Figure 4 as well as Figure 6 As shown, multiple differential pair pins 210 can be configured in the first direction (see reference). Figure 2 or Figure 4 or Figure 6 The differential pair pins 210 are arranged at intervals on the left and right sides of the drawing, such that the two middle pins of each pair of four adjacent pins in the same row come from the same pair of differential pair pins 210, and each pair of three adjacent pins in two adjacent rows includes two pins from the same pair of differential pair pins 210 and one pin from another pair of differential pair pins 210. The center line connecting any three adjacent pins forms a triangle. This arrangement facilitates on-site fabrication, saves on the overall structural size of the interposer layer 200, and facilitates wiring design. It also helps reduce crosstalk between the two closest differential pair pins 210 when transmitting differential signals, thus improving the transmission quality and integrity of differential signals.

[0070] It is understood that the specific design values ​​of the fourth, fifth, and sixth distances can make the center line connecting any three adjacent pins (vias) form, for example, an isosceles triangle or an equilateral triangle. That is, when the fourth, fifth, and sixth distances are all equal, the center line connecting any three adjacent pins (vias) can form, for example, an equilateral triangle. And when, for example, the fourth and fifth distances are equal, the center line connecting any three adjacent pins (vias) can form, for example, an isosceles triangle. This disclosure does not make specific limitations in this regard, and the art can adapt the design according to actual application requirements.

[0071] Additionally, it should be noted that in some embodiments not shown, the multiple pairs of differential pins 210 spaced apart in the first direction can be understood as a group of differential pins 210, and along a second direction perpendicular to the first direction (see reference...). Figure 2 or Figure 4 or Figure 6 The diagram (vertical direction) can be constructed as multiple sets of the aforementioned differential pair pins 210. Furthermore, to facilitate routing design, the multiple differential pair pins 210 on the interposer layer 200 can be arranged such that, when the interposer layer 200 and the substrate structure 100 are stacked, the multiple differential pair pins 210 are positioned in the positive direction (directly above or directly below) of the corresponding multiple differential pair vias 120, or as close as possible to both, to shorten, for example, wiring distances and facilitate on-site fabrication. This disclosure does not specifically limit this; those skilled in the art can adapt the design according to actual application requirements.

[0072] It is understood that the design of the aforementioned multiple differential pair pins 210 being located in the positive direction (directly above or directly below) or as close as possible to the corresponding multiple differential pair vias 120 can be understood to minimize the signal transmission distance between, for example, differential pair pins 210 and differential pair vias 120 with the same label, so as to achieve high-density interconnection between differential pair pins 210 and differential pair vias 120 with the same label.

[0073] Furthermore, in some possible implementations, reference is made to Figure 2 and Figure 4 As shown, the multiple differential pair pins 210 may include multiple differential signal pair pins 213 and at least one differential clock pair pin 214. The multiple differential pair pins 210 are arranged such that at least one differential clock pair pin 214 is located outside the multiple differential signal pair pins 213. By placing at least one differential clock pair pin 214 outside the multiple differential signal pair pins 213, the differential clock pair can be guaranteed to have high clock quality, high integrity and compact layout.

[0074] It should be noted that the specific embodiment described above, which places at least one pair of differential clock pair pins 214 outside of multiple pairs of differential signal pair pins 213, is exemplary. For example, in some alternative embodiments, refer to... Figure 6 As shown, the multiple pairs of differential pins 210 can also be arranged such that at least one pair of differential clock pair pins 214 is located inside the multiple pairs of differential signal pair pins 213. This arrangement, by placing at least one pair of differential clock pair pins 214 inside the multiple pairs of differential signal pair pins 213, ensures high signal quality and compact layout for the differential clock pairs. This disclosure is not limited thereto; those skilled in the art can adapt the design according to actual application requirements.

[0075] It should be noted that pins (vias) starting with, for example, DL or UL can be understood as the differential signal pair pins 213 mentioned above, and pins (vias) starting with, for example, CLK can be understood as the differential clock pair pins 214 mentioned above. Furthermore, the specific number of differential clock pair pins 214 can be adaptively designed according to actual application requirements. This disclosure exemplifies the use of a pair of differential clock pair pins 214, but is not limited to this.

[0076] In some possible implementations, refer to Figure 2 , Figure 4 as well as Figure 6 As shown, the intermediate layer 200 may also be provided with a plurality of second ground vias 220, and the plurality of second ground vias 220 are arranged in a circle around the outer periphery of the plurality of differential pair pins 210. This arrangement can reduce crosstalk between differential pair pins and improve the transmission quality and integrity of differential signals.

[0077] The second grounding via 220 can be prepared by any processing method in the art, for example, by using a mechanical drill bit to form a VSS mechanical via (second grounding via 220) on the interposer layer 200, but this disclosure is not limited thereto.

[0078] Additionally, it should be noted that the multiple differential pair pins 210 described above in this disclosure can be fabricated, for example, using a mechanical drill bit to form signal mechanical apertures (e.g., pins starting with DL, UL, CLK) on the interposer layer 200, but this disclosure is not limited thereto.

[0079] Furthermore, in some possible implementations, reference is made to Figure 2 , Figure 4 as well as Figure 6 As shown, along a second direction perpendicular to the first direction, the width of the interposer 200 is greater than or equal to 2 mm. For example, the width of the interposer 200 can be 2 mm. Furthermore, along the second direction, the VSS mechanical vias (second ground via 220) and signal mechanical vias (e.g., pins starting with DL, UL, or CLK) can be arranged such that, for example, four rows of vias are arranged on the interposer 200. This arrangement facilitates saving the overall structural size of the interposer 200 and simplifying wiring design. It also helps reduce crosstalk between the two closest differential pair pins 210 when transmitting differential signals, thus improving the transmission quality and integrity of the differential signals. This disclosure is not limited thereto.

[0080] Based on the above specific embodiments, the first embodiment of this disclosure provides an arrangement of differential pair vias 120 on a substrate structure 100 and a arrangement of differential pair pins 210 on an interposer layer 200. Specifically, refer to... Figure 1and Figure 2 As shown, where, as Figure 1 As shown, on the substrate structure 100, the differential pair vias 120 are configured such that the distance between the center of via (DL0M) and the center of via (DL3M) and via (DL3P) is 0.65mm; the distance between the center of via (DL0P) and the center of via (DL2P) and via (DL2M) is 0.65mm; the distance between the center of via (DL1P) and the center of via (DL2P) and via (DL2M) is 0.75mm; the distance between the center of via (DL1M) and the center of via (UL0M) and via (UL0P) is 0.75mm; the distance between the center of via (UL1P) and the center of via (UL0M) and via (UL0P) is 0.65mm; and the distance between the center of via (UL1M) and the center of via (CLKP) is 0.65mm. The distance between the center of the via (DL0M) and the center of the via (DL1P) is 0.65mm, the distance between the center of the via (DL1P) and the center of the via (DL1M) is 0.55mm, the distance between the center of the via (UL1P) and the center of the via (UL1M) is 0.55mm, the distance between the center of the via (DL3P) and the center of the via (DL3M) is 0.65mm, the distance between the center of the via (DL2P) and the center of the via (DL2M) is 0.65mm, the distance between the center of the via (UL0P) and the center of the via (UL0M) is 0.65mm, and the distance between the center of the via (CLKP) and the center of the via (CLKM) is 0.65mm.

[0081] In addition, such as Figure 2 As shown, multiple differential pair pins 210 on the interposer layer 200 are configured such that the inner diameter of the vias (third via 211 and fourth via 212) of the differential pair pins 210 is, for example, 0.35 mm, and the aforementioned fourth distance, fifth distance and sixth distance are, for example, 0.6 mm.

[0082] In addition, refer to Figures 9 to 12 As shown, this disclosure simulates the arrangement of differential pair vias 120 on a substrate structure 100 and the arrangement of differential pair pins 210 on an interposer layer 200 based on the first embodiment described above. The simulation results are as follows. Figures 9 to 12 As shown, from Figure 9 It can be seen that the NEXT BB Lane-to-Lane Crosstalk is less than -40dB, which meets the crosstalk requirements (spec). Figure 10 It can be seen that the NEXT RF lane-to-lane crosstalk is less than -40dB, which meets the crosstalk requirements (spec). Figure 11It can be seen that the NEXT BB CLK To DLCrosstalk values ​​are all less than -45dB, meeting the crosstalk requirements (spec). Figure 12 It can be seen that the NEXT RF CLK ToDL Crosstalk is less than -45dB, which meets the crosstalk requirements (spec). In summary, the arrangement of differential pair vias 120 on the substrate structure 100 and the arrangement of differential pair pins 210 on the interposer layer 200 provided in the first embodiment of this disclosure can reduce crosstalk between differential pair vias and improve the transmission quality and integrity of differential signals.

[0083] Based on the above specific embodiments, the second embodiment of this disclosure provides an arrangement of differential pair vias 120 on a substrate structure 100 and a arrangement of differential pair pins 210 on an interposer layer 200. Specifically, refer to... Figure 3 and Figure 4 As shown, where, as Figure 3 As shown, on the substrate structure 100, the differential pair vias 120 are configured such that the distance between the center of via (DL0M) and the center of via (DL3M) and via (DL3P) is 0.6mm; the distance between the center of via (DL0P) and the center of via (DL2P) and via (DL2M) is 0.6mm; the distance between the center of via (DL1P) and the center of via (DL2P) and via (DL2M) is 0.75mm; the distance between the center of via (DL1M) and the center of via (UL0M) and via (UL0P) is 0.75mm; the distance between the center of via (UL1P) and the center of via (UL0M) and via (UL0P) is 0.6mm; and the distance between the center of via (UL1M) and the center of via (CLKP) is... The distance between the center of the via (CLKM) and the center of the via (DL0M) is 0.6mm; the distance between the center of the via (DL0M) and the center of the via (DL0P) is 0.58mm; the distance between the center of the via (DL1P) and the center of the via (DL1M) is 0.58mm; the distance between the center of the via (UL1P) and the center of the via (UL1M) is 0.58mm; the distance between the center of the via (DL3P) and the center of the via (DL3M) is 0.65mm; the distance between the center of the via (DL2P) and the center of the via (DL2M) is 0.65mm; the distance between the center of the via (UL0P) and the center of the via (UL0M) is 0.65mm; and the distance between the center of the via (CLKP) and the center of the via (CLKM) is 0.65mm.

[0084] In addition, such as Figure 4As shown, on the interposer layer 200, multiple differential pair pins 210 are configured such that the inner diameter of the vias (third via 211 and fourth via 212) of the differential pair pins 210 is, for example, 0.35 mm, and the aforementioned fourth distance, fifth distance and sixth distance are, for example, 0.55 mm.

[0085] In addition, refer to Figures 13 to 16 As shown, this disclosure simulates the arrangement of differential pair vias 120 on a substrate structure 100 and the arrangement of differential pair pins 210 on an interposer layer 200 based on the second embodiment described above. The simulation results are as follows. Figures 13 to 16 As shown, from Figure 13 It can be seen that the NEXT BB Lane-to-Lane Crosstalk is less than -40dB, which meets the crosstalk requirements (spec). Figure 14 It can be seen that the NEXT RF Lane-to-Lane Crosstalk is less than -40dB, which meets the crosstalk requirements (spec). Figure 15 It can be seen that NEXT, BB, CLK, ToDL, and Crosstalk are all less than -45dB, meeting the crosstalk requirements (spec). Figure 16 It can be seen that NEXT RF CLKTo DL Crosstalk is less than -45dB, which meets the crosstalk requirements (spec). In summary, the arrangement of differential pair vias 120 on the substrate structure 100 and the arrangement of differential pair pins 210 on the interposer layer 200 provided in the second embodiment of this disclosure can reduce crosstalk between differential pair vias and improve the transmission quality and integrity of differential signals.

[0086] Based on the above specific embodiments, the third embodiment of this disclosure provides an arrangement of differential pair vias 120 on a substrate structure 100 and a arrangement of differential pair pins 210 on an interposer layer 200. Specifically, refer to... Figure 5 and Figure 6 As shown, where, as Figure 5As shown, on the substrate structure 100, the differential pair vias 120 are configured such that the distance between the center of via (DL0P) and the center of via (DL2M) is 0.65mm, the distance between the center of via (DL0M) and the center of via (CLKM) and via (CLKP) is 0.65mm, the distance between the center of via (DL3P) and the center of via (CLKM) and via (CLKP) is 0.8mm, the distance between the center of via (DL3M) and the center of via (DL1P) and via (DL1M) is 0.6mm, the distance between the center of via (UL0M) and the center of via (DL1P) and via (DL1M) is 0.6mm, and the distance between the center of via (UL0P) and the center of via (UL1P) is 0.6mm. The distance between the center of the via (UL1M) and the center of the via (DL0P) is 0.6mm, the distance between the center of the via (DL0P) and the center of the via (DL0M) is 0.47mm, the distance between the center of the via (DL3P) and the center of the via (DL3M) is 0.47mm, the distance between the center of the via (UL0M) and the center of the via (UL0P) is 0.47mm, the distance between the center of the via (DL2P) and the center of the via (DL2M) is 0.55mm, the distance between the center of the via (CLKP) and the center of the via (CLKM) is 0.55mm, the distance between the center of the via (DL1P) and the center of the via (DL1M) is 0.55mm, and the distance between the center of the via (UL1P) and the center of the via (UL1M) is 0.55mm.

[0087] In addition, such as Figure 6 As shown, on the interposer layer 200, multiple differential pair pins 210 are configured such that the inner diameter of the vias (third via 211 and fourth via 212) of the differential pair pins 210 is, for example, 0.35 mm, and the aforementioned fourth distance, fifth distance and sixth distance are, for example, 0.55 mm.

[0088] In addition, refer to Figures 17 to 20 As shown, this disclosure simulates the arrangement of differential pair vias 120 on a substrate structure 100 and the arrangement of differential pair pins 210 on an interposer layer 200 based on the third embodiment described above. The simulation results are as follows. Figures 17 to 20 As shown, from Figure 17 It can be seen that the NEXT BB Lane-to-Lane Crosstalk is less than -40dB, which meets the crosstalk requirements (spec). Figure 18 It can be seen that the NEXT RF Lane-to-Lane Crosstalk is less than -40dB, which meets the crosstalk requirements (spec). Figure 19It can be seen that NEXT, BB, CLK, ToDL, and Crosstalk are all less than -45dB, meeting the crosstalk requirements (spec). Figure 20 It can be seen that the NEXT RF CLKTo DL Crosstalk is less than -45dB, which meets the crosstalk requirements (spec). In summary, the arrangement of differential pair vias 120 on the substrate structure 100 and the arrangement of differential pair pins 210 on the interposer layer 200 provided in the third embodiment of this disclosure can reduce crosstalk between differential pair vias and improve the transmission quality and integrity of differential signals.

[0089] It should be noted that the specific embodiments of the arrangement of differential pair vias 120 on the three substrate structures 100 and the arrangement of differential pair pins 210 on the interposer layer 200 provided above are all exemplary. This disclosure is not limited thereto. The art can also adapt the specific arrangement according to actual application requirements. For example, the specific arrangement positions of differential pair pins 210 and differential pair vias 120 with different labels can be adapted according to requirements, and differential pair pins 210 and differential pair vias 120 with the same label can also exchange positions with each other.

[0090] According to a third aspect of this disclosure, an electronic device is provided, which includes the substrate structure 100 provided in the first aspect, or the packaging structure provided in the second aspect. Furthermore, the electronic device also possesses all the beneficial effects of the substrate structure 100 provided in the first aspect or the packaging structure provided in the second aspect, and this disclosure is not limited thereto.

[0091] In some possible implementations, the aforementioned electronic device may include, but is not limited to, mobile phones, personal computers, servers, computing devices, and smart cars. This disclosure is not limited thereto.

[0092] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0093] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0094] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A substrate structure, characterized in that, include: The body is provided with multiple pairs of differential vias, each of the differential vias including a first via and a second via; In two adjacent pairs of differential vias, the center of one pair of differential vias has a first distance from the center of the first via of the other pair of differential vias closest to the position of the via, and the center of the one pair of differential vias has a second distance from the center of the second via of the other pair of differential vias closest to the position of the via, wherein the first distance is equal to the second distance.

2. The substrate structure according to claim 1, characterized in that, The multiple pairs of differential vias are spaced apart in a first direction. The multiple pairs of differential vias are arranged such that in each row of four adjacent vias, the two vias in the middle come from the same pair of differential vias, and in each row of three adjacent vias, there are two vias from the same pair of differential vias and one via from another pair of differential vias. The center line connecting any three adjacent vias forms a triangle.

3. The substrate structure according to claim 1, characterized in that, The plurality of differential pair vias includes a plurality of differential signal pair vias and at least one differential clock pair via. The plurality of differential pair vias are arranged such that the at least one differential clock pair via is located outside the plurality of differential signal pair vias, and / or such that the at least one differential clock pair via is located inside the plurality of differential signal pair vias.

4. The substrate structure according to claim 1, characterized in that, The signal transmission distance between the first via of the differential pair and the chip is configured to be equal to the signal transmission distance between the second via of the same differential pair and the chip.

5. The substrate structure according to claim 1, characterized in that, The inner diameter of the first via in the pair of differential vias is the same as the inner diameter of the second via.

6. The substrate structure according to claim 1, characterized in that, The body is also provided with a plurality of first grounding vias, and the plurality of first grounding vias are arranged in a circle around the outer periphery of the plurality of differential pair vias; and / or, The main body is also provided with multiple signal vias, which are connected to the vias of the differential pair vias.

7. The substrate structure according to any one of claims 1-6, characterized in that, The first distance is 0.6mm-0.8mm; and / or, There is a third distance between the center of the first via and the center of the second via in the pair of differential vias, the third distance being 0.47mm-0.65mm.

8. A packaging structure, characterized in that, It includes a first circuit board, which includes the substrate structure according to any one of claims 1-7.

9. The packaging structure according to claim 8, characterized in that, The packaging structure further includes an intermediary layer, through which the body of the substrate structure is connected to the chip or the second circuit board; The intermediate layer is provided with multiple pairs of differential pins, each of which includes a third via and a fourth via. In two adjacent pairs of differential pins, there is a fourth distance between the center of the via of one pair of differential pins and the center of the third via of the other pair of differential pins that is closest to the location of the via. There is also a fifth distance between the center of the via of the pair of differential pins and the center of the fourth via of the other pair of differential pins that is closest to the location of the via. The fourth distance is equal to the fifth distance.

10. The packaging structure according to claim 9, characterized in that, The multiple pairs of differential pins are spaced apart in a first direction. The multiple pairs of differential pins are arranged such that the two middle pins in each of four adjacent pins in the same row come from the same pair of differential pins, and each of three adjacent pins in two adjacent rows includes two pins from the same pair of differential pins and one pin from another pair of differential pins. The center line connecting any three adjacent pins forms a triangle.

11. The packaging structure according to claim 9, characterized in that, The plurality of differential pair pins includes a plurality of differential signal pair pins and at least one differential clock pair pin. The plurality of differential pair pins are arranged such that the at least one differential clock pair pin is located outside the plurality of differential signal pair pins, and / or such that the at least one differential clock pair pin is located inside the plurality of differential signal pair pins.

12. The packaging structure according to claim 9, characterized in that, The inner diameter of the third via in one of the differential pair pins is the same as the inner diameter of the fourth via.

13. The packaging structure according to claim 9, characterized in that, The intermediate layer is also provided with a plurality of second ground vias, and the plurality of second ground vias are arranged in a circle around the outer periphery of the plurality of differential pair pins.

14. The packaging structure according to any one of claims 9-13, characterized in that, The fourth distance is 0.55mm-0.6mm; and / or, There is a sixth distance of 0.55mm-0.6mm between the center of the third via and the center of the fourth via in a pair of differential pins.

15. An electronic device, characterized in that, It includes the substrate structure according to any one of claims 1-7, or the packaging structure according to any one of claims 8-14.

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