Multilayer high-speed board

Abstract

The disclosure provides a kind of multilayer high-speed plate, including sequentially stacked connection first solder stop layer, first outer circuit layer, first pp layer, first inner circuit layer, substrate layer, second inner circuit layer, second pp layer, second outer circuit layer and second solder stop layer;The substrate layer is a glass fiber reinforced material layer, so that the consistency of the substrate is good;First outer circuit layer is provided with first laser blind hole, and the first laser blind hole extends to the first inner circuit layer through the first outer circuit layer and the first pp layer;First inner circuit layer is provided with first inner circuit main body and first compensation etching part located on the both sides of first inner circuit main body;Second outer circuit layer is provided with second laser blind hole, and the second laser blind hole extends to the second inner circuit layer through the second outer circuit layer and the second pp layer;Second inner circuit layer is provided with second inner circuit main body and second compensation etching part located on the both sides of second inner circuit main body, effectively avoid the problem that the circuit width is small after inner layer circuit etching.

Description

Technical Field

[0001] This disclosure relates to the technical field of circuit boards, and in particular to a multilayer high-speed board. Background Technology

[0002] With the emergence of technologies such as PCIe 6.0 and 112GSerDes, signal edge speeds have been reduced to the picosecond level, meaning a significant increase in signal speed. Impedance mismatch, or impedance tolerance, can lead to reflections, jitter, and increased bit error rates. Impedance tolerance refers to the allowable deviation between the actual PCB transmission line impedance and the target value (such as 50Ω or 100Ω differential). It is usually ±10% as the industry benchmark, while high-speed designs of multilayer high-speed boards require ±5% or even stricter tolerances.

[0003] In high-density interconnect (HDI) board design, due to the complex structure of multilayer high-speed boards, their impedance tolerance is affected by many factors, mainly as follows: 1. Inconsistent substrate material. The substrate material of existing multilayer high-speed boards is FR4, which has a glass fiber weaving effect, resulting in large local fluctuations in the dielectric constant (Dk) at high frequencies; 2. The line width is too small after etching of the inner layer. Due to the difference in the etching sidewall angle between the line width and the spacing, the copper layer is over-etched after etching, especially for thicker lines, that is, the line width obtained after etching is smaller than the target line width. Utility Model Content

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a multilayer high-speed board with better substrate consistency and to avoid the problem of small line width after inner layer line etching.

[0005] The purpose of this disclosure is achieved through the following technical solution: A multilayer high-speed board includes a first solder mask layer, a first outer circuit layer, a first PP layer, a first inner circuit layer, a substrate layer, a second inner circuit layer, a second PP layer, a second outer circuit layer, and a second solder mask layer, which are sequentially stacked and connected. The substrate layer is a glass fiber reinforced material layer; The first outer circuit layer has a first laser blind hole, which extends through the first outer circuit layer and the first PP layer to the first inner circuit layer; the first inner circuit layer has a first inner circuit body and a first compensation etching portion located on both sides of the first inner circuit body. The second outer circuit layer has a second laser blind hole, which extends through the second outer circuit layer and the second PP layer to the second inner circuit layer; the second inner circuit layer has a second inner circuit body and a second compensation etching part located on both sides of the second inner circuit body.

[0006] In one embodiment, the width of the first compensation etched portion is 0.3mil to 0.5mil.

[0007] In one embodiment, the first internal circuit body and the first compensation etching part are integrally formed.

[0008] In one embodiment, the width of the second compensation etched portion is 0.3mil to 0.5mil.

[0009] In one embodiment, the second inner circuit body and the second compensation etching part are integrally formed.

[0010] In one embodiment, the tolerance value of the thickness of the first PP layer is equal to ±0.1m, where m is the thickness value of the first PP layer; The tolerance value of the thickness of the second PP layer is equal to ±0.1n, where n is the thickness value of the second PP layer.

[0011] In one embodiment, the surface of the first solder resist layer is provided with an integrally formed first surface treatment layer and a first conductor thickening portion, the thickness of the first conductor thickening portion being 0.2μm~1μm.

[0012] In one embodiment, the surface of the second solder resist layer is provided with an integrally formed second surface treatment layer and a second conductor thickening portion, the thickness of the second conductor thickening portion being 0.2μm~1μm.

[0013] In one embodiment, the drilling accuracy of the first laser blind hole is ±25 μm.

[0014] In one embodiment, the drilling accuracy of the second laser blind hole is ±25μm.

[0015] Compared with the prior art, this disclosure has at least the following advantages: 1) The above-mentioned multilayer high-speed board, since the substrate layer is a glass fiber reinforced material layer, makes the structure of the substrate layer a randomly oriented structure, which effectively eliminates the periodic weaving pattern, making the medium more uniform on the entire plane, and thus making the substrate more consistent. 2) Since the first laser blind via extends to the first inner circuit layer through the first outer circuit layer and the first PP layer, the first outer circuit layer is connected to the first inner circuit layer through the first laser blind via. Furthermore, since the first inner circuit layer has a first inner circuit body and first compensation etching portions located on both sides of the first inner circuit body, compensation etching is performed on both sides of the first inner circuit body to form first compensation etching portions, thus avoiding the problem of insufficient line width after etching the first inner circuit layer. Similarly, the second outer circuit layer is connected to the second inner circuit layer through the second laser blind via, and compensation etching is performed on both sides of the second inner circuit body of the second inner circuit layer to form second compensation etching portions, thus avoiding the problem of insufficient line width after etching the second inner circuit layer. This effectively avoids the problem of insufficient line width after etching the inner layer circuits. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this disclosure and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a multilayer high-speed board according to an embodiment; Figure 2 for Figure 1 A partial cross-sectional view of the first inner circuit layer of the multilayer high-speed board shown. Figure 3 for Figure 1 A partial cross-sectional view of the second inner circuit layer of the multilayer high-speed board shown. Detailed Implementation

[0018] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure.

[0019] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly attached to the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0021] This application provides a multilayer high-speed board, comprising a first solder mask layer, a first outer circuit layer, a first PP layer, a first inner circuit layer, a substrate layer, a second inner circuit layer, a second PP layer, a second outer circuit layer, and a second solder mask layer stacked sequentially. The substrate layer is a glass fiber reinforced material layer; The first outer circuit layer has a first laser blind hole, which extends through the first outer circuit layer and the first PP layer to the first inner circuit layer; the first inner circuit layer has a first inner circuit body and a first compensation etching portion located on both sides of the first inner circuit body. The second outer circuit layer has a second laser blind via, which extends through the second outer circuit layer and the second PP layer to the second inner circuit layer; the second inner circuit layer has a second inner circuit body and a second compensation etching portion located on both sides of the second inner circuit body.

[0022] The aforementioned multilayer high-speed board, due to its glass fiber reinforced substrate layer, has a randomly oriented structure, effectively eliminating periodic weaving patterns and resulting in a more uniform dielectric material across the entire plane, thus improving substrate consistency. The first laser blind via extends through the first outer circuit layer and the first PP layer to the first inner circuit layer, allowing the first outer circuit layer to conduct through the first laser blind via to the first inner circuit layer. Furthermore, the first inner circuit layer has a first inner circuit body and first compensation etching portions located on both sides of the first inner circuit body; that is, compensation etching is performed on both sides of the first inner circuit body to form first compensation etching portions, avoiding the problem of insufficient line width after etching the first inner circuit layer. Similarly, the second outer circuit layer conducts through the second laser blind via to the second inner circuit layer, and compensation etching is performed on both sides of the second inner circuit body to form second compensation etching portions, avoiding the problem of insufficient line width after etching the second inner circuit layer. This effectively avoids the problem of insufficient line width after etching the inner layer circuits.

[0023] like Figures 1 to 3 As shown, to better understand the technical solution and beneficial effects of this disclosure, the following detailed description is provided in conjunction with specific embodiments: One embodiment of the multilayer high-speed board 10 includes a first solder mask layer 100, a first outer circuit layer 200, a first PP (prepreg) layer 300, a first inner circuit layer 400, a substrate layer 500, a second inner circuit layer 600, a second PP layer 700, a second outer circuit layer 800, and a second solder mask layer 900, which are stacked and connected in sequence.

[0024] The substrate layer 500 is a glass fiber reinforced material layer, which makes the structure of the substrate layer 500 randomly oriented. This effectively eliminates the problem of periodic weaving patterns in the high-speed plates of traditional FR4 materials, making the medium more uniform on the entire plane, and thus making the substrate more consistent.

[0025] Furthermore, the first outer circuit layer 200 has a first laser blind via 201, which extends through the first outer circuit layer 200 and the first PP layer 300 to the first inner circuit layer 400, electrically connecting the first outer circuit layer 200 to the first inner circuit layer 400 via the first laser blind via 201. The first inner circuit layer 400 has a first inner circuit body 410 and first compensation etching portions 420 located on both sides of the first inner circuit body 410. That is, compensation etching is performed on both sides of the first inner circuit body 410 of the first inner circuit layer 400 to form the first compensation etching portions 420 on both sides of the first inner circuit body 410, avoiding the problem of the line width being too small after etching the first inner circuit layer 400. In the design, the line width of the first inner circuit body 410 is slightly wider than the target line width, so that etching deviation compensation can be performed during etching, and the width of the etched first inner circuit layer 400 meets the actual requirements, especially for the thicker first inner circuit layer 400. In one embodiment, the thickness of the first inner circuit layer 400 is 1 oz.

[0026] Furthermore, the second outer circuit layer 800 has a second laser blind via 801, which extends through the second outer circuit layer 800 and the second PP layer 700 to the second inner circuit layer 600, electrically connecting the second outer circuit layer 800 to the second inner circuit layer 600 via the second laser blind via 801. The second inner circuit layer 600 has a second inner circuit body 610 and second compensation etching portions 620 located on both sides of the second inner circuit body 610. That is, compensation etching is performed on both sides of the second inner circuit body 610 of the second inner circuit layer 600 to form second compensation etching portions 620 on both sides of the second inner circuit body 610, avoiding the problem of the line width being too small after etching the second inner circuit layer 600. In the design, the line width of the second inner circuit body 610 is slightly wider than the target line width, so that etching deviation compensation can be performed during etching, and the width of the etched second inner circuit layer 600 meets the actual requirements, especially for the thicker second inner circuit layer 600. In one embodiment, the thickness of the second inner circuit layer 600 is 1 oz.

[0027] The aforementioned multilayer high-speed board 10, because the substrate layer 500 is a glass fiber reinforced material layer, has a randomly oriented structure, effectively eliminating periodic weaving patterns and making the dielectric more uniform across the entire plane, thus resulting in better substrate consistency. Since the first laser blind via 201 extends through the first outer circuit layer 200 and the first PP layer 300 to the first inner circuit layer 400, the first outer circuit layer 200 is connected to the first inner circuit layer 400 through the first laser blind via 201. Furthermore, since the first inner circuit layer 400 is provided with a first inner circuit body 410 and first compensation etching portions 420 located on both sides of the first inner circuit body 410, i.e., the first inner... Compensation etching is performed on both sides of the first inner circuit body 410 of the circuit layer 400 to form a first compensation etching portion 420 on both sides of the first inner circuit body 410, thereby avoiding the problem of the circuit width being too small after the first inner circuit layer 400 is etched. Similarly, the second outer circuit layer 800 is connected to the second inner circuit layer 600 through the second laser blind hole 801, and compensation etching is performed on both sides of the second inner circuit body 610 of the second inner circuit layer 600 to form a second compensation etching portion 620 on both sides of the second inner circuit body 610, thereby avoiding the problem of the circuit width being too small after the second inner circuit layer 600 is etched. In this way, the problem of the circuit width being too small after the inner circuit is etched is effectively avoided.

[0028] In one embodiment, the width of the first compensation etching portion 420 is 0.3 mil to 0.5 mil to better compensate for etching problems during the inner layer circuitry process. In this embodiment, the first inner circuit body 410 and the first compensation etching portion 420 are integrally formed.

[0029] In one embodiment, the width of the second compensation etching portion 620 is 0.3mil to 0.5mil to better compensate for etching problems during the inner layer circuitry process. In this embodiment, the second inner circuit body 610 and the second compensation etching portion 620 are integrally formed structures.

[0030] In one embodiment, the thickness tolerance of the first PP layer 300 is equal to ±0.1m, where m is the thickness of the first PP layer 300. This makes the thickness tolerance of the first PP layer 300 smaller, further reducing the impedance tolerance of the multilayer high-speed board 10.

[0031] In one embodiment, the thickness tolerance of the second PP layer 700 is equal to ±0.1n, where n is the thickness value of the second PP layer 700. This smaller thickness tolerance of the second PP layer 700 further reduces the impedance tolerance of the multilayer high-speed board 10. In this embodiment, m equals n. Specifically, m equals 7.5 mil.

[0032] In one embodiment, the surface of the first solder mask layer 100 is provided with an integrally formed first surface treatment layer (not shown) and a first conductor thickening portion (not shown). The thickness of the first conductor thickening portion is 0.2μm~1μm, which reduces the impedance tolerance of the multilayer high-speed board 10.

[0033] In one embodiment, the surface of the second solder resist layer 900 is provided with an integrally formed second surface treatment layer (not shown) and a second conductor thickening portion (not shown). The thickness of the second conductor thickening portion is 0.2μm~1μm, which reduces the impedance tolerance of the multilayer high-speed board 10.

[0034] In one embodiment, the drilling accuracy of the first laser blind hole 201 is ±25μm, which further reduces the impedance tolerance of the multilayer high-speed board 10.

[0035] In one embodiment, the drilling accuracy of the second laser blind hole 801 is ±25μm, which further reduces the impedance tolerance of the multilayer high-speed board 10.

[0036] Compared with the prior art, this disclosure has at least the following advantages: 1) In the above-mentioned multilayer high-speed board 10, since the substrate layer 500 is a glass fiber reinforced material layer, the structure of the substrate layer 500 is a randomly oriented structure, which effectively eliminates the periodic weaving pattern, making the medium more uniform on the entire plane, and thus making the substrate more consistent. 2) Since the first laser blind via 201 extends to the first inner circuit layer 400 through the first outer circuit layer 200 and the first PP layer 300, the first outer circuit layer 200 is connected to the first inner circuit layer 400 through the first laser blind via 201. Furthermore, since the first inner circuit layer 400 has a first inner circuit body 410 and first compensation etching portions 420 located on both sides of the first inner circuit body 410, compensation etching is performed on both sides of the first inner circuit body 410 to form [something] on both sides of the first inner circuit body 410. The first compensation etching portion 420 avoids the problem of the line width being too small after the first inner circuit layer 400 is etched. Similarly, the second outer circuit layer 800 is connected to the second inner circuit layer 600 through the second laser blind hole 801, and compensation etching is performed on both sides of the second inner circuit body 610 of the second inner circuit layer 600 to form the second compensation etching portion 620 on both sides of the second inner circuit body 610, thereby avoiding the problem of the line width being too small after the second inner circuit layer 600 is etched. In this way, the problem of the line width being too small after the inner circuit is etched is effectively avoided.

[0037] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A multilayer high-speed board, characterized in that, It includes a first solder mask layer, a first outer circuit layer, a first PP layer, a first inner circuit layer, a substrate layer, a second inner circuit layer, a second PP layer, a second outer circuit layer, and a second solder mask layer that are stacked and connected in sequence. The substrate layer is a glass fiber reinforced material layer; The first outer circuit layer has a first laser blind hole, which extends through the first outer circuit layer and the first PP layer to the first inner circuit layer; the first inner circuit layer has a first inner circuit body and a first compensation etching portion located on both sides of the first inner circuit body. The second outer circuit layer has a second laser blind hole, which extends through the second outer circuit layer and the second PP layer to the second inner circuit layer; the second inner circuit layer has a second inner circuit body and a second compensation etching part located on both sides of the second inner circuit body.

2. The multilayer high-speed board according to claim 1, characterized in that, The width of the first compensation etching portion is 0.3mil to 0.5mil.

3. The multilayer high-speed board according to claim 1, characterized in that, The first inner circuit body and the first compensation etching part are integrally formed structures.

4. The multilayer high-speed board according to claim 1, characterized in that, The width of the second compensation etching section is 0.3mil to 0.5mil.

5. The multilayer high-speed board according to claim 1, characterized in that, The second inner circuit body and the second compensation etching part are integrally formed.

6. The multilayer high-speed board according to claim 1, characterized in that, The tolerance value of the thickness of the first PP layer is ±0.1m, where m is the thickness value of the first PP layer; The tolerance value of the thickness of the second PP layer is equal to ±0.1n, where n is the thickness value of the second PP layer.

7. The multilayer high-speed board according to claim 1, characterized in that, The surface of the first solder resist layer is provided with an integrally formed first surface treatment layer and a first conductor thickening portion, the thickness of the first conductor thickening portion being 0.2μm~1μm.

8. The multilayer high-speed board according to claim 1, characterized in that, The surface of the second solder resist layer is provided with an integrally formed second surface treatment layer and a second conductor thickening portion, the thickness of the second conductor thickening portion being 0.2μm~1μm.

9. The multilayer high-speed board according to any one of claims 1 to 8, characterized in that, The drilling accuracy of the first laser blind hole is ±25μm.

10. The multilayer high-speed board according to any one of claims 1 to 8, characterized in that, The drilling accuracy of the second laser blind hole is ±25μm.

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