Gold finger structure of a multi-layer board DDR5 memory stick

Abstract

The utility model discloses a kind of gold finger structure of multilayer board DDR5 memory stick, it is related to memory stick technical field, the multilayer board includes top layer, bottom layer and the inner layer between top layer and bottom layer, gold finger structure is provided on top layer and bottom layer;The inner layer includes multiple GND signal planes and several power signal planes, form first shielding plane using the GND signal plane in inner layer closest to top layer, form second shielding plane using the GND signal plane in inner layer closest to bottom layer;In multilayer board thickness direction, first shielding plane and second shielding plane respectively with gold finger structure on top layer and bottom layer are apart from preset distance, and the inner layer between first shielding plane and gold finger structure on top layer, and the inner layer between second shielding plane and gold finger structure on bottom layer is hollowed out and handled.This structure can solve the signal crosstalk at gold finger, impedance discontinuity and signal integrity problem.

Description

Technical Field

[0001] This utility model relates to the field of memory module technology, and in particular to a gold finger structure for a multilayer DDR5 memory module. Background Technology

[0002] A printed circuit board (PCB) is an important component of electrical or electronic systems, manufactured using copper foil substrates. It serves as a crucial electronic part, supporting electronic components and carrying the electrical connections between them. Because it is produced using electronic printing techniques, it is called a "printed" circuit board. PCBs can be classified according to the number of circuit layers into single-sided, double-sided, and multi-layer boards.

[0003] The gold fingers (connecting fingers) are composed of numerous golden-yellow conductive contacts. They are called "gold fingers" because their surface is gold-plated and the conductive contacts are arranged in a finger-like pattern. They are commonly found in the interaction between devices such as memory modules (e.g., DDR5), graphics cards (PCIe interface), and solid-state drives (M.2 SSDs) and the motherboard.

[0004] RAM is a core storage component of modern electronic devices, serving as a crucial foundation for their stable and efficient operation. During operation, RAM is essential for temporary caching and high-speed data access in electronic devices. Insufficient capacity or inadequate performance can directly lead to program loading delays, system lag, and even crashes. In multi-tasking scenarios, RAM enables isolated allocation of memory space between tasks, ensuring smooth process switching and avoiding efficiency losses caused by storage resource contention. Furthermore, for high-performance applications such as big data computing and high-definition video rendering, the read / write speed and maximum capacity of RAM directly determine the device's ability to handle complex workloads.

[0005] Currently, DDR5 memory modules are beginning to emerge. Compared to previous generations of DDR memory, DDR5 memory modules offer significantly improved performance, boasting wider bandwidth, higher speeds, larger capacities, and lower power consumption. However, these improvements in speed, density, and power consumption also introduce signal integrity issues. High-speed data transmission reduces the margin tolerance for crosstalk, synchronous switching noise, and receiver signal quality. Simultaneously, signals become more sensitive to impedance discontinuities, and reflections caused by these discontinuities further exacerbate signal integrity problems. Currently, the design and processing of DDR gold fingers are relatively simple. Requirements regarding the hollowing out of the pads, chamfer angles, and gold plating thickness are primarily designed to ensure the reliability of mechanical insertion and removal. Existing technologies suffer from signal integrity issues related to impedance discontinuities and crosstalk at the gold fingers of multi-layer DDR5 memory modules. Utility Model Content

[0006] In response to the aforementioned problems and technical requirements, the applicant has proposed a gold finger structure for a multilayer DDR5 memory module.

[0007] The technical solution of this utility model is as follows:

[0008] A gold finger structure for a multilayer DDR5 memory module, wherein the multilayer board includes a top layer, a bottom layer, and an inner layer located between the top layer and the bottom layer, and gold finger structures are provided on the top layer and the bottom layer;

[0009] The inner layer includes multiple GND signal planes and several power signal planes. The GND signal plane closest to the top layer in the inner layer forms a first shielding plane, and the GND signal plane closest to the bottom layer in the inner layer forms a second shielding plane.

[0010] In the thickness direction of the multilayer board, the first shielding plane and the second shielding plane are respectively separated from the gold finger structure disposed on the top layer and the bottom layer by a preset distance, and the inner layer between the first shielding plane and the gold finger structure on the top layer, and the inner layer between the second shielding plane and the gold finger structure disposed on the bottom layer are hollowed out.

[0011] A further technical solution is that the multilayer board is rectangular and divided into a main wiring area, a gold finger area and a chamfer area along the width direction, and the gold finger structure disposed on the top and bottom layers is located within the gold finger area.

[0012] A further technical solution is that the gold finger structure includes several single-ended signal gold fingers, several pairs of differential signal gold fingers, several GND gold fingers, and several power supply gold fingers arranged in parallel along the length of the multilayer board.

[0013] A further technical solution is to provide multiple GND vias above and below the GND gold fingers, and to provide a power via above each power gold finger; the GND vias and power vias are electroplated through holes, the GND vias are connected to the GND signal plane in the inner layer, and the power vias are connected to the power signal plane in the inner layer.

[0014] A further technical solution is that the projection area of ​​the GND signal plane in the inner layer covers the main wiring area, the gold finger, and the GND via located below the GND gold finger.

[0015] The further technical solution is that the GND vias located above the GND gold fingers are aligned along the length of the multilayer board, and the GND vias located below the GND gold fingers are also aligned along the length of the multilayer board.

[0016] For each GND via, the center of the GND via is equidistant from the two adjacent gold fingers along the length of the multilayer board.

[0017] The further technical solution is that for each GND gold finger, a GND via is provided on the upper and lower sides of both sides of the GND gold finger.

[0018] For each GND gold finger, the GND vias located above the two sides of the GND gold finger are connected by a first horizontal trace, and the GND vias located below the two sides of the GND gold finger are connected by a second horizontal trace. The first horizontal trace and the second horizontal trace are connected by a vertical trace to form an I-type GND trace, and the vertical trace is connected to the GND gold finger.

[0019] When multiple GND gold fingers are arranged adjacently along the length of the multilayer board, the multiple first horizontal traces corresponding to the multiple GND gold fingers are connected, and the multiple second horizontal traces corresponding to the multiple GND gold fingers are connected.

[0020] A further technical solution is that the GND vias and power vias located above the GND gold fingers are located within the main wiring area, and the GND vias located below the GND gold fingers are located within the gold finger area.

[0021] A further technical solution is that the power gold finger is connected to the corresponding power via through a power trace, the single-ended signal gold finger is connected to one end of the single-ended signal trace, and the other end of the single-ended signal trace extends to the main wiring area.

[0022] A further technical solution is that each pair of differential signal gold fingers includes a first differential signal gold finger and a second differential signal gold finger, and a GND via is provided above and below the gap between the first differential signal gold finger and the second differential signal gold finger; the first differential signal gold finger and the second differential signal gold finger are respectively connected to one end of a differential signal trace, and the other ends of the two differential signal traces extend to the main wiring area.

[0023] The beneficial technical effects of this utility model are:

[0024] This invention provides a gold finger structure for a multilayer DDR5 memory module. Compared to the traditional method of completely hollowing out and drilling holes under the gold finger in multilayer PCBs, this invention optimizes the connection method of the inner GND signal plane and the ground hole drilling method below the gold finger. By using holes above and below the GND gold finger and increasing the inner GND signal plane, more GND connections and isolation are achieved, thereby reducing crosstalk between signals and shortening their return path. Simultaneously, by controlling the distance between the gold finger and the inner GND signal plane below, impedance discontinuities at this point can be further optimized and controlled, reducing reflections. During high-speed DDR5 operation, it significantly optimizes the signal quality at the gold finger without requiring additional components or excessive design or processing costs, offering significant advantages and broad application prospects. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of one embodiment of the gold finger structure of the multilayer DDR5 memory module provided by this utility model.

[0026] Figure 2 This is a cross-sectional schematic diagram of one embodiment of the multilayer DDR5 memory module provided by this utility model.

[0027] Figure 3 This is a schematic diagram of one embodiment of the first / second shielding layer provided by this utility model.

[0028] Figure 4 This is a front view of a 288-pin DDR5 DIMM PCB in one embodiment of this utility model.

[0029] Figure 5 This is a schematic diagram of the back of a 288-pin DDR5 DIMM PCB in one embodiment of this utility model.

[0030] Figure label:

[0031] 100 - Main wiring area, 200 - Gold finger area, 300 - Chamfered area;

[0032] F101 - Single-ended signal gold finger, F102 - Differential signal gold finger, F103 - GND gold finger, F104 - Power gold finger; V101 - GND via, V102 - Power via;

[0033] T101 - Single-ended signal trace, T102 - Differential signal trace, T103 - GND trace, T104 - Power signal trace; P101 - GND signal plane, P102 - Power signal plane. Detailed Implementation

[0034] The specific embodiments of this utility model will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0035] This utility model provides a gold finger structure for a multi-layer DDR5 memory module. The multi-layer board includes a top layer, a bottom layer, and an inner layer located between the top layer and the bottom layer. Gold finger structures are provided on the top layer and the bottom layer.

[0036] The inner layer includes multiple GND signal planes P101 and several power signal planes P102. The GND signal plane P101 closest to the top layer in the inner layer forms a first shielding plane, and the GND signal plane P101 closest to the bottom layer in the inner layer forms a second shielding plane.

[0037] In the thickness direction of the multilayer board, the first shielding plane and the second shielding plane are respectively separated from the gold finger structure disposed on the top layer and the bottom layer by a preset distance, and the inner layer between the first shielding plane and the gold finger structure disposed on the top layer, and the inner layer between the second shielding plane and the gold finger structure disposed on the bottom layer are hollowed out.

[0038] Specifically, the multilayer board refers to a multilayer PCB. The inner layers of the multilayer board include overlapping multiple insulating support layers and multiple metal layers. The metal layers form the GND signal plane P101 and the power signal plane P102. Any two adjacent signal planes in the inner layer are connected by the insulating support layers. In this embodiment, a GND signal plane is set at a predetermined distance below the gold finger structure of the top and bottom layers, respectively.

[0039] P101 forms a symmetrical first and second shielding plane, and hollows out the inner layer between the first and second shielding planes and the gold finger structures on the top and bottom layers to solve the signal integrity problems of impedance discontinuity and crosstalk at the gold fingers of multilayer DDR5 memory modules. Hollowing out the inner layer between the first and second shielding planes and the gold finger structures on the top and bottom layers means that there is no signal plane in the inner layer between the first and second shielding planes and the gold finger structures on the top and bottom layers.

[0040] Figure 1 This is a partial structural diagram of a 288-pin DDR5 DIMM PCB, illustrating one embodiment of the gold finger structure of the multilayer DDR5 memory module. Figure 1 As shown, the multilayer board is rectangular and divided along its width into a main wiring area 100, a gold finger area 200, and a chamfer area 300. The gold finger structure, located on the top and bottom layers, is situated within the gold finger area 200. It should be noted that multilayer DDR5 memory modules are not limited to this type of board. Figure 1 The part shown, Figure 4-5 This diagram shows the complete front and back views of the 288-pin DDR5 DIMM PCB. Figure 1 The part shown corresponds to Figure 4 The area outlined in the middle is only for illustrating the key part of the structure of this utility model (gold finger structure), the multilayer board.

[0041] The other structures involved in DDR5 memory modules are consistent with those of existing conventional multi-layer PCB DDR5 memory modules, and will not be elaborated further here.

[0042] Furthermore, the gold finger structure includes several single-ended signal gold fingers F101, several pairs of differential signal gold fingers F102, several GND gold fingers F103, and several power supply gold fingers F104 arranged side by side along the length direction of the multilayer board, with the length direction of the gold fingers being the width direction of the multilayer board.

[0043] Multiple GND vias V101 are provided above and below the GND gold finger F103 along the length of the multilayer board. The GND vias V101 above the GND gold finger F103 are aligned along the length of the multilayer board, and the GND vias V101 below the GND gold finger F103 are also aligned along the length of the multilayer board.

[0044] Figure 2 This diagram shows a cross-sectional view of a multi-layer DDR5 memory module structure. Figure 2 As can be seen, in this embodiment, the preset distance between the gold finger structure located at the top / bottom layer and the first / second shielding plane in the thickness direction of the multilayer board is 0.38mm (15mil). In specific implementation, the preset distance can be obtained by simulation using existing technical means based on the thickness of the multilayer PCB, so as to achieve the effect of optimizing and controlling the impedance discontinuity at the gold finger structure. Figure 3 A schematic diagram of one embodiment of the first / second shielding layer is shown, as follows: Figure 2-3 As shown, the projection area of ​​the GND signal plane P101 in the inner layer must cover the main wiring area 100, the gold finger, and the GND via V101 located below the GND gold finger, and maintain a preset safe distance from the chamfer area in the width direction of the multilayer board.

[0045] For each GND via V101, the center of the GND via V101 is equidistant from the two adjacent gold fingers along the length of the multilayer board. That is, the GND via V101 is positioned above / below the interval between the two gold fingers, and the center of the GND via V101 is located on the axis of symmetry of the two gold fingers.

[0046] When distributing GND vias V101, it is also necessary to ensure that for each GND gold finger F103, there is a GND via V101 above and below both sides of the GND gold finger F103.

[0047] like Figure 1As shown, for each GND gold finger F103, the GND vias V101 located above both sides of the GND gold finger F103 are connected by a first horizontal trace, and the GND vias V101 located below both sides of the GND gold finger F103 are connected by a second horizontal trace. The first horizontal trace and the second horizontal trace are connected by a vertical trace to form a type I GND trace T103, which is connected to the GND gold finger F103. Furthermore, when multiple GND gold fingers F103 are arranged adjacent to each other along the length of the multilayer board, the multiple first horizontal traces corresponding to the multiple GND gold fingers F103 are connected, and the multiple second horizontal traces corresponding to the multiple GND gold fingers F103 are connected.

[0048] Furthermore, a power via V102 is provided above each power gold finger F104, and the power gold finger F104 is connected to the corresponding power via V102 through a power trace T104; the placement of the power via V102 can be as follows: Figure 1 The GND via V101 shown is aligned along the length of the multilayer board, or it can be staggered with the GND via V101, as long as it meets the optimization requirements of the power signal design constraints in the prior art and is within the manufacturing capabilities of the processing technology. There is no particularly mandatory requirement for a fixed placement position. The GND via V101 and the power via V102 are electroplated through holes. The GND via V101 is connected to the GND signal plane P101 in the inner layer, and the power via V102 is connected to the power signal plane P102 in the inner layer. The GND via V101 and the power via V102 located above the GND gold finger F103 are located within the main wiring area 100, and the GND via V101 located below the GND gold finger F103 is located within the gold finger area 200.

[0049] Specifically, GND vias V101 and V102 are respectively provided with GND via pads and power via pads at both ends. These GND via pads and power via pads are located on the top and bottom layers of the multilayer board, respectively. The GND vias V101 located above / below the GND gold finger F103 are connected via first / second horizontal traces, meaning the GND via pads of the GND vias V101 located above / below the GND gold finger F103 are connected via first / second horizontal traces. The power gold finger F104 is connected to the corresponding power via V102 via power trace T104, meaning the power gold finger F104 is connected to the power via pad of the corresponding power via V102 via power trace T104. The edge of the GND via pad connected to the GND gold finger F103 via the type I GND trace T103 should be as close as possible to the connected GND gold finger F103. The edge of the power via pad connected to the power gold finger F104 should also be as close as possible to the connected power gold finger F104. Within the manufacturing capabilities of the processing technology, the closer the distance, the better.

[0050] In some embodiments, the diameters of GND via V101 and power via V102 can be 8 mil, and the diameters of the GND via pad and power via pad can be 16 mil. In other embodiments, the diameters of GND via V101 and power via V102 can be 10 mil, and the diameters of the GND via pad and power via pad can be 16 mil. In still other embodiments, the diameters of GND via V101 and power via V102 can be 10 mil, and the diameters of the GND via pad and power via pad can be 18 mil. In specific implementations, the diameters of GND via V101 and power via V102, as well as the diameters of the GND via pad and power via pad, can be set according to actual conditions.

[0051] Furthermore, the single-ended signal gold finger F101 is used to represent the single-ended signal of DDR5, such as data signal, address signal and command bus signal. On the top and bottom layers of the multilayer board, the single-ended signal gold finger F101 is connected to one end of the single-ended signal trace T101, and the other end of the single-ended signal trace T101 extends to the main wiring area 100.

[0052] Furthermore, the differential signal gold fingers F102 are used to represent the differential signals of DDR5, such as DQS signals, clock signals, etc. Each pair of differential signal gold fingers F102 includes a first differential signal gold finger and a second differential signal gold finger. A GND via V101 is provided above and below the gap between the first differential signal gold finger and the second differential signal gold finger, consistent with the above-mentioned arrangement of the GND via V101. The center of the GND via V101 located above / below the gap between the two differential signal gold fingers F102 is equal to the distance between the two differential signal gold fingers F102 in the length direction of the multilayer board. On the top and bottom layers of the multilayer board, the first differential signal gold finger and the second differential signal gold finger are respectively connected to one end of a differential signal trace T102. The other ends of the two differential signal traces T102 extend to the main wiring area 100. The two differential signal traces extending to the main wiring area 100 are respectively located on both sides of a GND via V101.

[0053] In the description of this application, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0054] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0055] In the description of this application, if terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "vertical", "horizontal" appear, these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0056] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0057] In this application, unless otherwise expressly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0058] The above descriptions are merely preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations that can be directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.

Claims

1. A gold finger structure for a multilayer DDR5 memory module, characterized in that, The multilayer board includes a top layer, a bottom layer, and an inner layer located between the top layer and the bottom layer, and the top layer and the bottom layer are provided with gold finger structures. The inner layer includes multiple GND signal planes and several power signal planes. The GND signal plane closest to the top layer in the inner layer forms a first shielding plane, and the GND signal plane closest to the bottom layer in the inner layer forms a second shielding plane. In the thickness direction of the multilayer board, the first shielding plane and the second shielding plane are respectively separated from the gold finger structure disposed on the top layer and the bottom layer by a preset distance, and the inner layer between the first shielding plane and the gold finger structure on the top layer, and the inner layer between the second shielding plane and the gold finger structure disposed on the bottom layer are hollowed out.

2. The gold finger structure of the multilayer DDR5 memory module according to claim 1, characterized in that, The multilayer board is rectangular and divided into a main wiring area, a gold finger area, and a chamfer area along its width. The gold finger structure disposed on the top and bottom layers is located within the gold finger area.

3. The gold finger structure of the multilayer DDR5 memory module according to claim 2, characterized in that, The gold finger structure includes several single-ended signal gold fingers, several pairs of differential signal gold fingers, several GND gold fingers, and several power supply gold fingers arranged side by side along the length of the multilayer board.

4. The gold finger structure of the multilayer DDR5 memory module according to claim 3, characterized in that, Multiple GND vias are provided above and below the GND gold fingers, and a power via is provided above each power gold finger; the GND vias and power vias are electroplated through holes, the GND vias are connected to the GND signal plane in the inner layer, and the power vias are connected to the power signal plane in the inner layer.

5. The gold finger structure of the multilayer DDR5 memory module according to claim 4, characterized in that, The projection area of ​​the GND signal plane in the inner layer covers the main wiring area, the gold finger, and the GND via located below the GND gold finger.

6. The gold finger structure of the multilayer DDR5 memory module according to claim 5, characterized in that, The GND vias located above the GND gold fingers are aligned along the length of the multilayer board, and the GND vias located below the GND gold fingers are also aligned along the length of the multilayer board. For each GND via, the center of the GND via is equidistant from the two adjacent gold fingers along the length of the multilayer board.

7. The gold finger structure of the multilayer DDR5 memory module according to claim 6, characterized in that, For each GND gold finger, a GND via is provided on the top and bottom sides of both sides of the GND gold finger. For each GND gold finger, the GND vias located above the two sides of the GND gold finger are connected by a first horizontal trace, and the GND vias located below the two sides of the GND gold finger are connected by a second horizontal trace. The first horizontal trace and the second horizontal trace are connected by a vertical trace to form an I-type GND trace, and the vertical trace is connected to the GND gold finger. When multiple GND gold fingers are arranged adjacently along the length of the multilayer board, the multiple first horizontal traces corresponding to the multiple GND gold fingers are connected, and the multiple second horizontal traces corresponding to the multiple GND gold fingers are connected.

8. The gold finger structure of the multilayer DDR5 memory module according to claim 5, characterized in that, GND vias and power vias located above the GND gold finger are located within the main wiring area, while GND vias located below the GND gold finger are located within the gold finger area.

9. The gold finger structure of the multilayer DDR5 memory module according to claim 5, characterized in that, The power gold finger is connected to the corresponding power via through a power trace, the single-ended signal gold finger is connected to one end of the single-ended signal trace, and the other end of the single-ended signal trace extends to the main wiring area.

10. The gold finger structure of the multilayer DDR5 memory module according to claim 6, characterized in that, Each pair of differential signal gold fingers includes a first differential signal gold finger and a second differential signal gold finger. A GND via is provided above and below the gap between the first differential signal gold finger and the second differential signal gold finger. The first differential signal gold finger and the second differential signal gold finger are respectively connected to one end of a differential signal trace, and the other ends of the two differential signal traces extend to the main wiring area.

Images