Semiconductor device and electronic apparatus
Patent Information
- Application Number
- CN202522274793.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-27
- Publication Date
- 2026-10-23
- Estimated Expiration
- 2035-10-27
AI Technical Summary
但芯片偏置后，芯片封装结构容易发生翘曲
[0015]本申请实施例提供的半导体器件在第二方向上，第一芯片的正投影的部分与第三芯片的正投影的部分交叠时，第一芯片在第一方向上与第三芯片偏置排布，可以防止第三芯片对第一芯片的散热路径造成阻碍，有利于提高第三芯片的散热性能，避免热量在局部集中。在第二方向上，第二芯片的正投影落入第三芯片的正投影内时，第二芯片可以充分利用第三芯片下方的空间，避免因第一芯片的偏置布局导致空间利用率降低。并且，第二芯片的位置设置可降低第一芯片偏置布局带来的结构分布不对称性，改善半导体器件的应力分布，有利于降低热机械应力，防止封装翘曲，提升了产品的可靠性。
Smart Images
Figure CN224891022U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device and electronic device. Background Technology
[0002] In the field of semiconductor packaging, HBPOP (High Bandwidth Package-on-Package) packaging technology is widely used in high-performance computing, smart terminals and Internet of Things devices due to its high bandwidth, high integration and thinness.
[0003] To improve heat dissipation efficiency, related technologies place stacked chips at an offset position to increase the contact area between the chip and the package edge, thereby enhancing heat dissipation. However, after the chips are offset, the chip package structure is prone to warping. Utility Model Content
[0004] This application provides a semiconductor device and an electronic device.
[0005] A first aspect of this application provides a semiconductor device, the semiconductor device comprising: First wiring structure layer; The second wiring structure layer is disposed opposite to and spaced apart from the first wiring structure layer; A first layer chip is disposed between the first wiring structure layer and the second wiring structure layer; the first layer chip includes at least a first chip and a second chip spaced apart in a first direction, and at least the first chip is electrically connected to the second wiring structure layer. A heat sink is located on the side of the first wiring structure layer away from the first layer chip; it is used to dissipate heat from the first layer chip. The second layer chip includes a third chip, which is located on the side of the first wiring structure layer away from the second wiring structure layer and on the side of the heat sink, and is electrically connected to the first wiring structure layer; the orthographic projection of the second chip on the second wiring structure layer falls into the orthographic projection of the third chip on the second wiring structure layer, and the orthographic projection of the first chip on the second wiring structure layer and the orthographic projection of the third chip on the second wiring structure layer partially overlap; At least one conductive post is located between the first wiring structure layer and the second wiring structure layer for electrically connecting the first wiring structure layer and the second wiring structure layer.
[0006] In some embodiments, the conductive post includes a first sub-conductive post, which is disposed between the first chip and the second chip.
[0007] In some embodiments, the conductive pillar further includes a second sub-conductive pillar; the second sub-conductive pillar is located on at least one side of opposite sides of the first layer chip in a first direction.
[0008] In some embodiments, the first chip is a data processing chip, the second chip is an auxiliary support chip used only to balance the stress of the first layer chip, and the third chip is a storage chip.
[0009] In some embodiments, the conductive pillar includes a third sub-conductive pillar, which penetrates the second chip.
[0010] In some embodiments, the heat sink and the third chip are arranged along a first direction, and the first chip is closer to the heat sink than the second chip.
[0011] In some embodiments, the side of the second chip facing away from the first chip is flush with the side of the third chip facing away from the heat sink.
[0012] In some embodiments, the orthographic projection of the heat sink on the second wiring structure layer overlaps with the orthographic projection of the first chip on the second wiring structure layer; And / or, the first wiring structure layer is provided with a metal wiring layer, and the orthographic projection of the metal wiring layer on the second wiring structure layer overlaps with the orthographic projection of the heat sink on the second wiring structure layer.
[0013] In some embodiments, the first chip and the second chip are both data processing chips, and the third chip is a storage chip.
[0014] A second aspect of this application provides an electronic device, the electronic device including a circuit board and the aforementioned semiconductor device; a second wiring structure layer of the semiconductor device is disposed on the circuit board facing the circuit board and electrically connected to the circuit in the circuit board.
[0015] In the second direction, when the orthographic projection of the first chip overlaps with that of the third chip, the first chip is offset from the third chip in the first direction. This prevents the third chip from obstructing the heat dissipation path of the first chip, improving its heat dissipation performance and preventing heat concentration in localized areas. When the orthographic projection of the second chip falls within the orthographic projection of the third chip in the second direction, the second chip can fully utilize the space below the third chip, avoiding reduced space utilization due to the offset layout of the first chip. Furthermore, the positioning of the second chip reduces the structural asymmetry caused by the offset layout of the first chip, improves the stress distribution of the semiconductor device, reduces thermomechanical stress, prevents package warpage, and enhances product reliability.
[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description
[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.
[0018] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application; Figures 2 to 6 A schematic diagram of the structure of a semiconductor device provided for other embodiments of this application. Detailed Implementation
[0019] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.
[0020] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.
[0021] The semiconductor devices and electronic devices according to embodiments of this application will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can complement or combine with each other.
[0022] This application provides a semiconductor device, such as... Figure 1 As shown, the semiconductor device includes a first wiring structure layer 10, a second wiring structure layer 20, a first-layer chip 30, a second-layer chip 40, a heat sink 50, and conductive pillars 60.
[0023] The first wiring structure layer 10 and the second wiring structure layer 20 are positioned opposite each other and spaced apart. A first-layer chip 30 is disposed between the first wiring structure layer 10 and the second wiring structure layer 20, and the first-layer chip 30 includes at least a first chip 31 and a second chip 32 spaced apart in the first direction X. Both the first chip 31 and the second chip 32 are electrically connected to the second wiring structure layer 20, or only the first chip 31 is electrically connected to the second wiring structure layer 20.
[0024] like Figure 1 As shown in the figure, a first direction X and a second direction Y are illustrated. The second direction Y is the thickness direction of the semiconductor device, which is also the stacking direction of the first wiring structure layer 10 and the second wiring structure layer 20. The first direction X is perpendicular to the second direction Y, which is the length or width direction of the semiconductor device.
[0025] The second layer chip 40 includes a third chip 41, which is located on the side of the first wiring structure layer 10 away from the second wiring structure layer 20 and is electrically connected to the first wiring structure layer 10. The orthographic projection of the second chip 32 on the second wiring structure layer 20 falls within the orthographic projection of the third chip 41 on the second wiring structure layer 20, and the orthographic projection of the first chip 31 on the second wiring structure layer 20 overlaps with the orthographic projection of the third chip 41 on the second wiring structure layer 20.
[0026] The heat sink 50 is located on the side of the first wiring structure layer 10 away from the first layer chip 30 and on the side of the third chip 41, and is used to dissipate heat from the first layer chip 30.
[0027] The number of conductive posts 60 is at least one. The conductive post 60 is located between the first wiring structure layer 10 and the second wiring structure layer 20, and is used to electrically connect the first wiring structure layer 10 and the second wiring structure layer 20, thereby realizing the electrical connection between the first layer chip 30 and the second layer chip 40.
[0028] In the semiconductor device provided in this application embodiment, when the orthographic projection portion of the first chip 31 overlaps with the orthographic projection portion of the third chip 41 in the second direction Y, the first chip 31 and the third chip 41 are offsetly arranged in the first direction X. This can prevent the third chip 41 from obstructing the heat dissipation path of the first chip 31, which is beneficial to improving the heat dissipation performance of the third chip 41 and avoiding heat concentration in a local area.
[0029] In the second direction Y, when the orthographic projection of the second chip 32 falls within the orthographic projection of the third chip 41, the second chip 32 can fully utilize the space below the third chip 41, avoiding reduced space utilization due to the biased layout of the first chip 31. Furthermore, the placement of the second chip 32 can reduce the asymmetry in structural distribution caused by the biased layout of the first chip 31, improve the stress distribution of the semiconductor device, help reduce thermomechanical stress, prevent package warping, and improve product reliability.
[0030] In one embodiment, the first wiring structure layer 10 and the second wiring structure layer 20 are wiring substrates or rewiring layers, providing mechanical support for the chip. Both the first wiring structure layer 10 and the second wiring structure layer 20 may contain metal wiring layers for electrical connections. Figure 1 In the embodiment shown, a welding structure 21 is provided on the side of the second wiring structure layer 20 away from the first wiring structure layer 10, and the semiconductor device can be electrically connected to the external circuit through the welding structure 21.
[0031] In one embodiment, such as Figure 1 As shown, the heat sink 50 and the third chip 41 are arranged along the first direction X, and the first chip 31 is closer to the heat sink 50 than the second chip 32. The first chip 31 is usually a high-power chip, which generates more heat when in operation. By placing the first chip 31 closer to the heat sink 50, it is more conducive to the heat generated by the first chip 31 being transferred to the outside through the heat sink 50, thus avoiding the accumulation of heat inside the semiconductor device.
[0032] In one embodiment, such as Figure 1 As shown, the orthographic projection of the heat sink 50 on the second wiring structure layer 20 overlaps with the orthographic projection of the first chip 31 on the second wiring structure layer 20. The heat sink 50 is made of a material with high thermal conductivity, which can quickly conduct heat from inside the semiconductor device to the outside. When the heat sink 50 directly covers or is close to the heat-generating area of the first chip 31, it can shorten the heat conduction path, reduce thermal resistance, and improve the heat dissipation efficiency of the first chip 31.
[0033] In one embodiment, such as Figure 1 As shown, a metal wiring layer 11 is provided within the first wiring structure layer 10. The orthographic projection of the metal wiring layer 11 onto the second wiring structure layer 20 overlaps with the orthographic projection of the heat sink 50 onto the second wiring structure layer 20. The heat generated by the first chip 30 is transferred to the first wiring structure layer 10 and then conducted to the heat sink 50 through the metal wiring layer 11. In the second direction Y, when the orthographic projections of the metal wiring layer 11 and the heat sink 50 overlap, the metal wiring layer 11 can quickly guide heat to the heat sink 50, improving the heat dissipation efficiency of the semiconductor device.
[0034] In one embodiment, the semiconductor device further includes a molding compound 70 located between the first wiring structure layer 10 and the second wiring structure layer 20, and covering the first chip 31 and the second chip 32.
[0035] In one embodiment, such as Figure 1 As shown, the first chip 31 and the second chip 32 are both data processing chips, and the third chip 41 is a storage chip. The storage chip is responsible for high-speed data storage and caching, and can provide high-frequency data access for the data processing chip; the data processing chip is used to perform computing tasks and efficiently process large-scale data. In this embodiment, the first chip 31 and the second chip 32 are electrically connected to the conductive pillar 60 through the metal wiring layer in the second wiring structure layer 20, and then electrically connected to the third chip 41 through the metal wiring layer in the first wiring structure layer 10, so that the first chip 31 and the second chip 32 can obtain data from the third chip 41.
[0036] In one embodiment, such as Figure 2 As shown, the first chip 31 is a data processing chip, the second chip 32 is an auxiliary support chip used only to balance the stress of the first chip layer, and the third chip 41 is a memory chip. The second chip 32 is not electrically connected to other film layers; it is only a silicon wafer that serves a supporting and stress-balancing function. The material of the second chip 32 is basically the same as that of the first chip 31, which makes the stress distribution and thermal expansion properties of the film layers containing the first chip 31 and the second chip 32 more balanced, preventing the film layer containing the first chip 30 from separating from other film layers and avoiding warping problems in semiconductor devices.
[0037] In one embodiment, the number of first chips 31 can be one or more, and the number of second chips 32 can be one or more.
[0038] In one embodiment, such as Figure 3 As shown, the conductive post 60 includes a first sub-conductive post 61, which is disposed between the first chip 31 and the second chip 32. The first chip 31 and the second chip 32 occupy a large area in the semiconductor device. When the first sub-conductive post 61 is disposed between the first chip 31 and the second chip 32, it can enhance the mechanical support performance between the chips and avoid stress concentration.
[0039] In one embodiment, when there are multiple first chips 31 and multiple second chips 32, the first sub-conductive post 61 can be disposed between adjacent first chips 31, between first chips 31 and second chips 32, or between second chips 32.
[0040] In one embodiment, such as Figure 4As shown, the conductive pillar also includes a second sub-conductive pillar 62, which is located on at least one side of the first layer chip 30 on opposite sides in the first direction X. The second sub-conductive pillar 62 is located at the edge of the chip and can form a rigid connection with the first wiring structure layer and the second wiring structure layer, absorbing local stress and suppressing the warping of the semiconductor device.
[0041] The second sub-conductive post 62 is located on at least one side of all the chips included in the first layer chip 30 in the first direction X, opposite to each other. For example... Figure 4 As shown, the first-layer chip 30 includes a first chip 31 and a second chip 32. The second sub-conductive post 62 is located on the side of the first chip 31 away from the second chip 32 and on the side of the second chip 32 away from the first chip 31. Figure 5 As shown, when the first layer chip 30 includes a first chip 31 and two second chips 32, the second sub-conductive post 62 is disposed on the side of the outermost second chip 32 away from the first chip 31.
[0042] In one embodiment, such as Figure 6 As shown, when the second chip 32 is an auxiliary support chip, the conductive post 60 includes a third sub-conductive post 63, which penetrates the second chip 32. This arrangement creates a mechanical connection between the third conductive posts 63 and the second chip 32, which helps improve the rigidity of the overall structure.
[0043] Since the second chip 32 only serves as a support and stress balancer, a through hole can be provided on the second chip 32 and a conductive material can be filled in the through hole to form a third sub-conductive pillar 63.
[0044] In one embodiment, such as Figure 6 As shown, the side of the second chip 32 facing away from the first chip 31 is flush with the side of the third chip 41 facing away from the heat sink 50. The edge of the third chip 41 away from the heat sink 50 is basically the same as the edge of the semiconductor device. When the side of the second chip 32 facing away from the first chip 31 is flush with the side of the third chip 41 facing away from the heat sink 50, the second chip 32 also extends to the edge of the semiconductor device, which can make the stress distribution at the edge of the semiconductor device more uniform, reduce the stress concentration at the side edge, and avoid cracking.
[0045] In other embodiments, such as Figure 2 As shown, the side of the second chip 32 that is away from the side of the first chip 31 can also be closer to the heat sink 50 than the side of the third chip 41 that is away from the side of the heat sink 50.
[0046] This application also provides an electronic device, which includes a circuit board and the aforementioned semiconductor device. The second wiring structure layer of the semiconductor device is disposed on the circuit board facing the circuit board and is electrically connected to the circuit in the circuit board. The first chip 31 can transmit data processing results to other functional modules of the electronic device through the circuit board.
[0047] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A semiconductor device, characterized in that, The semiconductor device includes: First wiring structure layer; The second wiring structure layer is disposed opposite to and spaced apart from the first wiring structure layer; A first layer chip is disposed between the first wiring structure layer and the second wiring structure layer; the first layer chip includes at least a first chip and a second chip spaced apart in a first direction, and at least the first chip is electrically connected to the second wiring structure layer. A heat sink is located on the side of the first wiring structure layer away from the first layer chip, and is used to dissipate heat from the first layer chip. The second layer chip includes a third chip, which is located on the side of the first wiring structure layer away from the second wiring structure layer and on the side of the heat sink, and is electrically connected to the first wiring structure layer; the orthographic projection of the second chip on the second wiring structure layer falls into the orthographic projection of the third chip on the second wiring structure layer, and the orthographic projection of the first chip on the second wiring structure layer and the orthographic projection of the third chip on the second wiring structure layer partially overlap; At least one conductive post is located between the first wiring structure layer and the second wiring structure layer for electrically connecting the first wiring structure layer and the second wiring structure layer.
2. The semiconductor device according to claim 1, characterized in that, The conductive pillar includes a first sub-conductive pillar, which is disposed between the first chip and the second chip.
3. The semiconductor device according to claim 1, characterized in that, The conductive pillar further includes a second sub-conductive pillar; the second sub-conductive pillar is located on at least one side of the first layer chip on opposite sides in a first direction.
4. The semiconductor device according to claim 1, characterized in that, The first chip is a data processing chip, the second chip is an auxiliary support chip used only to balance the stress of the first layer chip, and the third chip is a storage chip.
5. The semiconductor device according to claim 4, characterized in that, The conductive pillar includes a third sub-conductive pillar, which penetrates the second chip.
6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The heat sink and the third chip are arranged along a first direction, and the first chip is closer to the heat sink than the second chip.
7. The semiconductor device according to claim 6, characterized in that, The side of the second chip facing away from the first chip is flush with the side of the third chip facing away from the heat sink.
8. The semiconductor device according to claim 1, characterized in that, The orthographic projection of the heat sink on the second wiring structure layer overlaps with the orthographic projection of the first chip on the second wiring structure layer; And / or, the first wiring structure layer is provided with a metal wiring layer, and the orthographic projection of the metal wiring layer on the second wiring structure layer overlaps with the orthographic projection of the heat sink on the second wiring structure layer.
9. The semiconductor device according to claim 1, characterized in that, The first chip and the second chip are both data processing chips, and the third chip is a storage chip.
10. An electronic device, characterized in that, The electronic device includes a circuit board and a semiconductor device according to any one of claims 1 to 9; the second wiring structure layer of the semiconductor device is disposed on the circuit board facing the circuit board and is electrically connected to the circuit in the circuit board.