Semiconductor package structure

Abstract

The application discloses a semiconductor packaging structure, comprising: a first packaging layer, defining a capacitor region and a signal transmission region; and a capacitor structure, located in the capacitor region; and a conductive column, located in the signal transmission region; the capacitor structure and the conductive column each comprise a seed layer; and the seed layer of the capacitor structure and the seed layer of the conductive column are located on the same side. The above technical scheme of the application can at least reduce the cost.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure. Background Technology

[0002] Current advanced packaging platforms, such as FOPOP (Fan-out Stacked Package), FOCoS-Bridge (Fan-out Chip-on-Substrate Bridge), or FOPLP (Fan-out Panel-Level Package), all use DTC (Deep Trench Capacitor) to enhance product performance. See also Figure 1A and Figure 1B In the current FOCoS-Bridge structure 10, a DTC 20 is formed next to the bridge core 12. However, the existing DTC 20 has the following problems:

[0003] (1) High cost: The molding layer 30 uses liquid molding material, such as high-cost molding material MUF to protect the inserted DTC 20. Liquid molding material costs more than 5 times more than particulate molding material. In addition, the minimum height required to protect the high conductivity pillar 35 is 125μm, which affects the yield.

[0004] (2) Complex process: It adopts a double-sided process (one side of the mold sealing layer 30 covers the bridge tube core 12, and the other side of the mold sealing layer 50 covers the core 52), and uses MEOL (mid-range process) to prepare DTC 20, which is costly;

[0005] (3) Space occupied: Keep out zone (KOZ) requirement between DTC 20 and conductive post 35. Specifically, since DTC 20 is manufactured separately and then placed between conductive posts 35, a distance Dz must be maintained between DTC 20 and conductive post 35 to ensure that DTC 20 does not collide with conductive post 35. Utility Model Content

[0006] To address the above problems, this application proposes a semiconductor packaging structure that can at least reduce costs.

[0007] According to one aspect of this application, a semiconductor package structure is provided, comprising: a first package layer defining a capacitor region and a signal transmission region; a capacitor structure located within the capacitor region; and a conductive pillar located within the signal transmission region, wherein the capacitor structure and the conductive pillar each include a seed layer, and the seed layer of the capacitor structure and the seed layer of the conductive pillar are located on the same side.

[0008] In some embodiments, the capacitor structure includes electrode posts, a seed layer of the capacitor structure covers the sidewalls and bottom of the electrode posts, and a seed layer of the conductive posts covers the bottom of the conductive posts.

[0009] In some embodiments, the electrode post includes an inner electrode post and an outer electrode post, with the outer electrode post surrounding the inner electrode post in a top view.

[0010] In some embodiments, the capacitor structure further includes an insulating layer located between the inner electrode post and the outer electrode post, the insulating layer surrounding the inner electrode post.

[0011] In some embodiments, the semiconductor package structure further includes a first wiring layer located below the first package layer, and the seed layer of the capacitor structure and the seed layer of the conductive pillar are located on the side of the capacitor structure and the conductive pillar close to the first wiring layer, respectively.

[0012] In some embodiments, the semiconductor package structure further includes a first die disposed in a first package layer, wherein the spacing between the conductive pillar and the capacitor structure is smaller than the spacing between the first die and adjacent conductive pillars, or smaller than the spacing between adjacent capacitor structures.

[0013] In some embodiments, the dielectric constant of the insulating layer is greater than the dielectric constant of the first encapsulation layer.

[0014] In some embodiments, the electrode post includes a plurality of inner electrode posts and an outer electrode post, wherein the outer electrode post is a hollow rectangular column shape and, in a top view, the outer electrode post surrounds the plurality of inner electrode posts.

[0015] In some embodiments, the semiconductor package structure further includes a second wiring layer located above the first package layer, and a capacitor structure electrically connects the first wiring layer and the second wiring layer.

[0016] In some embodiments, the capacitor structure is located in a through-hole defined by the first encapsulation layer, and the capacitor structure is in physical contact with the first encapsulation layer.

[0017] In the above semiconductor packaging structure, since the deep trench capacitor (DTC) is replaced by a capacitor structure with a TMV structure that has a capacitive effect, the complex process used to prepare the DTC can be omitted, thus reducing costs and making the product more cost-competitive. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1A This is a cross-sectional schematic diagram of an existing semiconductor packaging structure.

[0020] Figure 1B yes Figure 1A A cross-sectional schematic diagram of the DTC in the diagram.

[0021] Figure 2A , Figure 3A , Figures 4 to 6 This is a cross-sectional schematic diagram of multiple stages in forming the semiconductor package structure according to embodiments of this application.

[0022] Figure 2B and Figure 3B They are Figure 2A and Figure 3A Top-view diagrams of areas A2 and A3 in the middle.

[0023] Figure 7A , Figure 8A , Figure 9 This is a cross-sectional schematic diagram of multiple stages at which a semiconductor package structure according to another embodiment of this application is formed.

[0024] Figure 7B and Figure 8B They are Figure 7A and Figure 8A Top-view diagrams of areas A2 and A3 in the middle.

[0025] Figure 10 This is a top view schematic diagram of a capacitor structure according to another embodiment of this application.

[0026] Figure 11A This is a cross-sectional schematic diagram of an intermediate stage in forming a capacitor structure according to another embodiment of this application.

[0027] Figure 11B yes Figure 11A A top-down view of area A3 in the central region.

[0028] Figure 12 This is a top view schematic diagram of a capacitor structure according to another embodiment of this application. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0030] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present invention. These are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the present invention. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0031] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0032] Figures 2A to 6 These are cross-sectional and top views showing various stages in forming the semiconductor package structure according to embodiments of this application. First, see... Figure 2A and Figure 2B As shown, a carrier 201 is provided, on which conductive lines 112 are formed, and a dielectric layer 114 is formed covering the conductive lines 112. The conductive lines 112 can be an RDL (rewiring layer). The dielectric layer 114 can be made of PI material. The conductive lines 112 and the dielectric layer 114 together form a first wiring layer 110. The first wiring layer 110 can be a redistribution layer (RDL).

[0033] Then, conductive pillars 120 are formed above the dielectric layer 114 and the conductive line 112. The conductive pillars 120 can be connected to the underlying conductive line 112. Furthermore, electrode pillars can be formed beside the conductive pillars 120; in this embodiment, the electrode pillars include inner electrode pillars 152 and outer electrode pillars 154. Figure 2B In the top view shown, the outer electrode post 154 surrounds the inner electrode post 152. The inner electrode post 152 and the outer electrode post 154 are used to form a capacitor structure. The inner electrode post 152 can be connected to the conductive line 112 below. In some embodiments, the conductive post 120 and the inner electrode post 152 and the outer electrode post 154 can be formed simultaneously by the same lithography process. The lithography process for forming the conductive post 120 and the inner electrode post 152 and the outer electrode post 154 may include steps such as coating, exposure, and development.

[0034] See Figure 3A and Figure 3BAs shown, a bridging die 132 is disposed on the dielectric layer 114. The bridging die 132 can be referred to as the first die. At this time, the active surface of the bridging die 132 and the connection terminal 133 on the active surface face upward. Then, a first encapsulation layer 130 is formed, which surrounds the conductive post 120, the bridging die 132, and the outer side of the external electrode post 154. In this embodiment, the first encapsulation layer 130 is a particulate molding material.

[0035] In addition, in this embodiment, the particulate molding material used for the first encapsulation layer 130 is also filled between the inner electrode post 152 and the outer electrode post 154 to form an insulating layer 157. That is, the insulating layer 157 is a particulate molding material. Then a polishing process can be performed to make the surfaces of the first encapsulation layer 130, the inner electrode post 152, the outer electrode post 154, the insulating layer 157, the conductive post 120, and the connecting terminal 133 flush with each other.

[0036] Thus, the capacitor structure 150 is formed by the internal electrode post 152, the external electrode post 154, and the insulating layer 157. Since the capacitor structure 150 passes through the first encapsulation layer 130, and can be located within a through-hole defined by the first encapsulation layer 130, the capacitor structure 150 can be referred to as a TMV (through mold via) with a capacitive effect. Furthermore, the capacitor structure 150 is in physical contact with the first encapsulation layer 130. And, since the capacitor structure 150 is composed of the internal electrode post 152, the external electrode post 154, and the insulating layer 157, it can also be referred to as a MIM (metal-insulator-metal) capacitor. The internal electrode post 152 and the external electrode post 154 can be used as the first electrode and the second electrode of the capacitor structure 150, respectively.

[0037] In this embodiment, the inner electrode post 152 is a cylinder, and the outer electrode post 154 is a hollow cylinder. The outer electrode post 154 surrounds the insulating layer 157, and the insulating layer 157 surrounds the inner electrode post 152. Figure 3B From the top-view perspective shown, the thickness of the external electrode post 154 is the same as the thickness of the insulating layer 157. In this embodiment, the material and dielectric constant of the insulating layer 157 of the capacitor structure 150 are the same as those of the first encapsulation layer 130. In other embodiments, the insulating layer 157 can also be formed independently of the first encapsulation layer 130; that is, an insulating layer 157 with any suitable dielectric constant can be formed using a different material than that of the first encapsulation layer 130.

[0038] See Figure 4A second wiring layer 220 is formed above the first encapsulation layer 130. The second wiring layer 220 may include conductive lines 222 and a dielectric layer 224 covering the conductive lines 222. The conductive lines 222 may be connected to the underlying conductive posts 120. The second wiring layer 220 may be a redistribution layer. In some embodiments, the conductive lines 222 may be electrically connected to the internal electrode posts 152 or the external electrode posts 154 of the underlying capacitor structure 150. In this embodiment, the capacitor structure 150 may be electrically connected to the first wiring layer 110 and the second wiring layer 220.

[0039] See Figure 5 A second die 240 is bonded above the second wiring layer 220. The second die 240 can be electrically connected to the underlying second wiring layer 220 via an electrical connector 241. An underfill 243 can be formed to cover and protect the electrical connector 241. A second encapsulation layer 230 is then formed, surrounding the second die 240 and the underfill 243.

[0040] See Figure 6 Carrier 201 (see) Figure 5 The traces are removed. Then, an electrical connector 113 is bonded below the first wiring layer 110. The electrical connector 113 can be electrically connected to the conductive lines 112 of the first wiring layer 110. The electrical connector 113 can be, for example, a solder ball. In this way, a semiconductor package structure 100 is formed.

[0041] In the semiconductor package structure 100, since the DTC capacitor structure is replaced by a capacitor structure 150 with a TMV structure having a capacitive effect, the complex process (such as MEOL process) used to prepare the DTC can be omitted; and there is no need to use high-cost liquid molding material to protect the DTC, but the first package layer 130 is formed by particulate molding material, thus reducing costs and making the product more cost-competitive, with cost-effectiveness improved by about 10 times.

[0042] Additionally, in the semiconductor package structure 100, the first package layer 130 may define a capacitor region Ac and a signal transmission region As. A capacitor structure 150 is located within the capacitor region Ac, and conductive posts 120 are located within the signal transmission region As. A bridging die 132 may also be located within the signal transmission region As. The conductive posts 120 within the signal transmission region As can be used to electrically connect the first wiring layer 110 and the second wiring layer 220 (which may be electrically connected to the second die 240) for signal transmission.

[0043] In some embodiments, the distance d1 between the conductive post 120 and the capacitor structure 150 is smaller than the distance d2 between the bridge core 132 and the adjacent conductive post 120. Alternatively, in some embodiments, the distance d1 between the conductive post 120 and the capacitor structure 150 may be smaller than the distance d3 between adjacent capacitor structures 150. In the embodiments of this application, since the capacitor structure 150 is not formed separately but simultaneously with the conductive post 120, it does not require the KOZ of the DTC structure, thus the distance d1 between the conductive post 120 and the capacitor structure 150 can be reduced, making d1 smaller than d2 or d3. In this way, the capacitor structure 150 can occupy less space, which is beneficial for product miniaturization.

[0044] Figures 7A to 9 These are cross-sectional and top views showing various stages in forming the semiconductor package structure according to embodiments of this application. See also... Figure 7A and Figure 7B As shown, similar to the above description, conductive pillars 120 are formed in the signal transmission region As, and internal electrode pillars 152 and external electrode pillars 154 are formed in the capacitance region Ac. In some embodiments, the conductive pillars 120, internal electrode pillars 152, and external electrode pillars 154 can be formed simultaneously using the same photolithography process. More specifically, the conductive pillars 120, the internal electrode pillars 152, and the external electrode pillars 154 of the capacitance structure each include a seed layer; the conductive pillar 120 includes a seed layer 120s, the internal electrode pillar 152 includes a seed layer 152s, and the external electrode pillar 154 includes a seed layer 154s.

[0045] Since the conductive pillar 120 is formed simultaneously with the internal electrode pillar 152 and the external electrode pillar 154 during this stage, the seed layer 152s of the internal electrode pillar 152, the seed layer 154s of the external electrode pillar 154, and the seed layer 120s of the conductive pillar 120 are located on the same side. In this embodiment, "located on the same side" means that the seed layer 152s is located on the side of the internal electrode pillar 152 closest to the first wiring layer 110, the seed layer 154s is located on the side of the external electrode pillar 154 closest to the first wiring layer 110, and the seed layer 120s is located on the side of the conductive pillar 120 closest to the first wiring layer 110.

[0046] More specifically, the seed layer 120s of the conductive post 120 may only cover the bottom of the conductive post 120. The seed layer 152s of the inner electrode post 152 covers the sidewalls and bottom of the inner electrode post 152, and the seed layer 154s of the outer electrode post 154 covers the sidewalls and bottom of the outer electrode post 154.

[0047] See Figure 8A and Figure 8B As shown, in accordance with the above references Figure 3A and Figure 3BSimilarly, a bridging core 132 is disposed above the first wiring layer 110 in the signal transmission area As. Then, a first encapsulation layer 130 is formed. In some embodiments, the first encapsulation layer 130 is a particulate molding material. Furthermore, the material of the first encapsulation layer 130 is also filled between the inner electrode post 152 and the outer electrode post 154 to form an insulating layer 157.

[0048] See Figure 9 , and the above reference Figure 4 Similarly, a second wiring layer 220 is formed above the first encapsulation layer 130. In this embodiment, the second wiring layer 220 may include an electrical transmission region and a blanking region 229, the electrical transmission region being the area of ​​the second wiring layer 220 excluding the blanking region 229. No conductive lines 222 of the second wiring layer 220 contact the capacitor structure 150 in the blanking region 229. In this embodiment, the blanking region 229 is located at the level of the second wiring layer 220 closest to the capacitor structure 150. In other embodiments, the blanking region 229 may include various levels of the second wiring layer 220 above the capacitor structure 150. The dielectric layer of the second wiring layer 220 contacts the capacitor structure. In such an embodiment, the capacitor structure 150 is not electrically connected to the second wiring layer 220. The capacitor structure 150 is electrically connected to the first wiring layer 110 via internal electrode posts 152.

[0049] Figures 7A to 9 Other aspects of the illustrated embodiments can be found in the above references. Figures 2A to 6 Similar descriptions are given and will not be repeated here. And... Figure 9 After the stages shown, you can refer to the above. Figures 5 to 6 The described method is used for subsequent processes to form the final semiconductor package structure.

[0050] Figure 10 A top view schematic diagram of a capacitor structure according to another embodiment of this application is shown. See also Figure 10 As shown, in some embodiments, the electrode posts of the capacitor structure 150 include a plurality of inner electrode posts 152 and an outer electrode post 154. The outer electrode post 154 is a hollow rectangular column, and in a top view, the outer electrode post 154 surrounds the plurality of spaced-apart inner electrode posts 152. Each inner electrode post 152 can be rectangular. The plurality of inner electrode posts 152 can be arranged in at least one row and at least one column within the outer electrode post 154. Figure 10 In the example, the multiple internal electrode posts 152 are arranged in 2 rows and 4 columns. In this embodiment, the material of the insulating layer 157 of the capacitor structure 150 can be the same as the material of the first encapsulation layer 130.

[0051] Figure 11A This is a cross-sectional schematic diagram of an intermediate stage in forming a capacitor structure according to another embodiment of this application. Figure 11B yes Figure 11A A top-down view of area A3 in the central region. Figure 11A and Figure 11B Several aspects of the illustrated embodiments can be compared with Figure 10 The embodiments shown are the same or similar. Figure 11A and Figure 11B The difference in the illustrated embodiment is that, in this embodiment, the material of the insulating layer 157 of the capacitor structure 150 can be different from the material of the first encapsulation layer 130. Specifically, an appropriate material for the insulating layer 157 can be selected according to the design requirements of the capacitor structure 150. In some embodiments, the dielectric constant of the insulating layer 157 can be greater than the dielectric constant of the first encapsulation layer 130.

[0052] Figure 12 A top view schematic diagram of a capacitor structure according to another embodiment of this application is shown. See also Figure 12 As shown, in some embodiments, the electrode posts of the capacitor structure 150 may include a first electrode post 152' and a second electrode post 154'. The first electrode post 152' and the second electrode post 154' are arranged opposite to each other and together form a finger-like capacitor structure. The plurality of finger-like portions 152p of the first electrode post 152' and the plurality of finger-like portions 154p of the second electrode post 154' are arranged alternately. In some embodiments, the width of the finger-like portions 154p is different from the width of the finger-like portions 152p; for example, the width of the finger-like portions 154p is greater than the width of the finger-like portions 152p.

[0053] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor packaging structure, characterized in that, include: The first encapsulation layer defines a capacitor area and a signal transmission area; as well as The capacitor structure is located within the capacitor region. A conductive pillar is located within the signal transmission area. Both the capacitor structure and the conductive pillar contain a seed layer, and the seed layer of the capacitor structure and the seed layer of the conductive pillar are located on the same side.

2. The semiconductor packaging structure according to claim 1, characterized in that, The capacitor structure includes electrode pillars, a seed layer of the capacitor structure covers the sidewalls and bottom of the electrode pillars, and a seed layer of the conductive pillar covers the bottom of the conductive pillar.

3. The semiconductor packaging structure according to claim 2, characterized in that, The electrode post includes an inner electrode post and an outer electrode post, with the outer electrode post surrounding the inner electrode post in a top-down view.

4. The semiconductor packaging structure according to claim 3, characterized in that, The capacitor structure further includes an insulating layer located between the inner electrode post and the outer electrode post, the insulating layer surrounding the inner electrode post.

5. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: The first wiring layer is located below the first encapsulation layer, and the seed layer of the capacitor structure and the seed layer of the conductive pillar are respectively located on the side of the capacitor structure and the conductive pillar close to the first wiring layer.

6. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: The first die is disposed within the first encapsulation layer. The distance between the conductive post and the capacitor structure is less than the distance between the first die and the adjacent conductive post, or less than the distance between the adjacent capacitor structures.

7. The semiconductor packaging structure according to claim 4, characterized in that, The dielectric constant of the insulating layer is greater than that of the first encapsulation layer.

8. The semiconductor packaging structure according to claim 2, characterized in that, The electrode post includes multiple inner electrode posts and an outer electrode post. The outer electrode post is a hollow rectangular column and surrounds the multiple inner electrode posts when viewed from above.

9. The semiconductor packaging structure according to claim 5, characterized in that, Also includes: The second wiring layer is located above the first encapsulation layer. The capacitor structure is electrically connected to the first wiring layer and the second wiring layer.

10. The semiconductor packaging structure according to claim 1, characterized in that, The capacitor structure is located in the through-hole defined by the first encapsulation layer, and the capacitor structure is in physical contact with the first encapsulation layer.

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