Mim capacitors

Abstract

The utility model provides a kind of MIM capacitor.The MIM capacitor includes first electrode layer, second electrode layer and insulating dielectric layer, second electrode layer is located on first electrode layer, and second electrode layer has second opening, insulating dielectric layer is between first electrode layer and second electrode layer, and the side wall of insulating dielectric layer laterally beyond second opening, extend to the first electrode layer corresponding to the position of second opening covered by second opening, so it can improve the problem that insulating dielectric layer is easily undercut to form undercut (undercut) and produce leakage weakness in wet cleaning process after forming second opening, that is, it can reduce the number of leakage weakness of MIM capacitor, improve the leakage problem of MIM capacitor, and improve the stability of MIM capacitor.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a MIM capacitor. Background Technology

[0002] Capacitors are commonly used passive electronic devices in integrated circuits, typically including metal-oxide-semiconductor (MODS) capacitors, polysilicon-insulator-polysilicon (PSI) capacitors, and metal-insulator-metal (MIM) capacitors. Among these, MIM capacitors are widely used due to their advantages such as low parasitic capacitance, low contact resistance, and relatively accurate capacitance values. However, existing MIM capacitors suffer from significant leakage problems and require further optimization. Utility Model Content

[0003] One of the objectives of this invention is to provide a MIM capacitor that can improve the leakage problem of MIM capacitors and enhance their stability.

[0004] To achieve the above objectives, this utility model provides a MIM capacitor. The MIM capacitor includes: a first electrode layer; a second electrode layer located on the first electrode layer, and having a second opening therein; and an insulating dielectric layer located between the first electrode layer and the second electrode layer, extending laterally beyond the sidewall of the second opening, into the second opening, and covering the first electrode layer corresponding to the location of the second opening.

[0005] Optionally, the insulating dielectric layer covers the sidewall of the first electrode layer, and the boundary of the second electrode layer extends laterally beyond the boundary of the first electrode layer located below the second electrode layer.

[0006] Optionally, for two adjacent electrode layers, the boundary of the lower electrode layer extends beyond the boundary of the upper electrode layer.

[0007] Optionally, the insulating dielectric layer is a multilayer structure composed of layers of different materials stacked together.

[0008] Optionally, the insulating dielectric layer includes a first zirconium oxide layer, an aluminum oxide layer, and a second zirconium oxide layer stacked sequentially from bottom to top on the first electrode layer.

[0009] Optionally, the MIM capacitor includes two or more first electrode layers and at least one second electrode layer located on a semiconductor substrate. The first electrode layers and the second electrode layers are alternately arranged in the thickness direction of the semiconductor substrate, and an insulating dielectric layer is disposed between adjacent first electrode layers and second electrode layers.

[0010] Optionally, each of the first electrode layers has a first opening, and the insulating dielectric layer located below and in contact with the first electrode layer extends laterally beyond the sidewall of the first opening, into the first opening, and covers the second electrode layer corresponding to the position of the first opening; each of the second electrode layers has a second opening, and the insulating dielectric layer located below and in contact with the second electrode layer extends laterally beyond the sidewall of the second opening, into the second opening, and covers the first electrode layer corresponding to the position of the second opening.

[0011] Optionally, the MIM capacitor further includes: a first pad and a second pad located on a semiconductor substrate; an interlayer dielectric layer located on the semiconductor substrate and on the first pad and the second pad, covering a portion of the surface of the first pad and a portion of the surface of the second pad; a first RV hole penetrating the first electrode layer and the insulating dielectric layer and contacting the first pad at its bottom, with the sidewall of the first RV hole in contact with the first electrode layer; and a second RV hole penetrating the second electrode layer and the insulating dielectric layer and contacting the second pad at its bottom, with the sidewall of the second RV hole in contact with the second electrode layer.

[0012] Optionally, the first electrode layer has a first opening, the first opening corresponding to the position of the first pad, and the insulating dielectric layer above the first opening fills the first opening; the second opening corresponds to the position of the second pad.

[0013] Optionally, the interlayer dielectric layer includes a silicon nitride layer located on the first pad and the second pad, and a silicon oxide layer located on the silicon nitride layer.

[0014] In the MIM capacitor provided by this utility model, the second electrode layer is located on the first electrode layer, and the second electrode layer has a second opening. The insulating dielectric layer is located between the first electrode layer and the second electrode layer, and the insulating dielectric layer extends laterally beyond the sidewall of the second opening, extends into the second opening, and covers the first electrode layer corresponding to the position of the second opening. That is, when etching the second electrode layer to form the second opening, the etching stops on the insulating dielectric layer below it. This can improve the problem that the insulating dielectric layer below the opening of the electrode layer is easily undercut during the wet cleaning process after the opening is formed, resulting in leakage weakness. In other words, it can reduce the leakage weakness area of ​​the MIM capacitor, thereby improving the leakage problem of the MIM capacitor and enhancing the stability of the MIM capacitor. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of a MIM capacitor.

[0016] Figure 2 This is a schematic diagram showing a partial detail of a MIM capacitor.

[0017] Figure 3 This is a schematic diagram of the structure of a MIM capacitor provided in an embodiment of the present invention.

[0018] Figure 4 This is a schematic diagram of the structure of a MIM capacitor including three or more electrode layers, provided as an embodiment of the present invention.

[0019] Figure 5 This is a schematic diagram of the structure of a MIM capacitor provided in another embodiment of the present invention.

[0020] Figure 6 A partial TEM image of a MIM capacitor provided in an embodiment of this utility model.

[0021] Explanation of reference numerals in the attached figures: 11-First electrode layer; 11a-First opening; 12-Second electrode layer; 12a-Second opening; 13-Insulating dielectric layer; 131-First zirconium oxide layer; 132-Alumina layer; 133-Second zirconium oxide layer; 141-Silicon nitride layer; 142-Silicon oxide layer; 151-First pad; 152-Second pad; 161-First RV hole; 162-Second RV hole. Detailed Implementation

[0022] Figure 1 This is a schematic diagram of a MIM capacitor. (Reference) Figure 1 As shown, electrochemical analysis (EFA) revealed that the openings and edges of the first electrode layer 11 and the second electrode layer 12 of the MIM capacitor are leakage weakpoint regions. Figure 1 The area indicated by the dashed box is the area with weak leakage current.

[0023] Figure 2 This is a schematic diagram showing a partial detail of a MIM capacitor. (Example) Figure 2 As shown, the insulating dielectric layer 13 between the first electrode layer 11 and the second electrode layer 12 has a ZAZ structure, that is, the insulating dielectric layer 13 includes a first zirconium oxide layer (ZrO2) 131, an aluminum oxide layer (Al2O3) 132, and a second zirconium oxide layer 133 sequentially stacked on the first electrode layer 11, and the second electrode layer 12 has a second opening 12a. Further research revealed that the electrode layer is formed by patterning the electrode material layer. During the patterning process of forming the second electrode layer 12, such as... Figure 2As shown, if the electrode material layer is etched through to form the second opening 12a, and then the insulating oxide layer 13 is etched through, the insulating oxide layer 13 will easily be undercut from the sidewall of the insulating oxide layer 13 below the second opening 12a during the subsequent wet (WET) cleaning process (i.e., the alumina layer 132 in the ZAZ structure will be lost during acidic WET cleaning, forming a lateral pit). This undercut is difficult to fill laterally, resulting in a hole. The hole has extremely poor breakdown resistance, and the breakdown probability of the upper and lower zirconium oxide layers increases sharply at this point. Thus, the undercut becomes a leak. electricity This creates a weak area and negatively impacts RE (Radiated Emission) testing, affecting the stability of the capacitor.

[0024] To address this, this application provides a MIM capacitor in which a second electrode layer is located on the first electrode layer and has a second opening. An insulating dielectric layer is located between the first electrode layer and the second electrode layer, and the insulating dielectric layer extends laterally beyond the sidewall of the second opening, into the second opening, and covers the first electrode layer corresponding to the location of the second opening. That is, when etching the second electrode layer to form the second opening, the etching stops on the insulating dielectric layer below it. This can improve the problem that the insulating dielectric layer below the opening of the electrode layer is easily undercut during the wet cleaning process after the opening is formed, resulting in leakage current weakness. In other words, it can reduce the leakage current weakness area of ​​the MIM capacitor, thereby improving the leakage current problem of the MIM capacitor and enhancing its stability.

[0025] The MIM capacitor proposed in this utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this utility model.

[0026] It should be noted that this application uses terms such as "first" and "second" to describe various elements, components, areas, layers, and / or parts. These elements, components, areas, layers, and / or parts should not be limited by these terms; they are merely used to distinguish one element, component, area, layer, or part from another. Therefore, without departing from the teachings of this utility model, the first element, component, area, layer, or part discussed below can be represented as the second element, component, area, layer, or part. In this application, unless otherwise expressly defined and specified, "above" or "below" a second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "on top of," and "over" a second feature are used to describe that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "below" a second feature are used to describe that the first feature is at a lower horizontal level than the second feature.

[0027] Figure 3 This is a schematic diagram of the structure of a MIM capacitor provided in an embodiment of the present invention. Figure 3 As shown, the MIM capacitor includes a first electrode layer 11, a second electrode layer 12, and an insulating dielectric layer 13. The second electrode layer 12 is located on the first electrode layer 11 and has a second opening 12a. The insulating dielectric layer 13 is located between the first electrode layer 11 and the second electrode layer 12, and the insulating dielectric layer 13 extends laterally beyond the sidewall of the second opening 12a, into the second opening 12a, and covers the first electrode layer 11 corresponding to the position of the second opening 12a.

[0028] For example, the materials of the first electrode layer 11 and the second electrode layer 12 include, but are not limited to, TiN. The thicknesses of the first electrode layer 11 and the second electrode layer 12 may be greater than or equal to 200 Å and less than or equal to 600 Å, but are not limited thereto.

[0029] In this embodiment, the insulating dielectric layer 13 can be a multilayer structure composed of layers of different materials. Specifically, the insulating dielectric layer 13 may include a first zirconium oxide layer 131, an aluminum oxide layer 132, and a second zirconium oxide layer 133 stacked sequentially from bottom to top on the first electrode layer 11, i.e., the insulating dielectric layer 13 has a ZAZ structure. The zirconium oxide layer has a relatively high dielectric constant, typically in the range of 20-25, which is much higher than that of traditional silicon oxide and silicon nitride, and also significantly higher than that of aluminum oxide, resulting in a relatively high breakdown field strength. Using the zirconium oxide layer as the insulating material between electrodes in a MIM capacitor can achieve high capacitance density. Aluminum oxide has the advantages of excellent insulation performance and low leakage current. Therefore, the insulating dielectric layer 13 of this application includes a first zirconium oxide layer 131, an aluminum oxide layer 132, and a second zirconium oxide layer 133 stacked sequentially from bottom to top. On the one hand, this can enable the MIM capacitor to have a high capacitance density, and on the other hand, it can reduce the leakage current of the MIM capacitor, thereby improving the reliability and stability of the MIM capacitor.

[0030] For example, the total thickness of the insulating dielectric layer 13 can be greater than or equal to 50 Å and less than or equal to 100 Å, such as 69 Å, but is not limited thereto. The specific thicknesses of the first zirconium oxide layer 131, the aluminum oxide layer 132, and the second zirconium oxide layer 133 in the insulating dielectric layer 13, as well as the thickness ratio between them, can be set as needed.

[0031] It should be noted that this application forms the electrode layer and openings in the electrode layer by etching (i.e., patterning) the electrode material layer. During the etching process to form the second electrode layer 12 with the second opening 12a, the etching stops on the insulating dielectric layer 13 (specifically, on the second zirconia layer 133). This causes the insulating dielectric layer 13 to laterally extend beyond the sidewall of the second opening 12a, into the second opening 12a, and cover the first electrode layer 11 corresponding to the location of the second opening 12a. The second opening 12a does not expose the alumina layer 132 inside the insulating dielectric layer 13. After the patterning process for forming the second electrode layer 12 is completed, a wet cleaning process is needed to remove the byproducts generated from etching the electrode material layer. During this wet cleaning process, since the second zirconia layer 133 under the electrode layer opening is not etched through, the second zirconia layer 133 can protect the alumina layer 132, thereby avoiding the problem of the alumina layer 132 being undercut during the wet cleaning process. Figure 6 As shown in the TEM image, the ZAZ structure of the insulating dielectric layer 13 under the second opening 12a is complete, which reduces the leakage weak area of ​​the MIM capacitor and improves the leakage problem of the MIM capacitor.

[0032] For example, both the first electrode layer 11 and the second electrode layer 12 can be formed by patterning the electrode material layer formed using a physical vapor deposition (PVD) process. For example, the electrode material layer can be patterned using a dry etching process; the gas used in the dry etching process may include Cl2 and / or CH4; during dry etching, the etching selectivity ratio of the electrode material layer to the insulating dielectric layer 13 (specifically, the zirconium oxide in the insulating dielectric layer 13) can be greater than 20:1, that is, the insulating dielectric layer 13 needs to be used as the etching stop layer of the electrode material layer.

[0033] Continue to refer to Figure 3 As shown, although Figure 3 Only one first electrode layer 11 and one second electrode layer 12 are shown, but in this application, a MIM capacitor may include two or more first electrode layers and at least one second electrode layer located on a semiconductor substrate. Figure 4 A schematic diagram of a MIM capacitor comprising three or more electrode layers, provided as an embodiment of this utility model. (Reference) Figure 4 As shown, the first electrode layer 11 and the second electrode layer 12 are alternately disposed in the thickness direction of the semiconductor substrate, and an insulating dielectric layer 13 is disposed between adjacent first electrode layers 11 and second electrode layers 12, that is, in the direction from bottom to top on the semiconductor substrate ( Figure 4 The electrode layer and insulating dielectric layer 13 in the Y direction are arranged in the order of first electrode layer 11, insulating dielectric layer 13, second electrode layer 12, insulating dielectric layer 13, first electrode layer 11... This can form an interdigitated MIM capacitor to increase the capacitance value.

[0034] For MIM capacitors with three or more electrode layers, each first electrode layer 11 may have a first opening 11a. The insulating dielectric layer 13 located below and in contact with the first electrode layer 11 extends laterally beyond the sidewall of the first opening 11a, into the first opening 11a, and covers the second electrode layer 12 corresponding to the position of the first opening 11a. Each second electrode layer 12 may have a second opening 12a. The insulating dielectric layer 13 located below and in contact with the second electrode layer 12 extends laterally beyond the sidewall of the second opening 12a, into the second opening 12a, and covers the first electrode layer 11 corresponding to the position of the second opening 12a.

[0035] It should be noted that the bottom first electrode layer 11 (i.e. the first electrode layer 11 closest to the semiconductor substrate) also has a first opening 11a. Below the first opening 11a is the interlayer dielectric layer under the electrode layer. The purpose of setting the first opening 11a in the first electrode layer 11 is to prevent the first electrode layer 11 from being connected to the RV hole connecting the second electrode layer 12. The purpose of setting the second opening 12a in the second electrode layer 12 is to prevent the second electrode layer 12 from being connected to the RV hole connecting the first electrode layer 11. That is, the purpose of setting the first opening 11a and the second opening 12a is to prevent the first electrode layer 11 and the second electrode layer 12 from being short-circuited.

[0036] For details, please refer to Figure 3 and Figure 4 As shown, the MIM capacitor may further include: a first pad 151, a second pad 152, an interlayer dielectric layer, a first RV hole 161, and a second RV hole 162.

[0037] The first pad 151 and the second pad 152 are located on the semiconductor substrate. The first pad 151 and the second pad 152 can be two pads on the same metal layer on the semiconductor substrate. The materials of the first pad 151 and the second pad 152 include, but are not limited to, copper.

[0038] An interlayer dielectric layer is located on the semiconductor substrate and on the first pad 151 and the second pad 152. The interlayer dielectric layer may cover a portion of the surface of the first pad 151 and a portion of the surface of the second pad 152. In this embodiment, the interlayer dielectric layer may be a multilayer structure comprising layers of different materials stacked together. For example, Figure 3 and Figure 4 As shown, the interlayer dielectric layer includes a silicon nitride layer 141 and a silicon oxide layer 142 located on the silicon nitride layer 141. The interlayer dielectric layer composed of the silicon nitride layer 141 and the silicon oxide layer 142 can improve the isolation effect of the interlayer dielectric layer, and the silicon nitride layer 141 can also serve as an etch stop layer for the silicon oxide layer 142 to protect the first pad 151 and the second pad 152, etc. The thickness of the silicon nitride layer 141 can be greater than or equal to 500 Å and less than or equal to 1100 Å, for example, 500 Å or 700 Å; the thickness of the silicon oxide layer 142 can be greater than or equal to 2000 Å and less than or equal to 5000 Å, for example, 2000 Å or 3000 Å, but is not limited thereto.

[0039] The first opening 11a in the first electrode layer 11 can correspond to the position of the first pad 151, and the insulating dielectric layer 13 located above the first opening 11a fills the first opening 11a; the second opening 12a in the second electrode layer 12 can correspond to the position of the second pad 152.

[0040] A first RV via (Redistribution Via) 161 penetrates the first electrode layer 11 and the insulating dielectric layer 13, and its bottom contacts the first pad 151. The sidewall of the first RV via 161 is in contact with the first electrode layer 11, meaning that the first electrode layer 11 and the first pad 151 are electrically connected through the first RV via 161 and are led out through the first RV via 161. The first RV via 161 also passes through a second opening 12a above the first pad 151, and the width of the second opening 12a is greater than the width of the first RV via 161 located within the second opening 12a, to prevent the first RV via 161 from being electrically connected to the second electrode layer 12.

[0041] The second RV hole 162 penetrates the second electrode layer 12 and the insulating dielectric layer 13, and its bottom contacts the second pad 152. The sidewall of the second RV hole 162 is in contact with the second electrode layer 12, that is, the second electrode layer 12 and the second pad 152 are electrically connected through the second RV hole 162 and are led out through the second RV hole 162. The second RV hole 162 also passes through the first opening 11a above the second pad 152, and the width of the first opening 11a is greater than the width of the second RV hole 162 located within the first opening 11a, so as to avoid the second RV hole 162 being electrically connected to the first electrode layer 11.

[0042] For example, the materials of the first RV hole 161 and the second RV hole 162 include, but are not limited to, aluminum. The widths of the first opening 11a and the second opening 12a (i.e., Figure 4 The dimension in the X direction can be greater than or equal to 4.8µm, but is not limited to this.

[0043] The cross-section of the first RV hole 161 and the second RV hole 162 perpendicular to the semiconductor substrate can be an inverted trapezoid, which facilitates the filling of conductive material to form the first RV hole 161 and the second RV hole 162. When the first pad 151 has multiple stacked second openings 12a, the width of the upper second opening 12a can be greater than the width of the lower second opening 12a, which can effectively prevent the second electrode layer 12 from contacting the first RV hole 161; when the second pad 152 has multiple stacked first openings 11a, the width of the upper first opening 11a can be greater than the width of the lower first opening 11a, which can effectively prevent the first electrode layer 11 from contacting the second RV hole 162, but is not limited to this.

[0044] The first RV hole 161 and the second RV hole 162, perpendicular to the cross-section of the semiconductor substrate, can also be rectangular, etc. The widths of all first openings 11a can also be equal, or the width of the upper first opening 11a can be smaller than the width of the lower first opening 11a, as long as the sidewalls of the first openings do not contact the RV holes within them; the widths of all second openings 12a can also be equal, or the width of the upper second opening 12a can be smaller than the width of the lower second opening 12a, as long as the sidewalls of the second openings do not contact the RV holes within them.

[0045] In some embodiments of this application, for two adjacent electrode layers (the electrode layers are collectively referred to as the first electrode layer 11 and the second electrode layer 12), the boundary of the lower electrode layer extends beyond the boundary of the upper electrode layer, for example, referring to... Figure 4 As shown, the boundary of the first electrode layer 11 at the bottom extends beyond the boundary of the second electrode layer 12 located above it, and the boundary of the second electrode layer 12 extends beyond the boundary of the first electrode layer 11 located above the second electrode layer 12. This design conforms to the design rules, that is, it does not need to challenge the design rules.

[0046] In other embodiments of this application, for two adjacent electrode layers, the boundary of the upper electrode layer extends beyond the boundary of the lower electrode layer. This avoids leakage problems caused by undercut at the electrode layer junction and helps to further improve the leakage problem of MIM capacitors. However, such a design requires challenging design rules. Figure 5 This is a schematic diagram of the structure of a MIM capacitor provided in another embodiment of the present invention. For example, refer to... Figure 5 As shown, the boundary of the second electrode layer 12 extends laterally beyond the boundary of the first electrode layer 11 located below the second electrode layer 12.

[0047] It should be noted that, as Figure 3 , Figure 4 and Figure 5 As shown, the insulating dielectric layer 13 covers the sidewall of the electrode layer located thereunder.

[0048] In the MIM capacitor provided by this utility model, the second electrode layer 12 is located on the first electrode layer 11, and the second electrode layer 12 has a second opening 12a. The insulating dielectric layer 13 is located between the first electrode layer 11 and the second electrode layer 12, and the insulating dielectric layer 13 extends laterally beyond the sidewall of the second opening 12a, extends into the second opening 12a, and covers the first electrode layer 11 corresponding to the position of the second opening 12a. That is, when etching the second electrode layer 12 to form the second opening 12a, the etching stops on the insulating dielectric layer 13 below it. This can improve the problem that the insulating dielectric layer 13 below the opening of the electrode layer is easily undercut during the wet cleaning process after the opening is formed, resulting in a leakage weak area. In other words, it can reduce the leakage weak area of ​​the MIM capacitor, thereby improving the leakage problem of the MIM capacitor and improving the stability of the MIM capacitor.

[0049] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model. Any person skilled in the art can make possible changes and modifications to the technical solution of the present utility model by using the methods and techniques disclosed above without departing from the spirit and scope of the present utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present utility model without departing from the content of the technical solution of the present utility model shall fall within the protection scope of the technical solution of the present utility model.

Claims

1. A MIM capacitor, characterized in that, include: First electrode layer; A second electrode layer is located on top of the first electrode layer, and the second electrode layer has a second opening. as well as An insulating dielectric layer is located between the first electrode layer and the second electrode layer, and extends laterally beyond the sidewall of the second opening, into the second opening, and covers the first electrode layer corresponding to the location of the second opening.

2. The MIM capacitor as described in claim 1, characterized in that, The insulating dielectric layer covers the sidewall of the first electrode layer, and the boundary of the second electrode layer extends laterally beyond the boundary of the first electrode layer located below the second electrode layer.

3. The MIM capacitor as described in claim 1, characterized in that, For two adjacent electrode layers, the boundary of the lower electrode layer extends beyond the boundary of the upper electrode layer.

4. The MIM capacitor as described in claim 1, characterized in that, The insulating dielectric layer is a multilayer structure consisting of stacked layers of different materials.

5. The MIM capacitor as described in claim 4, characterized in that, The insulating dielectric layer comprises a first zirconium oxide layer, an aluminum oxide layer, and a second zirconium oxide layer, which are stacked sequentially from bottom to top on the first electrode layer.

6. The MIM capacitor as described in claim 1, characterized in that, The MIM capacitor includes two or more first electrode layers and at least one second electrode layer located on a semiconductor substrate. The first electrode layers and the second electrode layers are alternately arranged in the thickness direction of the semiconductor substrate, and an insulating dielectric layer is disposed between adjacent first electrode layers and second electrode layers.

7. The MIM capacitor as described in claim 6, characterized in that, Each of the first electrode layers has a first opening, and the insulating dielectric layer located below and in contact with the first electrode layer extends laterally beyond the sidewall of the first opening, into the first opening, and covers the second electrode layer corresponding to the position of the first opening; each of the second electrode layers has a second opening, and the insulating dielectric layer located below and in contact with the second electrode layer extends laterally beyond the sidewall of the second opening, into the second opening, and covers the first electrode layer corresponding to the position of the second opening.

8. The MIM capacitor as described in claim 1, 6, or 7, characterized in that, The MIM capacitor also includes: The first and second pads are located on the semiconductor substrate; An interlayer dielectric layer is located on the semiconductor substrate and on the first pad and the second pad, covering a portion of the surface of the first pad and a portion of the surface of the second pad; A first RV hole penetrates the first electrode layer and the insulating dielectric layer, and its bottom contacts the first pad; the sidewall of the first RV hole is in contact with the first electrode layer. The second RV hole penetrates the second electrode layer and the insulating dielectric layer and its bottom contacts the second pad. The sidewall of the second RV hole is in contact with the second electrode layer.

9. The MIM capacitor as described in claim 8, characterized in that, The first electrode layer has a first opening, which corresponds to the position of the first pad, and the insulating dielectric layer located above the first opening fills the first opening; the second opening corresponds to the position of the second pad.

10. The MIM capacitor as described in claim 8, characterized in that, The interlayer dielectric layer includes a silicon nitride layer located on the first pad and the second pad, and a silicon oxide layer located on the silicon nitride layer.

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