Layout structure of a power module

Abstract

The application provides a layout structure of a power module, which comprises an insulating substrate, a first conductive film on the surface of the insulating substrate, a plurality of upper bridge chips arranged in an array on the first conductive film, a second conductive film on the surface of the insulating substrate, the source of the upper bridge chips in the same column being connected to the second conductive film through a source bonding wire parallel to the length direction of the insulating substrate, a third conductive film on the surface of the insulating substrate, a plurality of lower bridge chips arranged in an array on the third conductive film, and a fourth conductive film on the surface of the insulating substrate, the source of the lower bridge chips in the same column being connected to the fourth conductive film through a source bonding wire parallel to the length direction of the insulating substrate. The application provides a layout structure of a power module, which can improve the electric heating performance of the power module.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductors, and in particular to a layout structure of a power module. Background

[0002] Electric vehicles pursue ultra-fast charging, low loss and high cruising range, and widely adopt silicon carbide power modules (hereinafter referred to as power modules) as the core components for power conversion. Especially in the main drive of electric vehicles, the electrothermal performance of the power module directly affects the final performance of the entire vehicle.

[0003] Therefore, it is necessary to provide a more effective and reliable technical solution to improve the electrothermal performance of the power module. Contents of the Utility Model

[0004] The present application provides a layout structure of a power module, which can improve the electrothermal performance of the power module.

[0005] The present application provides a layout structure of a power module, comprising: an insulating substrate; a first conductive film located on the surface of the insulating substrate, where a plurality of upper bridge chips distributed in an array are formed on the first conductive film; a second conductive film located on the surface of the insulating substrate, wherein the sources of the upper bridge chips in the same column are connected to the second conductive film through source bonding wires parallel to the length direction of the insulating substrate; a third conductive film located on the surface of the insulating substrate, where a plurality of lower bridge chips distributed in an array are formed on the third conductive film; a fourth conductive film located on the surface of the insulating substrate, wherein the sources of the lower bridge chips in the same column are connected to the fourth conductive film through source bonding wires parallel to the length direction of the insulating substrate.

[0006] In some embodiments of the present application, the sources of the upper bridge chips in the same column are connected to the second conductive film through the source bonding wires parallel to the length direction of the insulating substrate, and are also connected to the third conductive film at the same time.

[0007] In some embodiments of the present application, the layout structure further comprises: an upper bridge source conductive film, an upper bridge source located on the upper bridge source conductive film, and an upper bridge source conductor located between the plurality of upper bridge chips, wherein the sources of the plurality of upper bridge chips are respectively connected to the upper bridge source conductor through bonding wires, and the upper bridge source conductor is connected to the upper bridge source conductive film through bonding wires and is in electrical communication with the upper bridge source.

[0008] In some embodiments of the present application, the upper bridge source conductor is in a shape of a Chinese character "ji", and two side edges of the "ji" shape are connected through upper bridge bonding wires.

[0009] In some embodiments of this application, the layout structure further includes: an upper bridge gate conductive film, an upper bridge gate located on the upper bridge gate conductive film, and an upper bridge gate conductor located between the plurality of upper bridge chips. The gates of the plurality of upper bridge chips are respectively connected to the upper bridge gate conductor through bonding wires. The upper bridge gate conductor is connected to the upper bridge gate conductive film through bonding wires and is electrically connected to the upper bridge gate.

[0010] In some embodiments of this application, the layout structure further includes: a lower bridge source conductor and a lower bridge source located on the lower bridge source conductor, wherein the sources of the plurality of lower bridge chips are respectively connected to the lower bridge source conductor and electrically connected to the lower bridge source via bonding wires.

[0011] In some embodiments of this application, the number of the lower bridge source conductors is two and they are axially symmetrically distributed, and the two lower bridge source conductors are connected by a lower bridge bonding wire.

[0012] In some embodiments of this application, the layout structure further includes: a lower bridge gate conductor and a lower bridge gate located on the lower bridge gate conductor, wherein the gates of the plurality of lower bridge chips are respectively connected to the lower bridge gate conductor and electrically connected to the lower bridge gate via bonding wires.

[0013] In some embodiments of this application, the drains of the plurality of upper bridge chips are interconnected through the first conductive film, and the drains of the plurality of lower bridge chips are interconnected through the third conductive film.

[0014] In some embodiments of this application, the main body of the first conductive film is "H" shaped, the second conductive film is located above the crossbeam of the "H" shape, and the third and fourth conductive films are located below the crossbeam of the "H" shape in sequence.

[0015] This application provides a layout structure for a power module that can increase the chip spacing without changing the size of the insulating substrate, effectively reduce the thermal coupling effect between chips, reduce the thermal resistance of the module, and effectively improve the current output capability of the module. The symmetrical Kelvin source connection method can improve the current sharing between chips, reduce switching losses, and is also more friendly to external signal measurement. Attached Figure Description

[0016] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0017] Figure 1 This is a schematic diagram of the layout structure of the power module described in the embodiment of this application. Detailed Implementation

[0018] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0019] The technical solution of this utility model will be described in detail below with reference to the embodiments and accompanying drawings.

[0020] Figure 1 This is a schematic diagram of the layout structure of the power module according to an embodiment of this application. The layout structure of the power module according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0021] This application provides a layout structure for a power module, with reference to... Figure 1 As shown, the system includes: an insulating substrate 100; a first conductive film 110 located on the surface of the insulating substrate 100, on which a plurality of upper bridge chips 111 arranged in an array are formed; a second conductive film 120 located on the surface of the insulating substrate 100, on which the sources of the upper bridge chips 111 in the same column are connected to the second conductive film 120 through source bonding lines 112 parallel to the length direction of the insulating substrate 100; a third conductive film 130 located on the surface of the insulating substrate 100, on which a plurality of lower bridge chips 131 arranged in an array are formed; and a fourth conductive film 140 located on the surface of the insulating substrate 100, on which the sources of the lower bridge chips 131 in the same column are connected to the fourth conductive film 140 through source bonding lines 132 parallel to the length direction of the insulating substrate 100.

[0022] In some embodiments of this application, the insulating substrate 100 may be any insulating substrate conventional in the art. The insulating substrate 100 is rectangular and has a length direction, a width direction, and a central axis extending along the length direction.

[0023] In some embodiments of the present application, the main body of the first conductive thin film 110 is in an "H" shape, the plurality of upper bridge chips 111 are located at the crossbeam position of the "H" shape and are symmetrical about the central axis, the second conductive thin film 120 is located above the crossbeam of the "H" shape, and the third conductive thin film 130 and the fourth conductive thin film 140 are sequentially located below the crossbeam of the "H" shape.

[0024] In some embodiments of the present application, the sources of the upper bridge chips 111 in the same column are connected to the second conductive thin film 120 and also to the third conductive thin film 130 through source bonding wires 112 parallel to the length direction of the insulating substrate 100.

[0025] In the technical solution of the present application, the source bonding wire 112 and the source bonding wire 132 extend along the length direction of the insulating substrate 100, which can fully utilize the space in the length direction of the insulating substrate 100 and save the space in the width direction. Then the distance between the chips in the width direction can be increased, the chip spacing is increased without changing the size of the insulating substrate, the thermal coupling effect between the chips is effectively reduced, the thermal resistance of the module is reduced, and the current output capability of the module is effectively improved.

[0026] With further reference to Figure 1 as shown, in some embodiments of the present application, the drains of the plurality of upper bridge chips 111 are interconnected through the first conductive thin film 110, and the drains of the plurality of lower bridge chips 131 are interconnected through the third conductive thin film 130.

[0027] In some embodiments of the present application, the number of the upper bridge chips 111 and the lower bridge chips 131 is at least two, for example, four, six, etc. The present application does not limit the specific number.

[0028] With further reference to Figure 1 as shown, in some embodiments of the present application, the layout structure further includes: an upper bridge source conductive thin film 113, an upper bridge source 114 located on the upper bridge source conductive thin film 113, and an upper bridge source conductor 115 located between the plurality of upper bridge chips 111. The sources of the plurality of upper bridge chips 111 are respectively connected to the upper bridge source conductor 115 through bonding wires, and the upper bridge source conductor 115 is connected to the upper bridge source conductive thin film 113 through bonding wires and is in electrical communication with the upper bridge source 114.

[0029] In some embodiments of the present application, the upper bridge source conductor 115 is in a shape of the Chinese character "几", and two side edges of the "几" shape are connected through upper bridge bonding wires 119. The upper bridge bonding wires 119 connect the symmetrical upper bridge source conductors 115 to improve the current sharing effect.

[0030] Reference to Figure 1As shown, in the technical solution of this application, the plurality of upper bridge chips 111 are symmetrical about the axis of symmetry, and the upper bridge source conductor 115 is also symmetrical about the axis of symmetry. The connection structure of the plurality of upper bridge chips 111 and the upper bridge source conductor 115 is a symmetrical Kelvin source connection method, which can improve the current sharing between chips, reduce switching losses, and is also more friendly to external signal measurement.

[0031] Continue to refer to Figure 1 As shown, in some embodiments of this application, the layout structure further includes: an upper bridge gate conductive film 116, an upper bridge gate 117 located on the upper bridge gate conductive film 116, and an upper bridge gate conductor 118 located between the plurality of upper bridge chips 111. The gates of the plurality of upper bridge chips 111 are respectively connected to the upper bridge gate conductor 118 through bonding wires. The upper bridge gate conductor 118 is connected to the upper bridge gate conductive film 116 through bonding wires and is electrically connected to the upper bridge gate 117.

[0032] Continue to refer to Figure 1 As shown, in some embodiments of this application, the layout structure further includes: a lower bridge source conductor 133 and a lower bridge source 134 located on the lower bridge source conductor 133, wherein the sources of the plurality of lower bridge chips 131 are respectively connected to the lower bridge source conductor 133 and electrically connected to the lower bridge source 134 via bonding wires.

[0033] In some embodiments of this application, the number of the lower bridge source conductors 133 is two and they are axially symmetrically distributed. The two lower bridge source conductors 133 are connected by a lower bridge bonding wire 139.

[0034] refer to Figure 1 As shown, in the technical solution of this application, the plurality of lower-bridge chips 131 are symmetrical about the axis of symmetry, and the lower-bridge source conductor 133 is also symmetrical about the axis of symmetry. The connection structure between the plurality of lower-bridge chips 131 and the lower-bridge source conductor 133 is a symmetrical Kelvin source connection method, which can improve the current sharing between chips, reduce switching losses, and is also more user-friendly for external signal measurement.

[0035] Continue to refer to Figure 1 As shown, in some embodiments of this application, the layout structure further includes: a lower bridge gate conductor 135 and a lower bridge gate 136 located on the lower bridge gate conductor 135, wherein the gates of the plurality of lower bridge chips 131 are respectively connected to the lower bridge gate conductor 135 and electrically connected to the lower bridge gate 136 via bonding wires.

[0036] This application provides a layout structure for a power module that increases chip spacing without changing the size of the insulating substrate, effectively reducing thermal coupling between chips, decreasing the module's thermal resistance, and significantly improving the module's current output capability. Simulation tests by the applicant show that this layout structure reduces the highest and lowest junction temperatures by 15°C, lowers the thermal resistance by 16.7%, and increases the module's current output capability by 8% under the same heat dissipation and loss conditions. This application also employs a symmetrical Kelvin source connection method, which improves current sharing between chips, reduces switching losses, and is more compatible with external signal measurements.

[0037] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0038] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0039] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0040] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0041] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A layout structure for a power module, characterized in that, comprising: an insulating substrate; a first conductive thin film, disposed on the surface of the insulating substrate, wherein a plurality of upper bridge chips distributed in an array are formed on the first conductive thin film; a second conductive thin film, disposed on the surface of the insulating substrate, wherein the sources of the upper bridge chips in the same column are connected to the second conductive thin film through source bonding wires parallel to the length direction of the insulating substrate; a third conductive thin film, disposed on the surface of the insulating substrate, wherein a plurality of lower bridge chips distributed in an array are formed on the third conductive thin film; a fourth conductive thin film, disposed on the surface of the insulating substrate, wherein the sources of the lower bridge chips in the same column are connected to the fourth conductive thin film through source bonding wires parallel to the length direction of the insulating substrate.

2. The layout structure of the power module as described in claim 1, characterized in that, The sources of the upper bridge chips in the same column are connected to the second conductive thin film through the source bonding wires parallel to the length direction of the insulating substrate, and are also connected to the third conductive thin film at the same time.

3. The layout structure of the power module as described in claim 1, characterized in that, further comprising: an upper bridge source conductive thin film, an upper bridge source disposed on the upper bridge source conductive thin film, and upper bridge source conductors disposed between the plurality of upper bridge chips, wherein the sources of the plurality of upper bridge chips are respectively connected to the upper bridge source conductors through bonding wires, and the upper bridge source conductors are connected to the upper bridge source conductive thin film through bonding wires and electrically communicate with the upper bridge source.

4. The layout structure of the power module as described in claim 3, characterized in that, The upper bridge source conductor is shaped like a Chinese character "几", and two sides of the "几" shape are connected through upper bridge bonding wires.

5. The layout structure of the power module as described in claim 1, characterized in that, further comprising: an upper bridge gate conductive thin film, an upper bridge gate disposed on the upper bridge gate conductive thin film, and upper bridge gate conductors disposed between the plurality of upper bridge chips, wherein the gates of the plurality of upper bridge chips are respectively connected to the upper bridge gate conductors through bonding wires, and the upper bridge gate conductors are connected to the upper bridge gate conductive thin film through bonding wires and electrically communicate with the upper bridge gate.

6. The layout structure of the power module as described in claim 1, characterized in that, further comprising: lower bridge source conductors and lower bridge sources disposed on the lower bridge source conductors, wherein the sources of the plurality of lower bridge chips are respectively connected to the lower bridge source conductors through bonding wires and electrically communicate with the lower bridge sources.

7. The layout structure of the power module as described in claim 6, characterized in that, The number of the lower bridge source conductors is two and they are distributed in axial symmetry, and the two lower bridge source conductors are connected through lower bridge bonding wires.

8. The layout structure of the power module as described in claim 1, characterized in that, further comprising: lower bridge gate conductors and lower bridge gates disposed on the lower bridge gate conductors, wherein the gates of the plurality of lower bridge chips are respectively connected to the lower bridge gate conductors through bonding wires and electrically communicate with the lower bridge gates.

9. The layout structure of the power module as described in claim 1, characterized in that, The drains of the plurality of upper bridge chips are interconnected through the first conductive thin film, and the drains of the plurality of lower bridge chips are interconnected through the third conductive thin film.

10. The layout structure of the power module as described in claim 1, characterized in that, The main body of the first conductive thin film is H-shaped, the second conductive thin film is located above the cross beam of the H shape, and the third conductive thin film and the fourth conductive thin film are sequentially located below the cross beam of the H shape.

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