A packaging structure, system-on-chip and electronic device
Patent Information
- Application Number
- CN202522029848.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-19
- Publication Date
- 2026-10-23
- Estimated Expiration
- 2035-09-19
AI Technical Summary
而由于不同功能的芯片对于布线层数的需求不同，如功耗相对较低的芯片(比如存储芯片)，其所需的布线层数相对较少，这类功能相对较低的芯片在与功耗相对较高的芯片(比如数据处理芯片)集成在同一布线基板时，容易造成功耗相对较低的芯片所对应连接的布线区域的布线层浪费
[0025]与相关技术相比，本申请所提供的封装结构，通过将基板设置为包括不同的第一基板区域和第二基板区域，所述基板具有电路结构，所述电路结构包括位于所述第一基板区域的第一电路结构和位于所述第二基板区域的第二电路结构；所述第一电路结构和所述第二电路结构均包括多层布线层；所述第一基板区域的基板厚度大于所述第二基板区域的基板厚度，且所述第一电路结构所包括的布线层的层数大于所述第二电路结构所包括的布线层的层数，使得不同芯片可根据需要设置于不同的基板区域，有利于提高布线层的利用率，有利于降低布线基板以及封装结构的成本。
Smart Images
Figure CN224891095U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a packaging structure, a system integrated chip, and an electronic device. Background Technology
[0002] With the continuous development of semiconductor technology, some packaging structures are designed to integrate chips with different functions (such as data processing chips and memory chips), and these chips with different functions are electrically led out or interconnected through the same wiring substrate. In related technologies, the thickness and number of wiring layers of the same wiring substrate are consistent in all regions. However, because chips with different functions have different requirements for the number of wiring layers, such as chips with relatively low power consumption (such as memory chips), which require relatively fewer wiring layers, when these chips with relatively low power consumption are integrated with chips with relatively high power consumption (such as data processing chips) on the same wiring substrate, it is easy to cause waste of wiring layers in the wiring areas corresponding to the relatively low power consumption chips. Utility Model Content
[0003] This application discloses a packaging structure, the packaging structure comprising:
[0004] A substrate has a first substrate region and a second substrate region connected together. The substrate has a circuit structure, which includes a first circuit structure located in the first substrate region and a second circuit structure located in the second substrate region. Both the first circuit structure and the second circuit structure include multiple wiring layers. The substrate thickness of the first substrate region is greater than the substrate thickness of the second substrate region, and the number of wiring layers included in the first circuit structure is greater than the number of wiring layers included in the second circuit structure.
[0005] The first chip is disposed in the first substrate region of the substrate and is electrically connected to the first circuit structure;
[0006] The second chip is disposed in the second substrate region of the substrate and electrically connected to the second circuit structure, and the first chip and the second chip are located on the same side of the substrate.
[0007] In some embodiments, the first substrate region has a first surface and a second surface that are opposite to each other, and the second substrate region has a third surface and a fourth surface that are opposite to each other; the first surface and the third surface are located on the same side of the substrate, and the second surface and the fourth surface are located on the same side of the substrate; the first chip is disposed on the first surface of the first substrate region, and the second chip is disposed on the third surface of the second substrate region;
[0008] Wherein, the second surface and the fourth surface are flush, and there is a height difference between the first surface and the third surface; or, the first surface and the third surface are flush, and there is a height difference between the second surface and the fourth surface.
[0009] In some embodiments, the packaging structure further includes:
[0010] The first decoupling device is disposed on the surface of the first substrate region on the side opposite to the first chip.
[0011] A second decoupling device is disposed in the second substrate region; when the second surface and the fourth surface are flush, and there is a height difference between the first surface and the third surface, the second decoupling device is disposed on the third surface; when the first surface and the third surface are flush, and there is a height difference between the second surface and the fourth surface, the second decoupling device is disposed on the fourth surface.
[0012] In some embodiments, both the first decoupling device and the second decoupling device are decoupling capacitors.
[0013] In some embodiments, the packaging structure further includes:
[0014] A first molding compound is located on the side of the substrate close to the first chip and the second chip, and at least covers the periphery of the first chip;
[0015] Multiple solder balls are disposed on the surface of the substrate opposite to the first chip and the second chip, and are at least electrically connected to the first circuit structure.
[0016] In some embodiments, when the first surface and the third surface are flush, and there is a height difference between the second surface and the fourth surface, the first substrate region of the substrate has a connecting side surface connecting the second surface and the third surface, and the connecting side surface forms a notch with the fourth surface; the packaging structure further includes:
[0017] The second encapsulation fills the gap.
[0018] In some embodiments, the first circuit structure is electrically connected to the second circuit structure;
[0019] When the second surface and the fourth surface are flush, a plurality of solder balls are disposed on the second surface of the first substrate region and the fourth surface of the second substrate region; a portion of the plurality of solder balls is electrically connected to the first circuit structure and another portion is electrically connected to the second circuit structure.
[0020] When the first surface and the third surface are flush, and there is a height difference between the second surface and the fourth surface, the plurality of solder balls are only disposed on the second surface of the first substrate region, and the plurality of solder balls are only electrically connected to the first circuit structure.
[0021] In some embodiments, the first circuit structure includes five or more wiring layers; the second circuit structure includes two or three wiring layers.
[0022] In some embodiments, the first chip is a data processing chip, and the second chip is a storage chip.
[0023] This application also provides a system integrated chip, which includes the packaging structure described above.
[0024] This application also provides an electronic device, which includes a circuit board and a packaging structure as described above. The substrate of the packaging structure faces the circuit board from the side opposite to the first chip and the second chip, and is electrically connected to the circuit in the circuit board.
[0025] Compared with related technologies, the packaging structure provided in this application, by setting the substrate to include different first substrate regions and second substrate regions, and the substrate having a circuit structure, the circuit structure includes a first circuit structure located in the first substrate region and a second circuit structure located in the second substrate region; both the first circuit structure and the second circuit structure include multiple wiring layers; the substrate thickness of the first substrate region is greater than the substrate thickness of the second substrate region, and the number of wiring layers included in the first circuit structure is greater than the number of wiring layers included in the second circuit structure, so that different chips can be set in different substrate regions as needed, which is beneficial to improving the utilization rate of wiring layers and reducing the cost of wiring substrate and packaging structure.
[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description
[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.
[0028] Figure 1 This is a cross-sectional view of an encapsulation structure according to an embodiment of this application;
[0029] Figure 2 This is a cross-sectional view of another packaging structure in one embodiment of this application;
[0030] Figure 3This is a cross-sectional view of yet another packaging structure in an embodiment of this application;
[0031] Figure 4 This is a cross-sectional view of another packaging structure in one embodiment of this application. Detailed Implementation
[0032] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.
[0033] If the embodiments of this application contain terms relating to directional indications or positional relationships (e.g., up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture; if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance. Connections in this application can refer to mechanical connections, electrical connections, or signal connections, etc.
[0034] This application discloses a packaging structure, a system integrated chip, and an electronic device. The packaging structure includes a substrate, a first chip, and a second chip. The substrate has a first substrate region and a second substrate region connected together. The substrate has a circuit structure, including a first circuit structure located in the first substrate region and a second circuit structure located in the second substrate region. Both the first and second circuit structures include multiple wiring layers. The substrate thickness of the first substrate region is greater than that of the second substrate region, and the number of wiring layers in the first circuit structure is greater than the number of wiring layers in the second circuit structure. The first chip is disposed in the first substrate region of the substrate and electrically connected to the first circuit structure. The second chip is disposed in the second substrate region of the substrate and electrically connected to the second circuit structure, and the first and second chips are located on the same side of the substrate. In this packaging structure, different chips can be disposed in different substrate regions as needed, which is beneficial for improving the utilization rate of the wiring layers and reducing the cost of the wiring substrate and the packaging structure.
[0035] The following is in conjunction with the appendix Figures 1 to 4 The above-described packaging structure is described in detail. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0036] Please refer to Figure 1 This application provides a packaging structure 100. The packaging structure 100 includes a substrate 10, a first chip 20, and a second chip 30.
[0037] The substrate 10 has a first substrate region 11 and a second substrate region 12 connected together. The substrate 10 has a circuit structure 101 and a dielectric layer 102 covering the circuit structure 101.
[0038] The circuit structure 101 includes a first circuit structure 1001 located in the first substrate region 11 and a second circuit structure 1002 located in the second substrate region 12. Both the first circuit structure 1001 and the second circuit structure 1002 include multiple wiring layers 1011 and conductive pillars 1012 connecting each adjacent pair of wiring layers 1011. The substrate thickness T1 of the first substrate region 11 is greater than the substrate thickness T2 of the second substrate region 12. Furthermore, the number of wiring layers 1011 included in the first circuit structure 1001 is greater than the number of wiring layers 1011 included in the second circuit structure 1002.
[0039] The first substrate region 11 and the second substrate region 12 can be arranged in the W direction, and the packaging structure 100 has a thickness direction T. The W direction can be perpendicular to the thickness direction T or have other non-zero included angles. The substrate thickness T1 of the first substrate region 11 and the substrate thickness T2 of the second substrate region 12 can both be understood as the dimensions in the thickness direction of the packaging structure 100.
[0040] The circuit structure 101 can be exposed on the surface of the substrate 10 to be electrically connected to the first chip 20 and the second chip 30.
[0041] The first circuit structure 1001 can be electrically connected to the second circuit structure 1002.
[0042] The dielectric layer 102 may be made of a dielectric material. The dielectric material may be polyimide (PI), benzocyclobutene (BCB), epoxy resin, or other suitable dielectric materials.
[0043] It is understood that the substrate 10 is a single integrated structure. A portion of the wiring layers 1011 of the first circuit structure 1001 corresponds one-to-one with the wiring layers 1011 of the second circuit structure 1002. The corresponding wiring layers 1011 in the first circuit structure 1001 and the second circuit structure 1002 are arranged on the same layer (i.e., synchronously). The other wiring layers 1011 of the first circuit structure 1001 are arranged separately and are not synchronously arranged with the wiring layers 1011 of the second circuit structure 1002.
[0044] The first chip 20 is disposed in the first substrate region 11 of the substrate 10 and is electrically connected to the first circuit structure 1001.
[0045] like Figure 1 As shown, the first circuit structure 1001 is exposed on the surface of the first substrate region 11 near the first chip 20. The surface of the first chip 20 facing the substrate 10 is an active surface, and this active surface is provided with an electrical connection bond 201. The first chip 20 is connected to the exposed portion of the first circuit structure 1001 through the electrical connection bond 201 to realize the electrical connection between the first chip 20 and the first circuit structure 1001.
[0046] The second chip 30 is disposed in the second substrate region 12 of the substrate 10 and is electrically connected to the second circuit structure 1002. The first chip 20 and the second chip 30 are located on the same side of the substrate 10.
[0047] like Figure 1 As shown, the second circuit structure 1002 is exposed from the surface of the second substrate region 12 near the second chip 30. The surface of the second chip 30 facing the substrate 10 is an active surface, which is provided with electrical connection bonds (not shown). The second circuit structure 1002 is exposed from the surface of the second substrate region 12 near the second chip 30. The second circuit structure 1002 can be electrically connected to the electrical connection bonds of the active surface of the second chip 30 via solder balls 40.
[0048] In some embodiments, the height of the solder ball 40 is greater than the height of the electrical connection key 201.
[0049] In some embodiments, the thickness of the second chip 30 is greater than the thickness of the second chip 20.
[0050] like Figure 1 As shown, in some embodiments, the first substrate region 11 has a first surface 111 and a second surface 112 that are opposite to each other, and the second substrate region 12 has a third surface 121 and a fourth surface 122 that are opposite to each other; the first surface 111 and the third surface 121 are located on the same side of the substrate 10, and the second surface 112 and the fourth surface 122 are located on the same side of the substrate 10; the first chip 20 is disposed on the first surface 111 of the first substrate region 11, and the second chip 30 is disposed on the third surface 121 of the second substrate region 12.
[0051] The second surface 112 and the fourth surface 122 are flush, and there is a height difference between the first surface 111 and the third surface 121.
[0052] With this configuration, compared to using a substrate of the same thickness, using this substrate 10 not only saves costs but also helps control the thickness of the packaging structure 100.
[0053] In some embodiments, the packaging structure 100 further includes a first decoupling device 51.
[0054] The first decoupling device 51 is disposed on the surface of the first substrate region 11 opposite to the first chip 20. That is, the first decoupling device 51 is disposed on the second surface 112.
[0055] In some embodiments, the packaging structure 100 further includes a second decoupling device 52. The second decoupling device 52 is disposed in the second substrate region 12.
[0056] like Figure 1 As shown, the second decoupling device 52 can be disposed on the third surface 121, which is more conducive to decoupling the circuit structure of the first substrate region 11 and the second substrate region 12.
[0057] In some embodiments, the first decoupling device 51 and the second decoupling device 52 are both decoupling capacitors.
[0058] The arrangement of the first decoupling device 51 and the second decoupling device 52 helps to ensure the power integrity of the first chip 20.
[0059] In some embodiments, the encapsulation structure 100 further includes a first molding compound 61.
[0060] The first molding compound 61 is located on the side of the substrate 10 close to the first chip 20 and the second chip 30, and covers the periphery of the first chip 20.
[0061] The surface 202 of the first chip 20 away from the first substrate region 11 exposes the first molding compound 61.
[0062] It is understandable that the surface 202 of the first chip 20 that is away from the first substrate region 11 can also be covered by the first molding compound 61.
[0063] The first molding compound 61 may be made of epoxy molding compound (EMC).
[0064] In some embodiments, the package structure 100 further includes a plurality of solder balls 70.
[0065] like Figure 1 As shown, a plurality of solder balls 70 are disposed on the side surface of the substrate 10 away from the first chip 20 and the second chip 30, and are electrically connected to the first circuit structure 1001 and the second circuit structure 1002.
[0066] Solder ball 70 can be a tin-containing solder ball, such as a tin-lead alloy solder ball, a tin-silver alloy solder ball, or a tin-silver alloy solder ball.
[0067] In some embodiments, the wiring layers 1011 included in the first circuit structure 1001 are greater than or equal to five layers, such as five or six layers. The wiring layers 1011 included in the second circuit structure 1002 are two or three layers.
[0068] for example Figure 1 As shown, the first circuit structure 1001 includes five wiring layers 1011. The second circuit structure 1002 includes two wiring layers 1011.
[0069] In some embodiments, the first chip 20 is a data processing chip, and the second chip 30 is a storage chip.
[0070] The first chip 20 may be a system-on-a-chip (SoC). For example, the first chip 20 may be a system-on-a-chip (SoC) that includes at least one of a central processing unit (CPU) and a graphics processing unit (GPU).
[0071] like Figure 1 As shown, in some embodiments, the packaging structure 100 further includes an underfill adhesive 80. The underfill adhesive 80 fills at least the area between the first chip 30 and the wiring substrate 10, excluding the electrical connection bond 201.
[0072] like Figure 2 As shown, this application also provides a packaging structure 200. The packaging structure 200 is substantially the same as the packaging structure 100, and the similarities or similarities can be referred to the above-described related features. The difference is that in the packaging structure 200, the first molding compound 61 covers the periphery of the first chip 20, and also covers the periphery of the second chip 30 and the gap between the second chip 30 and the second substrate region 12 of the substrate 10.
[0073] The surface 301 of the second chip 30 on the side opposite to the second substrate region 12 can be exposed from the first molding compound 61.
[0074] In other embodiments, the surface 301 of the second chip 30 facing away from the second substrate region 12 may also be covered by the first molding compound 61.
[0075] like Figure 3As shown, this application also provides a packaging structure 300. Packaging structure 300 is substantially the same as packaging structure 100; similarities or identical features can be found in the above description. The difference is that in packaging structure 300, the first surface 111 and the third surface 121 are flush, and there is a height difference between the second surface 112 and the fourth surface 122. The second decoupling device 52 is disposed on the fourth surface 122. The first substrate region 11 of the substrate 10 has a connecting side surface 113 connecting the second surface 112 and the third surface 121, and the connecting side surface 113 forms a notch with the fourth surface 122; the packaging structure also includes a second molding compound 62. The second molding compound 62 fills the notch.
[0076] The material of the second molding compound 62 can be the same as that of the first molding compound 61, and they can be formed in the same process.
[0077] Accordingly, the plurality of solder balls 70 are disposed only on the second surface 112 of the first substrate region 11, and the plurality of solder balls 70 are electrically connected only to the first circuit structure 1001.
[0078] Figure 4 As shown, this application also provides a packaging structure 400. The packaging structure 400 is substantially the same as the packaging structure 300, and the similarities or similarities can be referred to the above-described related features. The difference is that in the packaging structure 400, the first molding compound 61 covers the periphery of the first chip 20, and also covers the periphery of the second chip 30 and the gap between the second chip 30 and the second substrate region 12 of the substrate 10.
[0079] It should be noted that at least one surface of the first substrate region 11 and the second substrate region 12 is flush. It is understood that in some other embodiments, the surfaces of the first substrate region 11 and the second substrate region 12 on the same side may not be flush, that is, notches are formed on both opposite surfaces of the second substrate region 12.
[0080] This application also provides a system integrated circuit (SOC) chip, which includes the package structure 100, package structure 200, package structure 300 or package structure 400 as described above.
[0081] This application also provides an electronic device. The electronic device includes a circuit board and a package structure 100, package structure 200, package structure 300 or package structure 400 as described above. The substrate 10 of the package structure 100, package structure 200, package structure 300 or package structure 400 faces the circuit board from the side opposite to the first chip 20 and the second chip 30, and is electrically connected to the circuit in the circuit board.
[0082] The first chip 20 can transmit the data processing results to other functional modules of the electronic device via a circuit board.
[0083] The electronic device can be a mobile phone, a tablet, or other electronic products.
[0084] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.
[0085] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.
Claims
1. A packaging structure, characterized in that, The packaging structure includes: A substrate has a first substrate region and a second substrate region connected together. The substrate has a circuit structure, which includes a first circuit structure located in the first substrate region and a second circuit structure located in the second substrate region. Both the first circuit structure and the second circuit structure include multiple wiring layers. The substrate thickness of the first substrate region is greater than the substrate thickness of the second substrate region, and the number of wiring layers included in the first circuit structure is greater than the number of wiring layers included in the second circuit structure. The first chip is disposed in the first substrate region of the substrate and is electrically connected to the first circuit structure; The second chip is disposed in the second substrate region of the substrate and electrically connected to the second circuit structure, and the first chip and the second chip are located on the same side of the substrate.
2. The packaging structure as described in claim 1, characterized in that, The first substrate region has a first surface and a second surface that are opposite to each other, and the second substrate region has a third surface and a fourth surface that are opposite to each other; the first surface and the third surface are located on the same side of the substrate, and the second surface and the fourth surface are located on the same side of the substrate; the first chip is disposed on the first surface of the first substrate region, and the second chip is disposed on the third surface of the second substrate region. Wherein, the second surface and the fourth surface are flush, and there is a height difference between the first surface and the third surface; or, the first surface and the third surface are flush, and there is a height difference between the second surface and the fourth surface.
3. The packaging structure as described in claim 2, characterized in that, The packaging structure further includes: The first decoupling device is disposed on the surface of the first substrate region on the side opposite to the first chip. A second decoupling device is disposed in the second substrate region; when the second surface and the fourth surface are flush, and there is a height difference between the first surface and the third surface, the second decoupling device is disposed on the third surface; when the first surface and the third surface are flush, and there is a height difference between the second surface and the fourth surface, the second decoupling device is disposed on the fourth surface.
4. The packaging structure as described in claim 3, characterized in that, Both the first decoupling device and the second decoupling device are decoupling capacitors.
5. The packaging structure as described in claim 2, characterized in that, The packaging structure further includes: A first molding compound is located on the side of the substrate close to the first chip and the second chip, and at least covers the periphery of the first chip; Multiple solder balls are disposed on the surface of the substrate opposite to the first chip and the second chip, and are at least electrically connected to the first circuit structure.
6. The packaging structure as described in claim 5, characterized in that, When the first surface and the third surface are flush, and there is a height difference between the second surface and the fourth surface, the first substrate region of the substrate has a connecting side surface that connects the second surface and the third surface, and the connecting side surface forms a notch with the fourth surface; The packaging structure further includes: The second encapsulation fills the gap.
7. The packaging structure as described in claim 6, characterized in that, The first circuit structure is electrically connected to the second circuit structure; When the second surface and the fourth surface are flush, a plurality of solder balls are disposed on the second surface of the first substrate region and the fourth surface of the second substrate region. A portion of the plurality of solder balls is electrically connected to the first circuit structure, and another portion is electrically connected to the second circuit structure; When the first surface and the third surface are flush, and there is a height difference between the second surface and the fourth surface, the plurality of solder balls are only disposed on the second surface of the first substrate region, and the plurality of solder balls are only electrically connected to the first circuit structure.
8. The packaging structure as described in claim 1, characterized in that, The first circuit structure includes five or more wiring layers; the second circuit structure includes two or three wiring layers.
9. The packaging structure as described in claim 1, characterized in that, The first chip is a data processing chip, and the second chip is a storage chip.
10. A system-integrated chip, characterized in that, Includes the packaging structure as described in any one of claims 1 to 9.
11. An electronic device, characterized in that, The electronic device includes a circuit board and a packaging structure as described in any one of claims 1 to 9, wherein the substrate of the packaging structure faces away from the first chip and the second chip and is electrically connected to the circuitry in the circuit board.