A fan-out package structure

Abstract

The utility model discloses a fan-out type packaging structure, include: wafer, circuit layer one, circuit layer two, copper column, capacitor, cavity structure G, plastic package body, the first surface of wafer is provided with circuit layer one, and the second surface of wafer is provided with circuit layer two, and the first surface of wafer is provided with cavity structure G. The utility model belongs to fan-out type packaging structure field, and specifically refers to a kind of fan-out type packaging structure and manufacturing method;The utility model solves the problem that crystal surface is often covered by PI or molding material.

Description

Technical Field

[0001] This utility model belongs to the technical field of fan-out packaging structure and manufacturing method, specifically referring to a fan-out packaging structure. Background Technology

[0002] In the semiconductor packaging field, with the ever-increasing demands for performance, size, and reliability in electronic products, fan-out packaging technology has been widely adopted due to its ability to achieve high-density interconnection and miniaturization of chips. However, traditional fan-out packaging structures and manufacturing methods have some problems that affect chip performance and the electrical performance of the packaging structure.

[0003] On the one hand, during the packaging process, the crystal surface is often covered with PI (polyimide) or molding (plastic) materials. For products requiring acoustic wave conduction, these materials can interfere with the chip's reception of acoustic waves, leading to poor acoustic signal transmission and reducing chip performance and reliability. On the other hand, during circuit rewiring, the accuracy of photolithography and the deposition and filling processes of metal layers can affect the circuit's conductivity and signal transmission efficiency. Traditional methods have shortcomings in these aspects and cannot meet the high precision and high reliability requirements of electronic products.

[0004] Furthermore, as electronic products evolve towards miniaturization and higher performance, higher demands are placed on the stability and electrical performance of fan-out packaging structures. Existing packaging structures still need improvement in terms of the stability of electrical connections and the accuracy of signal transmission.

[0005] This utility model discloses a fan-out packaging structure and manufacturing method, which exposes the crystal surface to avoid the influence of other materials on the chip's acoustic wave reception. At the same time, it precisely controls the photolithography and metal layer manufacturing process, improves the circuit's conductivity and signal transmission efficiency, and meets the needs of electronic products for high-performance packaging. Utility Model Content

[0006] In order to overcome the shortcomings of the prior art, this utility model provides a fan-out packaging structure, which effectively solves the problem that the crystal surface is often covered by PI or molding material in the current market.

[0007] The technical solution adopted by this utility model is as follows: This utility model proposes a fan-out type packaging structure, wherein the fabrication of the circuit layer on the first side of the product to be processed includes: The PI-1 layer is coated by spin coating, then exposed, developed and cured. Openings are made on the PI-1 layer, including opening A and opening B. A metal seed layer is sputtered on the PI-1 layer by sputtering process. After the photoresist layer is coated by spin coating, it is exposed and developed. An opening C is made on the metal seed layer, and a metal layer 1M is electroplated on the opening C and the opening A. The photoresist at the corresponding position is removed to form the opening D. The PI-2 layer is coated by spin coating, then exposed, developed and cured, and openings E and F are made on the electroplated metal layer. The method for making the opening B and the opening E includes: During the exposure and development process, a photomask is used, and the center of the photomask is a solid structure. The solid structure is solid and corresponds to the position to be exposed on the first side of the product to be processed during exposure, including the positions of opening B and opening E, so that the photoresist at the corresponding position is not exposed to ultraviolet light. When cleaning in the developer, the photoresist at the corresponding position is washed away, thereby forming opening B and opening E. The openings B, D, and E are positioned correspondingly to form the cavity structure G of the product.

[0008] Furthermore, the method for forming the product to be processed includes: A glass wafer is received, a release adhesive layer is coated on the glass wafer, and a metal seed layer is sputtered onto the release adhesive layer; Copper needles are assembled on the metal seed layer or copper pillars are formed by wet electroplating. The chip is mounted face down on the first glass wafer. The wafer and the copper needle or copper pillar are encapsulated and protected by plastic encapsulation. The encapsulated body is ground to expose the copper needles or copper pillars; A second circuit layer is fabricated on the second surface of the wafer; A second glass wafer is mounted on the second circuit layer, and the first glass wafer is removed from the product to form the product to be processed.

[0009] Furthermore, the method for forming the opening F includes: During the exposure and development process, a photomask is used. The position of the photomask corresponding to the opening F is set as a solid structure. During exposure, the photoresist at the position corresponding to the solid structure is not exposed to ultraviolet light. During cleaning in the developer, the photoresist at the corresponding position is washed away, thereby forming the opening F.

[0010] Furthermore, a capacitor is disposed on the opening F, the method comprising: attaching the capacitor to the opening F by printing flux, and soldering the capacitor onto the flux by reflow soldering.

[0011] Furthermore, the capacitors are provided in two sets.

[0012] Furthermore, a glass wafer is mounted on top of the capacitor; Remove the glass wafer from the product; Metal balls are implanted on the second circuit layer; A protective film is attached to the top of the metal ball to protect it. A protective film 2 is provided on one side of the capacitor to protect the cavity structure G of the product, so that the cavity structure is protected in the subsequent cutting process. Remove the protective film from the metal sphere; The product is cut from the side of the metal ball.

[0013] Furthermore, the removal of the second protective film forms the fan-out packaging structure.

[0014] Furthermore, it includes: a wafer, a first circuit layer, a second circuit layer, copper pillars, a capacitor, a cavity structure G, and a molding compound; The first side of the wafer is provided with a circuit layer one, the second side of the wafer is provided with a circuit layer two, and the first side of the wafer is provided with a cavity structure G.

[0015] Furthermore, a capacitor is disposed above the first circuit layer; A metal ball is placed above the second line layer.

[0016] Furthermore, an opening F is provided above the first circuit layer, and flux is disposed in the opening F, and the capacitor is connected to the first circuit layer through the flux.

[0017] The beneficial effects of this utility model by adopting the above structure are as follows: 1. The use of photomasks enables precise photolithography of corresponding positions on the chip, ensuring the accuracy of the lithographic area. By depositing metal layers through sputtering and performing operations such as photolithography and copper filling, precise 1M copper layer circuits can be formed, enabling circuit rewiring, improving circuit conductivity and signal transmission efficiency, and ensuring the electrical performance of the package structure.

[0018] 2. The exposure area exposes the crystal surface, avoiding the influence of other materials on the chip's acoustic wave reception, ensuring that the chip can accurately receive and process acoustic wave signals, improving the chip's performance and reliability. The use of the PI1 / PI2 photomask on the crystal surface further ensures that the acoustic wave reception of the crystal surface is not interfered with by other materials. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the packaging structure formed by the fan-out type packaging structure proposed in this utility model. Figure 2The overall steps of the fan-out type packaging structure proposed in this utility model Figure 1 ; Figure 3 The overall steps of the fan-out type packaging structure proposed in this utility model Figure 2 ; Figure 4 The overall steps of the fan-out type packaging structure proposed in this utility model Figure 3 ; Figure 5 The overall steps of the fan-out type packaging structure proposed in this utility model Figure 4 ; Figure 6 The overall steps of the fan-out type packaging structure proposed in this utility model Figure 5 ; Figure 7 The overall steps of the fan-out type packaging structure proposed in this utility model Figure 6 ; Figure 8 The overall steps of the fan-out type packaging structure proposed in this utility model Figure 7 ; Figure 9 The overall steps of the fan-out type packaging structure proposed in this utility model Figure 8 ; Figure 10 The overall steps of the fan-out type packaging structure proposed in this utility model Figure 9 ; Figure 11 The overall steps of the fan-out type packaging structure proposed in this utility model Figure 10 ; Figure 12 The overall steps of the fan-out type packaging structure proposed in this utility model Figure 10 one; Figure 13 The overall steps of the fan-out type packaging structure proposed in this utility model Figure 10 two; Figure 14 The steps of the fan-out type packaging structure proposed in this utility model Figure 9 Schematic diagram of solid structure.

[0020] Among them, 1. Molded body; 2. Wafer; 3. Circuit layer one; 4. Circuit layer two; 5. Copper pillar; 6. Capacitor; 7. Cavity structure G; 8. Opening A; 9. Opening B; 10. Opening C; 11. Opening D; 12. Opening E; 13. Opening F; 14. PI-1 layer; 15. PI-2 layer; 16. Metal layer 1M; 17. Metal ball; 18. Glass wafer one; 19. Glass wafer two; 20. Release adhesive layer; 21. Protective film one; 22. Protective film two; 23. Glass wafer three; 24. Photomask; 25. Solid structure.

[0021] The accompanying drawings are provided to further understand the present invention and form part of the specification. They are used together with the embodiments of the present invention to explain the present invention and do not constitute a limitation thereof. Detailed Implementation

[0022] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the protection scope of the present utility model.

[0023] In the description of this utility model, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0024] like Figure 9As shown, this utility model proposes a fan-out packaging structure. The first side of the product to be packaged is fabricated using circuit layer 3, including: coating a PI-1 layer 14 by spin coating, followed by exposure, development, and curing; creating openings on the PI-1 layer 14, including opening A8 and opening B9; sputtering a metal seed layer onto the PI-1 layer 14; coating a photoresist layer by spin coating, followed by exposure and development; creating opening C10 on the metal seed layer; electroplating a metal layer 1M 16 on opening C10 and opening A8; removing the photoresist at the corresponding positions to form opening D11; coating a PI-2 layer 15 by spin coating, followed by exposure, development, and curing; creating openings E12 and F13 on the electroplated metal layer; and creating openings B9 and E12. The method 12 includes: during exposure and development, using a photomask 24, with a solid structure 25 in the center of the photomask 24; the solid structure 25 is solid and corresponds to the exposed positions on the first side of the product to be processed during exposure, including the positions of openings B 9 and E 12, so that the photoresist at the corresponding positions is not exposed to ultraviolet light. During cleaning in the developing solution, the photoresist at the corresponding positions is washed away, thereby forming openings B 9 and E 12; the positions of openings B9, opening D 11 and opening E 12 correspond to each other, thereby forming the cavity structure G 7 of the product. A uniform thin film is formed by spin coating, and openings are made in the PI layer by exposure and development using the photomask 24. Electroplating forms metal lines, and multiple layers of PI and metal alternate to form a circuit layer. A circuit layer 1 is formed on the first side of the product, containing multiple openings and a metal layer 1M 16, laying the foundation for subsequent structures.

[0025] like Figures 2-8 The method for forming the product to be processed includes: receiving a glass wafer 18; coating a release liner 20 on the glass wafer 18; sputtering a metal seed layer on the release liner 20; mounting copper pins or performing wet electroplating to form copper pillars 5 on the metal seed layer; mounting a wafer 2 with its first side facing down on the glass wafer 18; encapsulating and protecting the wafer 2 and the copper pins or copper pillars 5 by molding; grinding the molding compound 1 to expose the copper pins or copper pillars 5; fabricating a second circuit layer 4 on the second side of the wafer 2; mounting a second glass wafer 19 on the second circuit layer 4; and removing the glass wafer 18 from the product to form the product to be processed.

[0026] The seed layer can be a titanium-copper layer. The release adhesive layer facilitates the peeling of the copper pillar 5 from the glass wafer 18. The copper pillar 5 connects the wafer 2 and the circuit layer. The molding compound protects the internal structure. The copper pillar 5 is exposed by grinding. The glass wafer 19 temporarily supports the circuit layer 4, forming the product to be processed, which includes the wafer 2, copper pillar 5, circuit layer and molding compound 1, in preparation for subsequent processing.

[0027] like Figure 14As shown, the method for forming aperture F13 includes: during exposure and development, a photomask 24 is used. The position of the photomask 24 corresponding to aperture F13 is set as a solid structure 25. During exposure, the photoresist at the position corresponding to the solid structure 25 is not exposed to ultraviolet light. During cleaning in the developing solution, the photoresist at the corresponding position is washed away, thereby forming aperture F13. The solid area of ​​the photomask 24 blocks ultraviolet light, making the corresponding photoresist soluble. After development, an aperture is formed, meeting circuit design requirements and enhancing functionality.

[0028] A capacitor 6 is disposed on an opening F 13. The method includes: printing flux onto the opening F 13, mounting the capacitor 6 on the opening F 13, and soldering the capacitor 6 onto the flux by reflow soldering.

[0029] Flux is used to assist in soldering, and reflow soldering enables capacitor 6 to be electrically connected to the circuit layer, completing the packaging structure, protecting internal components, and facilitating subsequent use. Capacitor 6 is fixed in the opening F 13 to realize the circuit function.

[0030] There are two sets of capacitors 6.

[0031] Two sets of capacitors 6 can form specific circuits, such as filters, to meet circuit design requirements and enhance functionality.

[0032] like Figures 10-13 As shown: a glass wafer 23 is mounted on top of capacitor 6; glass wafer 19 is removed from the product; a metal ball 17 is implanted on circuit layer 4; a protective film 21 is attached above the metal ball 17 to protect it; a protective film 22 is placed on one side of the product to protect the cavity structure G7 of the product, so that the cavity structure is protected in the subsequent cutting process; the protective film 21 on the metal ball 17 is removed; the product is cut from the side of the metal ball 17.

[0033] The glass wafer is temporarily supported by three 23s, the metal ball 17 serves as an external connection, the protective film prevents cutting damage, the cutting forms a single package, and the fan-out package structure is completed.

[0034] Remove the protective film 22 to form a fan-out package structure.

[0035] The capacitor performs the circuit function, and the metal ball 17 serves as an external connection terminal, improving the electrical performance and connection function of the package structure, forming a complete fan-out package structure to meet the packaging requirements of electronic components.

[0036] like Figure 1 As shown, the fan-out packaging structure of this utility model includes: a chip 2, a circuit layer 1 3, a circuit layer 2 4, a copper pillar 5, a capacitor 6, a cavity structure G 7, and a molding compound 1; The first side of the wafer 2 is provided with a circuit layer 3, the second side of the wafer 2 is provided with a circuit layer 4, and the first side of the wafer 2 is provided with a cavity structure G 7.

[0037] A capacitor 6 is installed above the first layer 3 of the circuit; a metal ball 17 is installed above the second layer 4 of the circuit.

[0038] An opening F13 is provided above the circuit layer 3, and flux is placed in the opening F13. The capacitor 6 is connected to the circuit layer 3 through the flux.

[0039] The fan-out packaging structure formed by the method of this utility model uses the photomask design of this utility model during the fabrication of the photoresist layer to form a cavity structure, thereby exposing the wafer surface and avoiding the influence of other materials on the chip's acoustic wave reception. This ensures that the chip can accurately receive and process acoustic wave signals, improving the chip's performance and reliability.

[0040] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0041] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

[0042] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the inventive spirit of the present invention, such designs should fall within the protection scope of the present invention.

Claims

1. A fan-out type packaging structure, characterized in that: include: Wafer (2), circuit layer 1 (3), circuit layer 2 (4), copper pillar (5), capacitor (6), cavity structure G (7), encapsulation (1); The first side of the wafer (2) is provided with a circuit layer 1 (3), the second side of the wafer (2) is provided with a circuit layer 2 (4), and the first side of the wafer (2) is provided with a cavity structure G (7).

2. The fan-out packaging structure according to claim 1, characterized in that: A capacitor (6) is provided above the line layer (3); A metal ball (17) is provided above the second (4) line layer.

3. The fan-out packaging structure according to claim 2, characterized in that: An opening F (13) is provided above the first circuit layer (3), and flux is provided in the opening F (13), and the capacitor (6) is connected to the first circuit layer (3) through the flux.

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