Panel level fanout package structure

Abstract

The embodiment of the application provides a Panel level Fanout packaging structure, and the embodiment of the application adds a first stress compensation layer and a second stress compensation layer on the front surface and the back surface of a chip body, so that the stress between layers of materials is reduced to protect the product from stress damage.

Description

Technical Field

[0001] The embodiments of this application belong to the technical field, and in particular relate to a Panel-level Fanout packaging structure. Background Technology

[0002] As semiconductor devices develop towards miniaturization, high density, high performance, and low cost, panel-level fanout wafer-level packaging technology has seen rapid development due to its ability to package a large number of chips using a larger substrate and its more flexible wiring design.

[0003] However, traditional panel level package (PLP) processes face some problems. Due to the mismatch in coefficient of thermal expansion (CTE) between materials such as chips, molding compounds, and RDL wiring layers, chip warping and deformation often occur during high-temperature and high-voltage applications, resulting in a large amount of stress and chip failure.

[0004] This solution is a new packaging structure developed based on Panel-level Fanout process technology, which improves stress during product application. Summary of the Invention

[0005] To address or mitigate the problems in the prior art, embodiments of this application provide a Panel-level Fanout packaging structure, including: a chip body;

[0006] The front side of the chip body is provided with an electrical connection layer spaced apart, the upper surface of the electrical connection layer is provided with a first stress compensation layer, and the back side of the chip body is provided with a second stress compensation layer.

[0007] A redistribution layer is provided on the upper surface of the first stress compensation layer;

[0008] The second stress compensation layer has external pins located away from the back of the chip body;

[0009] The chip body has a molding compound on both the front and back sides, and the outer pins are exposed away from the surface of the second stress compensation layer.

[0010] In a preferred embodiment of this application, both the first stress compensation layer and the second stress compensation layer are conductive silver paste.

[0011] In a preferred embodiment of this application, the second stress compensation layer is laid flat across the entire back side of the chip body.

[0012] In a preferred embodiment of this application, the electrical connection layer is a metal ball.

[0013] Compared with the prior art, the embodiments of this application provide a panel-level fanout packaging structure. The embodiments of this application reduce the stress between the materials of each layer by adding a first stress compensation layer and a second stress compensation layer on the front and back of the chip body, thereby protecting the product from stress damage. Attached Figure Description

[0014] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0015] Figure 1 This is a Panel-level Fanout encapsulation structure provided in the embodiments of this application. Detailed Implementation

[0016] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.

[0017] like Figure 1 As shown, this application embodiment provides a Panel-level Fanout packaging structure, including: a chip body:

[0018] The chip body 1 has an electrical connection layer 2 spaced apart on its front side. In this embodiment, the electrical connection layer 2 is a metal ball, specifically formed by a ball-mounting process. A first stress compensation layer 3 is provided on the upper surface of the electrical connection layer 2, and a second stress compensation layer 5 is provided on the back side of the chip body 1. In this embodiment, both the first stress compensation layer 3 and the second stress compensation layer 5 are conductive silver paste. By adding the first stress compensation layer 3 and the second stress compensation layer 5 to the front and back sides of the chip body 1, this embodiment can reduce the stress between the materials in each layer to protect the product from stress damage. A redistribution layer 4 is provided on the upper surface of the first stress compensation layer 3. The redistribution layer 7 is composed of copper. The main function of the redistribution layer 7 (RDL) is to redistribute the I / O pins of the chip to change the pin spacing or connect multiple chips.

[0019] The second stress compensation layer 5 has an external pin 6 located away from the back of the chip body 1;

[0020] The chip body 1 has a molding compound 7 on both the front and back sides, and exposes the surface of the external pin 6 away from the second stress compensation layer 5.

[0021] The first stress compensation layer 3 acts as a buffer between the electrical connection layer 1 and the redistribution layer 4, and the second stress compensation layer 5 acts as a buffer between the back side of the chip body 1 and the external pin 6.

[0022] In a preferred embodiment of this application, the second stress compensation layer 5 is laid flat across the entire back side of the chip body 1.

[0023] The following details the Panel-level Fanout packaging process:

[0024] 1. Bump balls 2 are implanted on the front side of the chip body 1 using a ball-mounting process;

[0025] 2. Apply a second stress compensation layer 5 to the back of the chip body 1, and then cure it;

[0026] 3. Mount the chip body 1 onto the carrier board;

[0027] 4. Encapsulate the chip body 1 and the bump ball 2 with the molding compound 7;

[0028] 5. The Bump ball 2 is exposed through a grinding process;

[0029] 6. Form a first stress compensation layer 3 on the surface of the bump ball 2, and then cure it;

[0030] 7. Electroplating a redistribution layer 4 on the upper surface of the first stress compensation layer 3;

[0031] 8. Cover the front of the chip body 1 with the molding compound 7;

[0032] 9. Remove the carrier board to expose the second stress compensation layer 5 on the back of the chip body 1.

[0033] 10. An outer pin 6 (made of copper) is grown on the back of the second stress compensation layer 5 by electroplating;

[0034] 11. The entire product is encapsulated by the plastic sealant 7.

[0035] 12. The entire tea plantation is cut into individual chips.

[0036] Compared with the prior art, the embodiments of this application provide a panel-level fanout packaging structure. By adding a first stress compensation layer and a second stress compensation layer to the front and back of the chip body, the stress between the materials of each layer is reduced to protect the product from stress damage. During the packaging process, it can effectively improve the warpage of the carrier board and improve the product production yield of the packaging process.

[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A panel-level fanout encapsulation structure, characterized in that, Includes: the chip itself: The front side of the chip body is provided with an electrical connection layer spaced apart, the upper surface of the electrical connection layer is provided with a first stress compensation layer, and the back side of the chip body is provided with a second stress compensation layer. A redistribution layer is provided on the upper surface of the first stress compensation layer; The second stress compensation layer has external pins located away from the back of the chip body; The chip body has a molding compound on both the front and back sides, and the outer pins are exposed away from the surface of the second stress compensation layer.

2. The Panel-level Fanout packaging structure as described in claim 1, characterized in that, Both the first stress compensation layer and the second stress compensation layer are conductive silver paste.

3. The Panel-level Fanout packaging structure as described in claim 1, characterized in that, The second stress compensation layer is laid flat across the entire back side of the chip body.

4. The Panel-level Fanout packaging structure as described in claim 1, characterized in that, The electrical connection layer is a metal sphere.

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