Endoscope wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation

Abstract

The utility model provides a kind of endoscope wireless radio frequency receiving and signal conversion circuit with multiple power domain isolation, including signal conversion chip, and with the signal conversion chip connection 50Ω standardization coaxial antenna input matching circuit, multiple power domain partition power supply circuit, MIPI signal output circuit and fault monitoring and outer synchronization auxiliary circuit.The utility model's endoscope wireless radio frequency receiving and signal conversion circuit with multiple power domain isolation, through standardization radio frequency link design, multiple power domain independent isolation, hardware protocol conversion, four big optimizations of fault real-time monitoring, completely solve the industry pain point of unstable wireless image transmission, poor compatibility, no fault self-checking.

Description

Technical Field

[0001] This utility model relates to a circuit, and more particularly to an endoscope wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation. Background Technology

[0002] Traditional wireless endoscope radio frequency circuits have several hardware defects, the main problems of which are as follows: 1. High RF signal transmission loss and poor reception performance: Traditional antenna circuits lack precise impedance matching and DC blocking filtering, resulting in impedance mismatch in high-frequency RF signal transmission, causing signal reflection and attenuation. In weak signal environments, the receiving sensitivity of the equipment is low, and long-distance transmission is prone to frame loss and disconnection.

[0003] 2. Power supply crosstalk interferes with high-speed image transmission: The multi-functional modules of the RF chip share a single power supply. The dynamic fluctuation of the operating current of the core, phase-locked loop, and transceiver circuit generates a large amount of ripple. The power supply ripple is coupled to each other, interfering with the high-speed serial image data stream of 4Gbps ultra-high-speed V-by-One image, resulting in more noise in the wireless image, screen flickering, and momentary lag.

[0004] 3. Incompatible signal protocols and weak versatility: The wireless handpiece transmits V-by-One serial signals, which are incompatible with the main control MIPI receiving protocol, making it impossible to connect to the original wired endoscope imaging system to share the whole imaging system, resulting in low equipment reuse rate.

[0005] 4. Lack of fault monitoring and timing synchronization mechanism: The lack of hardware fault detection pins means that RF lockout, antenna abnormalities, and chip failures cannot be identified in real time; there is no unified timing reference for wired and wireless images, and screen switching is prone to misalignment, flickering, and timing disorder, which seriously affects the stability of surgical imaging. Utility Model Content

[0006] This invention provides an endoscope wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation to solve at least one of the above problems.

[0007] According to one aspect of the present invention, an endoscope wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation is provided, comprising: The signal conversion chip is used to receive the V-by-One high-speed serial image signal transmitted by the wireless endoscope, complete clock data recovery, timing adjustment and data reconstruction, and convert the V-by-One protocol into the standard MIPI CSI image protocol output; A 50Ω standardized coaxial antenna input matching circuit is connected to the signal input terminal of the signal conversion chip. It is used to access the serial image signal of the wireless endoscope, achieve 50Ω link impedance matching and isolate DC noise interference. The multi-power domain partitioned power supply circuit is electrically connected to multiple independent power supply pins of the signal conversion chip to build multiple mutually isolated power domains, which independently power each functional unit inside the chip and suppress power ripple crosstalk between modules. The MIPI signal output matching circuit connects to the image differential output terminal of the signal conversion chip. It is used to perform impedance matching on the high-speed MIPI differential signal and outputs a 4-lane standard MIPI CSI image signal to the back-end main controller. The fault monitoring and external synchronization auxiliary circuit is connected to the fault alarm pin and external synchronization input pin of the signal conversion chip, respectively, to output the chip fault alarm signal to the outside, and at the same time connect to the external unified frame synchronization reference to unify the timing of wireless and wired image output.

[0008] This utility model presents an endoscope wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation. Through four major optimizations—standardized radio frequency link design, independent isolation of multiple power domains, hardware protocol conversion, and real-time fault monitoring—it completely solves the industry pain points of unstable wireless image transmission, poor compatibility, and lack of fault self-diagnosis.

[0009] In some embodiments, the 50Ω standardized coaxial antenna input matching circuit of this invention includes two coaxial RF sockets P3 and P4, a standard 50Ω coaxial transmission cable, multiple sets of DC blocking capacitors, and two sets of terminating matching resistors. One end of the standard 50Ω coaxial transmission cable is connected to the receiving antenna, and the other end is electrically connected to the signal terminals of the two coaxial RF sockets respectively. The two coaxial RF sockets are connected to the two RF input pins of the signal conversion chip through corresponding DC blocking capacitors. Each RF negative input pin is grounded through the corresponding DC blocking capacitor and terminating matching resistor. Therefore, DC noise and low-frequency interference can be completely isolated from the line, retaining only the effective high-frequency RF AC signal; full-link 50Ω standard impedance matching can be achieved, eliminating high-frequency signal reflection loss and significantly improving signal reception sensitivity and purity.

[0010] In some embodiments, the multi-power domain partitioned power supply circuit of this utility model includes: a core logic power supply branch, which is connected to the core power supply pins of the signal conversion chip and is used to power the main control unit inside the chip and suppress the power supply noise generated by the core operation from spreading outward; a first peripheral I / O power supply branch, which is connected to the first set of peripheral I / O pins of the signal conversion chip and is used to provide operating power for GPIO, interrupt input, and I2C communication peripheral interfaces, and is configured with filtering elements to achieve power supply noise reduction; and a second peripheral I / O power supply branch, which is connected to the second set of peripheral I / O pins of the signal conversion chip and is used to independently power the remaining peripheral interfaces, and is connected to the first peripheral I / O power supply branch. The circuits are electrically isolated from each other to avoid interference between the two sets of peripherals. The RF receiving domain power supply branch is connected to the RF receiving power supply pin of the signal conversion chip, providing independent power to the RF demodulation receiving circuit and isolating it from digital circuit noise interference with weak RF receiving signals. The PLL power supply branch is connected to the PLL power supply pin of the signal conversion chip, providing clean operating power to the internal clock PLL unit and ensuring stable timing of high-speed serial signals. The MIPI transmitting domain power supply branch is connected to the MIPI transmitting power supply pin of the signal conversion chip, providing independent power to the high-speed MIPI differential signal transmitting unit and reducing power ripple interference caused by high-speed data transmission. This eliminates cross-module power crosstalk, ensures stable high-speed signal transmission, guarantees stable operating voltage and extremely low power ripple for each module, and meets the power supply requirements for 4Gbps ultra-high-speed signal transmission.

[0011] In some embodiments, the core logic power supply branch of this invention includes a core filter capacitor C342. One end of the core filter capacitor C342 is connected to the RVDDCORE power supply network, and the other end is grounded, which is used to filter out power ripple for the core arithmetic unit of the signal conversion chip.

[0012] In some embodiments, the first peripheral I / O power supply branch of this invention includes a first filter capacitor C324, a second filter capacitor C325, multiple pull-up resistors, and multiple current-limiting resistors. One end of the first filter capacitor C324 and the second filter capacitor C325 are connected to the RVDDIO1 power supply network, and the other end is grounded. The RVDDIO1 power supply network supplies power to the GPIO pins, interrupt input pins, and I2C communication pins of the signal conversion chip. Each pull-up resistor and current-limiting resistor is connected in series with the I2C and GPIO signal lines, respectively. The second peripheral I / O power supply branch includes an I / O2 filter capacitor C345. One end of the I / O2 filter capacitor C345 is connected to the RVDDIO2 power supply network, and the other end is grounded. The RVDDIO2 power supply network independently supplies power to the second set of peripheral I / O ports of the signal conversion chip and is electrically isolated from the first peripheral I / O power supply branch.

[0013] In some embodiments, the power supply branch of the radio frequency receiving domain of this utility model includes two sets of radio frequency filter capacitors C338 and C339. One end of each set of radio frequency filter capacitors is connected to the RVDDRX power supply network, and the other end is grounded. The RVDDRX power supply network independently supplies power to the radio frequency demodulation receiving unit inside the signal conversion chip, blocking the interference of digital circuit noise on weak radio frequency input signals.

[0014] In some embodiments, the phase-locked loop power supply branch of this invention includes a phase-locked loop filter capacitor C328 and a level configuration resistor R314; one end of the phase-locked loop filter capacitor C328 is connected to the RVDDPLL power supply network and the other end is grounded, the RVDDPLL power supply network supplies power to the phase-locked loop unit inside the signal conversion chip; the phase-locked loop enable pin RPDN of the signal conversion chip is electrically connected to the RVDDIO1 power supply network via the level configuration resistor R314 to provide a power-on enable level for the phase-locked loop unit.

[0015] In some embodiments, the MIPI transmit domain power supply branch of this invention includes a MIPI transmit filter capacitor C329. One end of the MIPI transmit filter capacitor C329 is connected to the RVDDTX power supply network, and the other end is grounded. The RVDDTX power supply network independently supplies power to the MIPI differential signal transmit unit inside the signal conversion chip, thereby suppressing power interference caused by high-speed data transmission.

[0016] In some embodiments, the MIPI signal output circuit of this invention includes: a first differential matching resistor group RN1, a second differential matching resistor group RN2, a first single-channel matching resistor R317, and a second single-channel matching resistor R318; the first differential matching resistor group RN1 is configured on the third MIPI differential data positive transmission pin MIPI_RX0_D3P, the third MIPI differential data negative transmission pin MIPI_RX0_D3N, the first MIPI differential data positive transmission pin MIPI_RX0_D1P, and the first MIPI... The signal lines corresponding to the differential data negative transmission pin MIPI_RX0_D1N are used for impedance matching of the high-speed differential signals transmitted by the aforementioned pins. The second differential matching resistor group RN2 is set on the signal lines corresponding to the MIPI differential clock positive transmission pin MIPI_RX0_CK0P, the MIPI differential clock negative transmission pin MIPI_RX0_CK0N, the zeroth MIPI differential data positive transmission pin MIPI_RX0_D0P, and the zeroth MIPI differential data negative transmission pin MIPI_RX0_D0N, and is used for impedance matching of the high-speed differential signals transmitted by the aforementioned pins. The first single-channel matching resistor R317 is connected in series on the signal line of the second MIPI differential data positive transmission pin MIPI_RX0_D2P, and the second single-channel matching resistor R318 is connected in series on the signal line of the second MIPI differential data negative transmission pin MIPI_RX0_D2N, and is used for impedance matching of the second MIPI differential data signal.

[0017] In some embodiments, the fault monitoring and external synchronization auxiliary circuit of this utility model includes a fault monitoring branch; the fault monitoring branch includes a first fault test point TP2 and a second fault test point TP3; the first fault output pin ERR0 of the signal conversion chip is electrically connected to the first fault test point TP2, and the second fault output pin ERR1 of the signal conversion chip is electrically connected to the second fault test point TP3; the first fault test point TP2 and the second fault test point TP3 are used to collect fault level signals during the debugging phase, monitor the operating status of the signal conversion chip in real time, and output fault alarm signals to the outside.

[0018] The technical effects of this utility model are as follows: 1. Significantly improved RF reception performance: The end-to-end 50Ω precise impedance matching and high-frequency DC blocking filter design completely eliminate high-frequency signal reflection and transmission loss, resulting in high device reception sensitivity, strong anti-interference capability, and stable wireless image reception in long-distance and weak signal environments.

[0019] 2. High-speed wireless imaging is stable and without abnormalities: Multi-power domain partitioned isolated power supply eliminates power ripple crosstalk from the source. 4K wireless images are free of flickering, frame loss, noise and stuttering, and can be adapted to long-term continuous surgical work in the complex electromagnetic environment of the operating room.

[0020] 3. High equipment versatility: The hardware achieves seamless conversion from V-by-One to MIPI protocol, and the wireless endoscope can be directly connected to the original dual-channel wired imaging host. The single host is compatible with three types of equipment: optical endoscope, electronic endoscope and wireless endoscope, which greatly reduces the equipment procurement and maintenance costs.

[0021] 4. Enhanced equipment intelligence and stability: Equipped with hardware fault self-checking and timing synchronization functions, it can monitor wireless link faults in real time, achieving unified timing of wired and wireless images, smooth and error-free image switching, and significantly improving the overall imaging consistency and reliability. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of an endoscope wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation according to one embodiment of the present invention. Figure 2 This is a circuit diagram of a 50Ω standardized coaxial antenna input matching circuit for an endoscope wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation, according to one embodiment of the present invention. Figures 3-6 This is a circuit diagram of a multi-power domain partitioned power supply circuit for an endoscope wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation, according to one embodiment of the present invention. Figure 7 This is a circuit diagram of the fault monitoring branch of an endoscope wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation, according to one embodiment of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0024] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0025] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising" or "including" include not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0026] The present invention will now be described in further detail with reference to the accompanying drawings.

[0027] Figure 1 The diagram schematically illustrates the structure of an endoscope wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation according to one embodiment of the present invention.

[0028] As shown in Reference 1, the endoscope wireless RF receiver and signal conversion circuit with multi-power domain isolation includes a signal conversion chip for receiving V-by-One high-speed serial image signals transmitted by the wireless endoscope, completing clock data recovery, timing adjustment and data reconstruction, and converting the V-by-One protocol into the standard MIPI CSI image protocol output.

[0029] The 50Ω standardized coaxial antenna input matching circuit 10 is connected to the signal input terminal of the signal conversion chip and is used to access the serial image signal of the wireless endoscope, realize 50Ω link impedance matching and isolate DC noise interference.

[0030] The multi-power domain partitioned power supply circuit 20 connects to multiple independent power supply pins of the signal conversion chip to construct multiple mutually isolated power domains, which independently power each functional unit inside the chip and suppress power ripple crosstalk between modules.

[0031] The MIPI signal output circuit 30 is connected to the image differential output terminal of the signal conversion chip. It is used to perform impedance matching on the high-speed MIPI differential signal and output the 4-lane standard MIPI CSI image signal to the back-end main controller.

[0032] The MIPI signal output circuit includes: a first differential matching resistor group RN1, a second differential matching resistor group RN2, a first single-channel matching resistor R317, and a second single-channel matching resistor R318.

[0033] The first differential matching resistor group RN1 is set on the signal lines corresponding to the third MIPI differential data positive transmission pin MIPI_RX0_D3P, the third MIPI differential data negative transmission pin MIPI_RX0_D3N, the first MIPI differential data positive transmission pin MIPI_RX0_D1P, and the first MIPI differential data negative transmission pin MIPI_RX0_D1N, and is used to perform impedance matching on the high-speed differential signals transmitted by the above pins.

[0034] The second differential matching resistor group RN2 is set on the signal lines corresponding to the MIPI differential clock positive transmission pin MIPI_RX0_CK0P, the MIPI differential clock negative transmission pin MIPI_RX0_CK0N, the zeroth MIPI differential data positive transmission pin MIPI_RX0_D0P, and the zeroth MIPI differential data negative transmission pin MIPI_RX0_D0N, and is used to perform impedance matching on the high-speed differential signals transmitted by the above pins.

[0035] The first single-channel matching resistor R317 is connected in series with the signal line of the second MIPI differential data positive transmission pin MIPI_RX0_D2P, and the second single-channel matching resistor R318 is connected in series with the signal line of the second MIPI differential data negative transmission pin MIPI_RX0_D2N, and is used to perform impedance matching for the second MIPI differential data signal.

[0036] The fault monitoring and external synchronization auxiliary circuit 40 is connected to the fault alarm pin and the external synchronization input pin of the signal conversion chip, respectively, to output the chip fault alarm signal to the outside, and at the same time connect to the external unified frame synchronization reference to unify the timing of wireless and wired image output.

[0037] This system receives high-frequency radio frequency image signals emitted by the wireless endoscope handpiece, sequentially performing signal DC blocking filtering, impedance matching, radio frequency demodulation, and V-by-One serial protocol conversion. Finally, it outputs an industry-standard MIPI image signal, which is then fed into the main control SOC for image processing and display, enabling wireless endoscope imaging. Each module collaborates sequentially to complete the entire workflow, from antenna signal access and filtering to clean power supply, signal demodulation, protocol conversion, timing synchronization, and fault self-diagnosis.

[0038] In this embodiment, the signal conversion chip is the THCV242A-P chip.

[0039] The THCV242A-P chip 100 is a high-speed, high-frequency operating chip. Its internal functional units have extremely high requirements for power purity. The multi-power domain partitioned power supply circuit 20 of the THCV242A-P chip adopts a multi-power domain independent partitioned power supply architecture to eliminate cross-module power supply crosstalk and ensure stable high-speed signal transmission.

[0040] Power input process: The DC power supply of the whole system is connected to this board, which is split into multiple independent power supply branches. Each power supply is first connected in series with a high-frequency ferrite bead and then paired with a nearby ground-mounted filter capacitor to complete the first-stage filtering and noise reduction, filtering out front-end power supply noise and surge interference.

[0041] Power supply partitioning: The circuit divides the power supply into five completely independent power domains: the RVDDCORE core logic power branch, the RVDDIO1 / RVDDIO2 peripheral I / O power branch, the RVDDRX RF receiver power branch, the RVDDPLL phase-locked loop power branch, and the RVDDTX MIPI transmitter power branch. Each power group is electrically isolated and independently filtered to avoid crosstalk caused by ripple from the dynamic operating currents of different functional modules such as the chip core, RF receiver, clock phase-locked loop, and signal output. Among them, RVDDRX is a dedicated power supply for RF receiver, equipped with a C323 filter capacitor for separate voltage regulation and filtering, specifically protecting weak RF signals from interference.

[0042] Power output process: Five clean and independent power supplies are connected to the corresponding power pins of the chip, providing power to the chip's internal core computing, IO ports, RF demodulation, clock reference, and MIPI signal output units, ensuring stable operating voltage and extremely low power ripple for each module, meeting the power supply requirements for 4Gbps ultra-high-speed signal transmission.

[0043] The MIPI signal output circuit 30 realizes the complete conversion of radio frequency modulation signal to standard digital image signal, and is the core component of the wireless image access master control imaging system.

[0044] Signal Input and Demodulation: After the differential RF signal received by the RXIP / RXIN pins enters the chip, the RF demodulation unit performs carrier stripping, signal amplification, and noise filtering to restore the high-frequency modulated RF signal to the original V-by-One high-speed serial image data stream.

[0045] Onboard protocol conversion processing: The chip has a built-in hardware SerDes protocol conversion unit that automatically parses, timing-adjusts, and reassembles the V-by-One serial data stream, converting the non-universal serial protocol into the industry-standard 4Lane MIPICSI image protocol, achieving perfect adaptation with the main control SOC image receiving channel.

[0046] Signal output process: After protocol conversion is completed, refer to... Figure 6As shown, the chip outputs standard MIPI image signals through the MTXCLK differential clock and four differential data pins from MTX0 to MTX3. The circuit is equipped with a first differential matching resistor group RN1, a second differential matching resistor group RN2, and a second single-channel matching resistor R318 to optimize the impedance integrity of high-speed traces. Finally, the MIPI signal is stably output to the reserved MIPI receiving channel of the SS928 main control SOC. The wireless image data and the wired optical and electronic mirror image data share the same back-end image processing, image quality optimization, image rendering, and display output link.

[0047] Figure 2 The diagram schematically illustrates a 50Ω standardized coaxial antenna input matching circuit for an endoscope wireless radio frequency receiver and signal conversion circuit with multi-power domain isolation according to one embodiment of the present invention.

[0048] refer to Figure 2 As shown, the 50Ω standardized coaxial antenna input matching circuit is the only input link for wireless signals. It uses dual P3 and P4 COAX-M coaxial RF sockets, paired with RG174 standard 50Ω coaxial cable, to achieve low-loss access, DC blocking filtering, and precise impedance matching for differential RF signals.

[0049] The 50Ω standardized coaxial antenna input matching circuit includes two coaxial RF sockets P3 and P4, a standard 50Ω coaxial transmission cable, multiple sets of DC blocking capacitors, and two sets of terminating matching resistors. One end of the standard 50Ω coaxial transmission cable is connected to the receiving antenna, and the other end is electrically connected to the corresponding signal terminals of the two coaxial RF sockets. The two coaxial RF sockets are connected to the two RF input pins of the signal conversion chip through corresponding DC blocking capacitors. Each RF negative input pin is grounded through the corresponding DC blocking capacitor and terminating matching resistor.

[0050] The multiple sets of DC blocking capacitors include a first DC blocking capacitor C331, a second DC blocking capacitor C332, a third DC blocking capacitor C334, and a fourth DC blocking capacitor C337; the two sets of terminating matching resistors include a first terminating matching resistor R313 and a second terminating matching resistor R315. The signal terminal of the first coaxial RF socket P3 is electrically connected to the first RF positive input pin of the signal conversion chip via the second DC blocking capacitor C332. The first RF negative input pin of the signal conversion chip is grounded via the first DC blocking capacitor C331 and the first terminating matching resistor R313. The signal terminal of the second coaxial RF socket P4 is electrically connected to the second RF positive input pin of the signal conversion chip via the fourth DC blocking capacitor C337. The second RF negative input pin of the signal conversion chip is grounded via the third DC blocking capacitor C334 and the second terminating matching resistor R315.

[0051] Signal input process: The wireless endoscope handle transmits a high-frequency radio frequency image signal → the external receiving antenna picks up the signal → the RG174 50Ω coaxial cable transmits the signal → the P3 and P4 coaxial sockets are connected to the circuit board, where P4 corresponds to the differential positive signal CONRX_0P (RX1P) and P3 corresponds to the differential negative signal CONRX_1P (RX1N), thus completing the input of the radio frequency signal into the board.

[0052] Onboard processing flow: The input differential RF signal passes through 47pF high-frequency DC blocking capacitors C331 / C332 / C337 to completely block DC noise and low-frequency interference, retaining only the effective high-frequency RF AC signal; the back end is equipped with 49.9Ω high-precision terminating matching resistors R313 and R315 to achieve 50Ω standard impedance matching throughout the link, eliminating high-frequency signal reflection loss and significantly improving signal reception sensitivity and purity.

[0053] Signal output process: The pure differential RF signals RX1P / RX1N, after DC blocking filtering and impedance matching, are directly routed to pins 56 and 57 (RXIP / RXIN RF dedicated input pins) of the U26 (THCV242A-P) chip and enter the internal RF demodulation unit of the chip.

[0054] Figure 3-6 The diagram schematically illustrates a multi-power domain partitioned power supply circuit with multi-power domain isolation for an endoscope wireless radio frequency receiving and signal conversion circuit, according to one embodiment of the present invention.

[0055] The multi-power domain partitioned power supply circuit includes: RVDDCORE core logic power supply branch, RVDDIO1 first peripheral IO power supply branch, RVDDIO2 second peripheral IO power supply branch, RVDDRX RF receiver domain power supply branch, RVDDPLL phase-locked loop power supply branch and RVDDTX MIPI transmitter domain power supply branch.

[0056] refer to Figure 3 As shown, the first peripheral I / O power supply branch of RVDDIO1 connects to the first group of peripheral I / O pins of the signal conversion chip, providing power for GPIO, interrupt input, and I2C communication peripheral interfaces, and is configured with filtering components to achieve power supply noise reduction. The first peripheral I / O power supply branch includes a first filter capacitor C324, a second filter capacitor C325, multiple pull-up resistors, and multiple current-limiting resistors. One end of the first filter capacitor C324 and the second filter capacitor C325 is connected to the RVDDIO1 power supply network, and the other end is grounded. The RVDDIO1 power supply network supplies power to the GPIO pins, interrupt input pins, and I2C communication pins of the signal conversion chip. Each pull-up resistor and current-limiting resistor is connected in series with the I2C and GPIO signal lines, respectively.

[0057] refer to Figure 4As shown, the RVDDRX RF receiver power branch connects to the RF receiver power pin of the signal conversion chip, providing independent power to the RF demodulation receiver circuit and isolating weak RF received signals from digital circuit noise. The RF receiver power branch includes two sets of RF filter capacitors C338 and C339. One end of each set of capacitors is connected to the RVDDRX power supply network, and the other end is grounded. The RVDDRX power supply network independently powers the internal RF demodulation receiver unit of the signal conversion chip, blocking weak RF input signals from digital circuit noise.

[0058] refer to Figure 5 As shown, the second peripheral I / O power branch of RVDDIO2 connects to the second set of peripheral I / O pins of the signal conversion chip, providing independent power to the remaining peripheral interfaces. It is electrically isolated from the first peripheral I / O power branch to prevent interference between the two sets of peripherals. The second peripheral I / O power branch includes an I / O2 filter capacitor C345, with one end connected to the RVDDIO2 power supply network and the other end grounded. The RVDDIO2 power supply network independently powers the second set of peripheral I / O ports of the signal conversion chip, electrically isolated from the first peripheral I / O power branch.

[0059] refer to Figure 5 As shown, the RVDDPLL phase-locked loop (PLL) power supply branch connects to the PLL power supply pin of the signal conversion chip, providing a clean operating power supply to the internal clock PLL unit and ensuring the timing stability of high-speed serial signals. The PLL power supply branch includes a PLL filter capacitor C328 and a level-configuration resistor R314. One end of the PLL filter capacitor C328 is connected to the RVDDPLL power supply network, and the other end is grounded. The RVDDPLL power supply network supplies power to the internal PLL unit of the signal conversion chip. The PLL enable pin RPDN of the signal conversion chip is electrically connected to the RVDDIO1 power supply network via the level-configuration resistor R314, providing a power-on enable level for the PLL unit.

[0060] refer to Figure 5 As shown, the RVDDTX MIPI transmit domain power branch is connected to the MIPI transmit power pin of the signal conversion chip, providing independent power to the high-speed MIPI differential signal transmit unit and reducing power ripple interference caused by high-speed data transmission. The MIPI transmit domain power branch includes a MIPI transmit filter capacitor C329. One end of the MIPI transmit filter capacitor C329 is connected to the RVDDTX power supply network, and the other end is grounded. The RVDDTX power supply network independently powers the internal MIPI differential signal transmit unit of the signal conversion chip, suppressing power interference generated by high-speed data transmission.

[0061] refer to Figure 6As shown, the RVDDCORE core logic power supply branch connects to the core power supply pin of the signal conversion chip, providing power to the chip's internal main control unit and suppressing the outward propagation of power noise generated during core operation. The core logic power supply branch includes a core filter capacitor C342, one end of which is connected to the RVDDCORE power supply network, and the other end is grounded, used to filter out power ripple for the core operation unit of the signal conversion chip.

[0062] Figure 7 The diagram schematically illustrates the circuit of the fault monitoring branch of the endoscope wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation, and the external synchronization auxiliary circuit, according to one embodiment of the present invention.

[0063] refer to Figure 7 As shown, this fault monitoring branch consists of two pins: ERR0 and ERR1, which are built-in alarm output pins for the chip, corresponding to fault states such as RF lockout, no antenna signal, and chip malfunction. These pins are connected to TP2 and TP3 for debugging and testing, and also to the main control SOC's detection I / O. Under normal operation, the pins are at a fixed level. When there is an RF link abnormality, signal loss, or chip failure, the pin level automatically changes. The main control unit collects the level changes in real time, accurately identifying wireless link faults and enabling proactive device warnings and self-diagnostic faults.

[0064] The fault monitoring and external synchronization auxiliary circuit includes an external synchronization auxiliary branch, which has an external frame synchronization input pin EXTSYNC for introducing a unified timing reference for the main controller. (Reference) Figure 5 As shown, the external synchronization branch (EXTSYNC) is an external frame synchronization input pin. The signal flow is from the main control SOC timing synchronization signal → EXTSYNC pin → chip internal timing control unit. By introducing a unified timing reference from the main control, the timing of wireless image frames is fully aligned with that of wired MIPI image frames, eliminating issues such as screen switching flicker, timing misalignment, and mixed display disorder, thus ensuring the consistency of the overall imaging timing.

[0065] The above are merely some embodiments of this utility model. For those skilled in the art, various modifications and improvements can be made without departing from the inventive concept of this utility model, and these all fall within the protection scope of this utility model.

Claims

1. An endoscope wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation, characterized in that, include: The signal conversion chip is used to receive the V-by-One high-speed serial image signal transmitted by the wireless endoscope, complete clock data recovery, timing adjustment and data reconstruction, and convert the V-by-One protocol into the standard MIPI CSI image protocol output; A 50Ω standardized coaxial antenna input matching circuit is connected to the signal input terminal of the signal conversion chip. It is used to access the wireless endoscope serial image signal, achieve 50Ω link impedance matching, and isolate DC noise interference. The multi-power domain partitioned power supply circuit is electrically connected to multiple independent power supply pins of the signal conversion chip to construct multiple mutually isolated power domains, which independently power each functional unit inside the chip and suppress power ripple crosstalk between modules. The MIPI signal output circuit is connected to the image differential output terminal of the signal conversion chip. It is used to perform impedance matching on the high-speed MIPI differential signal and output the 4-lane standard MIPI CSI image signal to the back-end main controller. The fault monitoring and external synchronization auxiliary circuit is connected to the fault alarm pin and the external synchronization input pin of the signal conversion chip, respectively, to output the chip fault alarm signal to the outside, and at the same time connect to the external unified frame synchronization reference to unify the timing of wireless and wired image output.

2. The endoscopic wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation according to claim 1, characterized in that, The 50Ω standardized coaxial antenna input matching circuit includes two coaxial RF sockets P3 and P4, as well as a standard 50Ω coaxial transmission cable, multiple sets of DC blocking capacitors, and two sets of terminating matching resistors. One end of the standard 50Ω coaxial transmission cable is connected to an external receiving antenna, and the other end is electrically connected to the signal terminals of the two coaxial RF sockets respectively. The two coaxial RF sockets are connected to the two RF input pins of the signal conversion chip through corresponding DC blocking capacitors. Each RF negative input pin is grounded through the corresponding DC blocking capacitor and the terminal matching resistor.

3. The endoscopic wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation according to claim 1, characterized in that, The multi-power domain partitioned power supply circuit includes: The core logic power supply branch is connected to the core power supply pin of the signal conversion chip and is used to supply power to the main control unit inside the chip and suppress the power noise generated by the core operation from spreading outward. The first peripheral I / O power supply branch is connected to the first group of peripheral I / O pins of the signal conversion chip. It is used to provide working power for GPIO, interrupt input, and I2C communication peripheral interfaces, and is configured with filtering elements to achieve power supply noise reduction. The second peripheral I / O power supply branch is connected to the second set of peripheral I / O pins of the signal conversion chip. It is used to independently power the remaining peripheral interfaces and is electrically isolated from the first peripheral I / O power supply branch to avoid mutual interference between the two sets of peripherals. The power supply branch of the radio frequency receiving domain is connected to the radio frequency receiving power supply pin of the signal conversion chip. It is used to provide independent power supply for the radio frequency demodulation receiving circuit and isolate the weak radio frequency receiving signal from digital circuit noise interference. The phase-locked loop power supply branch is connected to the phase-locked loop power supply pin of the signal conversion chip, and is used to provide a clean operating power supply for the internal clock phase-locked loop unit to ensure the timing stability of high-speed serial signals. The MIPI transmit domain power supply branch is connected to the MIPI transmit power supply pin of the signal conversion chip and is used to independently power the high-speed MIPI differential signal transmission unit, reducing power ripple interference caused by high-speed data transmission.

4. The endoscopic wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation according to claim 3, characterized in that, The core logic power supply branch includes a core filter capacitor C342. One end of the core filter capacitor C342 is connected to the RVDDCORE power supply network, and the other end is grounded. It is used to filter out power ripple for the core arithmetic unit of the signal conversion chip.

5. The endoscopic wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation according to claim 3, characterized in that, The first peripheral I / O power supply branch includes a first filter capacitor C324, a second filter capacitor C325, multiple pull-up resistors, and multiple current-limiting resistors. One end of the first filter capacitor C324 and the second filter capacitor C325 are connected to the RVDDIO1 power supply network, and the other end is grounded. The RVDDIO1 power supply network supplies power to the GPIO pins, interrupt input pins, and I2C communication pins of the signal conversion chip. Each pull-up resistor and current-limiting resistor is connected in series with the I2C and GPIO signal lines, respectively. The second peripheral IO power supply branch includes an IO2 filter capacitor C345. One end of the IO2 filter capacitor C345 is connected to the RVDDIO2 power supply network, and the other end is grounded. The RVDDIO2 power supply network independently supplies power to the second set of peripheral IO ports of the signal conversion chip and is electrically isolated from the first peripheral IO power supply branch.

6. The endoscopic wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation according to claim 3, characterized in that, The power supply branch of the radio frequency receiving domain includes two sets of radio frequency filter capacitors C338 and C339. One end of each set of radio frequency filter capacitors is connected to the RVDDRX power supply network, and the other end is grounded. The RVDDRX power supply network independently supplies power to the radio frequency demodulation receiving unit inside the signal conversion chip, blocking digital circuit noise from interfering with weak radio frequency input signals.

7. The endoscopic wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation according to claim 3, characterized in that, The phase-locked loop power supply branch includes a phase-locked loop filter capacitor C328 and a level configuration resistor R314; one end of the phase-locked loop filter capacitor C328 is connected to the RVDDPLL power supply network and the other end is grounded, and the RVDDPLL power supply network supplies power to the phase-locked loop unit inside the signal conversion chip; the phase-locked loop enable pin RPDN of the signal conversion chip is electrically connected to the RVDDIO1 power supply network via the level configuration resistor R314 to provide a power-on enable level for the phase-locked loop unit.

8. The endoscopic wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation according to claim 3, characterized in that, The MIPI transmit domain power supply branch includes a MIPI transmit filter capacitor C329. One end of the MIPI transmit filter capacitor C329 is connected to the RVDDTX power supply network, and the other end is grounded. The RVDDTX power supply network independently supplies power to the MIPI differential signal transmit unit inside the signal conversion chip, suppressing power interference caused by high-speed data transmission.

9. The endoscopic wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation according to claim 1, characterized in that: The MIPI signal output circuit includes: a first differential matching resistor group RN1, a second differential matching resistor group RN2, a first single-channel matching resistor R317, and a second single-channel matching resistor R318. The first differential matching resistor group RN1 is set on the signal lines corresponding to the third MIPI differential data positive transmission pin MIPI_RX0_D3P, the third MIPI differential data negative transmission pin MIPI_RX0_D3N, the first MIPI differential data positive transmission pin MIPI_RX0_D1P, and the first MIPI differential data negative transmission pin MIPI_RX0_D1N, and is used to perform impedance matching on the high-speed differential signals transmitted by the above pins; The second differential matching resistor group RN2 is set on the signal lines corresponding to the MIPI differential clock positive transmission pin MIPI_RX0_CK0P, the MIPI differential clock negative transmission pin MIPI_RX0_CK0N, the zeroth MIPI differential data positive transmission pin MIPI_RX0_D0P, and the zeroth MIPI differential data negative transmission pin MIPI_RX0_D0N, and is used to perform impedance matching on the high-speed differential signals transmitted by the above pins; The first single-channel matching resistor R317 is connected in series with the signal line of the second MIPI differential data positive transmission pin MIPI_RX0_D2P, and the second single-channel matching resistor R318 is connected in series with the signal line of the second MIPI differential data negative transmission pin MIPI_RX0_D2N, and is used to perform impedance matching on the second MIPI differential data signal.

10. The endoscopic wireless radio frequency receiving and signal conversion circuit with multi-power domain isolation according to claim 1, characterized in that, The fault monitoring and external synchronization auxiliary circuit includes a fault monitoring branch; The fault monitoring branch includes a first fault test point TP2 and a second fault test point TP3; The first fault output pin ERR0 of the signal conversion chip is electrically connected to the first fault test point TP2, and the second fault output pin ERR1 of the signal conversion chip is electrically connected to the second fault test point TP3. The first fault test point TP2 and the second fault test point TP3 are used to collect fault level signals during the debugging phase, monitor the operating status of the signal conversion chip in real time, and output fault alarm signals to the outside.

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