A single photon detector system with low latency active dead time configuration

Abstract

The utility model discloses a single photon detector system of low delay initiative configuration dead time, it can be applied to quantum communication, single photon laser radar etc. Application scene, wherein through setting logic gate module, with the logic gate operation of the first dead time control signal that the avalanche signal discrimination module exports and the second dead time control signal that the initiative configuration of main control module generates obtains third dead time control signal, carries out dead time control to single photon detector, makes can with the control signal of minimum transmission delay that avalanche signal discrimination module directly exports directly initiative quenching avalanche current, effectively reduces the delay time from avalanche generation initiative quenching, optimizes the probability of postpulse, promotes the maximum saturation count rate index of detector, can also support initiative dead time configuration function simultaneously, makes single photon detector system can be well adapted to various application scenes.

Description

Technical Field

[0001] This utility model relates to the field of single-photon detection technology, specifically to a single-photon detector system with low-latency active configuration of dead time. Background Technology

[0002] Free-running mode single-photon detectors can perform asynchronous detection, meaning they can respond to photons arriving at any time except for dead time. This makes them an indispensable single-photon detection technology in fields such as single-photon lidar.

[0003] However, the afterpulse effect is more pronounced in free-running mode compared to gated mode for single-photon detectors. Typically, a dead-time signal needs to be applied after each avalanche event to release carriers trapped by defects, reducing the afterpulse probability and thus improving the overall signal-to-noise ratio. The length of the dead-time signal needs to be configurable to adapt to the requirements of saturation count rate and afterpulse performance in different application scenarios. On the other hand, in single-photon lidar applications, it is often necessary to simultaneously switch the single-photon detector from "Geiger mode" to "linear mode" at the moment of laser emission to prevent stray light coupling to the single-photon detector from affecting its operating state. Applying an active dead time is a direct and effective method to achieve this goal.

[0004] In existing free-running single-photon detectors, the dead-time control signal needs to be processed by the main control module before being output to achieve the requirements of dead-time signal length adjustment and application of active dead time, for example... Figure 1 The diagram illustrates an existing dead-time signal control topology. In this topology, the processing delay of the main control module causes the dead-time control signal to lag behind the avalanche signal in timing, resulting in greater accumulation of avalanche charge and thus a more severe afterpulse effect.

[0005] Figure 2 This illustrates a dead-time control scheme for gated single-photon detectors in the prior art. For example... Figure 2 As shown, when the avalanche signal discrimination module generates an avalanche discrimination output signal to the D flip-flop pulse shaping module, the D flip-flop pulse shaping module updates its output and immediately sends one of its output signals as the second dead time control signal to the gating module, thereby causing the avalanche signal processing circuit to enter the disabled state. Then, the main control module outputs the first dead time control signal to the D flip-flop pulse shaping module after a delay, causing it to set, thus enabling the avalanche signal processing circuit to enter the enabled state again. Figure 2 The dead-time control topology shown is mainly designed for gated single-photon detectors, which shortens the gate closing delay time of the gate module. However, it does not propose a design scheme for dead-time control of single-photon detectors in free-running mode, and this topology cannot realize the active dead-time configuration function in the absence of avalanche signals.

[0006] Therefore, in existing single-photon detector systems with dead-time control, the dead-time control signal must be processed by the main control module before it can be generated or set. This internal processing by the main control module introduces a delay, preventing the avalanche current of the single-photon avalanche diode in free-running mode from being actively quenched most quickly, resulting in a more severe afterpulse effect. Simultaneously, the minimum pulse width of the dead-time control signal is limited by the processing clock frequency of the main control module, thus restricting the maximum saturation count rate of the single-photon detector in applications requiring active dead-time control. Furthermore, solutions that can shorten the dead-time control delay are only applicable to gated single-photon detectors and cannot achieve active dead-time configuration in the absence of an avalanche signal. Summary of the Invention

[0007] To address the aforementioned deficiencies identified in the research, this invention discloses a single-photon detector system with low-latency active dead-time configuration. This system can be applied to quantum communication, single-photon lidar, and other applications. By setting up a logic gate module, a third dead-time control signal is obtained through logic gate operations on the first dead-time control signal directly output from the avalanche signal discrimination module and the second dead-time control signal actively configured by the main control module. This signal controls the dead-time of the single-photon detector. Therefore, the avalanche current can be actively quenched directly using the control signal with minimal transmission delay directly output from the avalanche signal discrimination module. This effectively reduces the delay time from avalanche generation to active quenching, optimizes the post-pulse probability, and improves the detector's maximum saturation count rate. Simultaneously, it supports active dead-time configuration, thus achieving low-latency dead-time control with active configuration capabilities in the single-photon detector system, making it well-suited for various application scenarios.

[0008] Specifically, this utility model relates to a single-photon detector system with low-latency active configuration of dead time, which includes a single-photon avalanche diode module, an avalanche signal discrimination module, a main control module, a logic gate module and a dead time control module. The single-photon avalanche diode module is configured to generate an avalanche signal in response to the input of a single-photon signal; The avalanche signal discrimination module is configured to discriminate the avalanche signal and output a detection signal and a first dead time control signal in response to the discriminated avalanche signal; The main control module is configured to generate and output a second dead time control signal, as well as to identify and / or count the detection signal; The logic gate module is connected to the avalanche signal discrimination module and the main control module respectively, and is configured to output a third dead time control signal to the dead time control module by means of logic gate operation when either the first dead time control signal or the second dead time control signal exists. The dead time control module is configured to output an effective dead time signal to the single-photon avalanche diode module in response to the third dead time control signal, so that it enters the dead time.

[0009] Furthermore, the avalanche signal discrimination module is configured to broaden the discriminated avalanche signal to generate two signals, which are used as the detection signal and the first dead time control signal, respectively.

[0010] Furthermore, the main control module is configured to actively or based on the triggering of the detection signal to generate and output the second dead time control signal.

[0011] Furthermore, the logic gate module is configured to generate the third dead time control signal based on logic gate operations on the first dead time control signal and the second dead time control signal.

[0012] Preferably, the logic gate operation is a "NOR" logic gate operation, and the third dead time control signal is a logic low level. The single-photon avalanche diode module is configured such that its anode is connected to a negative voltage, and its cathode is connected to the dead time control module to receive the effective dead time signal.

[0013] Preferably, the logic gate operation is an "OR" logic gate operation, and the third dead time control signal is a logic high level. The single-photon avalanche diode module is configured such that its cathode is connected to a positive voltage, and its anode is connected to the dead time control module to receive the effective dead time signal.

[0014] Optionally, the pulse width of the second dead time control signal is configured to zero or another value.

[0015] Furthermore, in response to the effective dead time signal, the reverse bias voltage across the single-photon avalanche diode module is lower than the avalanche breakdown voltage. Attached Figure Description

[0016] The specific embodiments of this utility model will be further described in detail below with reference to the accompanying drawings.

[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A dead-time signal control topology in the prior art is schematically illustrated; Figure 2 This schematically illustrates a dead-time control scheme for gated single-photon detectors in the prior art; Figure 3 An example of a single-photon detector system with low-latency, actively configurable dead time according to the present invention is illustrated schematically. Detailed Implementation

[0019] In the following description, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example to fully convey the spirit of the present invention to those skilled in the art. Therefore, the present invention is not limited to the embodiments disclosed herein.

[0020] Figure 3 An example of a single-photon detector system with low-latency, actively configurable dead time according to the present invention is illustrated schematically.

[0021] like Figure 3 As shown, the single-photon detector system of this invention may include a single-photon avalanche diode module, an avalanche signal discrimination module, a main control module, a logic gate module, and a dead time control module, etc.

[0022] The single-photon avalanche diode module is configured to absorb single-photon signals and generate an avalanche signal in response to the input of a single-photon signal. Therefore, in operation, the reverse bias voltage across the single-photon avalanche diode is configured to be higher than the avalanche breakdown voltage, in "Gieg mode," so as to generate a macroscopically measurable avalanche signal when absorbing a single-photon signal.

[0023] The avalanche signal discrimination module is connected to the single-photon avalanche diode module to receive the avalanche signal generated by the single-photon avalanche diode in response to the single-photon signal, discriminate the avalanche signal, and output a first dead time control signal in response to the discriminated avalanche signal for use in the dead time process corresponding to the current avalanche signal.

[0024] The application of this first dead time control signal in dead time control differs from that in the prior art, where it is processed by the main control module (which has a certain processing delay) before being used for dead time control. Instead, it is directly applied to dead time control after being output by the avalanche signal discrimination module and processed by the simplest logic gate operation. This allows it to participate in the dead time control process with minimal delay. The specific implementation method will be further explained below.

[0025] In this invention, the avalanche signal discrimination module outputs a first dead time control signal in response to the discrimination of avalanche signals. At the same time, in order to realize the single-photon detection function, it also outputs a detection signal for subsequent functions such as identification and counting of single-photon signals.

[0026] Preferably, in this invention, the avalanche signal discrimination module can output two signals after avalanche signal discrimination and broadening. One signal is used as a first dead time control signal, and the other is used as a detection signal. In this case, the avalanche signal discrimination module is actually an avalanche signal discrimination and broadening module, such as... Figure 3 As shown.

[0027] like Figure 3 As shown, in this invention, the main control module is connected to the avalanche signal discrimination module, receiving the detection signal output by the module and identifying and / or counting the detection signal to enable the detection of single-photon signals. Simultaneously, the main control module is also configured to flexibly generate a second dead-time control signal to achieve active control of the dead time of the single-photon detector.

[0028] In the main control module of this invention, various parameters of the second dead time control signal can be reasonably configured, including but not limited to pulse width and generation time, to generate a second dead time control signal that is suitable for different application scenarios. For example, for application scenarios with high requirements for saturation count rate, the pulse width of the second dead time control signal can be configured to zero, that is, only the first dead time control signal generated by avalanche signal discrimination (broadening) is used for the dead time control of the single-photon detector, so as to maximize the saturation count rate.

[0029] Therefore, the main control module of this utility model can either actively configure and generate the output second dead time control signal, or it can generate the output second dead time control signal based on the triggering of the detection signal, thereby providing a richer dead time control method.

[0030] See also Figure 3In addition to setting the main control module to output a second dead-time control signal to provide active control over the dead time of the single-photon detector, and setting the avalanche signal discrimination module to output a first dead-time control signal to directly participate in the dead-time control process to reduce dead-time control delay, this invention's single-photon detector system also includes a logic gate module for performing logic gate operations on the first and second dead-time control signals. This specific logic gate operation generates a third dead-time control signal, allowing the dead-time control module to respond to the third dead-time control signal and output an effective dead-time signal to the single-photon avalanche diode module, causing it to enter the dead time (during which the reverse bias voltage across the single-photon avalanche diode module will be lower than the avalanche breakdown voltage). This enables active control of the single-photon detector's dead time with minimal control delay.

[0031] Specifically, the logic gate module of this invention can be configured to output a third dead time control signal when either the first or second dead time control signal is present (i.e., within the maximum time range covered by the two dead time control signals) through logic gate operations using the first and second dead time control signals. This allows the single-photon detector to enter the dead time at the latest in response to the first dead time control signal (i.e., allowing the dead time control of the single-photon detector to have a minimum delay), while allowing the dead time length to be controlled by the second dead time control signal (i.e., allowing active control of the dead time of the single-photon detector). This solves the problem in the prior art that low delay and active control of dead time control cannot be achieved simultaneously.

[0032] See also Figure 3 The logic gate module of this utility model can be implemented by using "NOR" logic gates or "OR" logic gates. The selection of "NOR" or "OR" gates can be mainly determined based on the logic level requirements of the dead time control module for the third dead time control signal.

[0033] For example, when the dead-time control module is configured such that its output dead-time signal acts on the anode of a single-photon avalanche diode (i.e., a dead-time signal is applied to it), and correspondingly, the cathode of the single-photon avalanche diode is connected to a positive voltage (i.e., a positive high voltage is applied), since the reverse bias voltage across the single-photon avalanche diode can only be lower than the avalanche breakdown voltage and enter the dead time when the dead-time signal is at a logic high level, the logic level of the third dead-time control signal must be at a logic high level for the dead-time control module to generate a valid dead-time signal accordingly. In this case, the logic gate module can be implemented using an "OR" logic gate, so that the presence of either the first or second dead-time control signal will generate a logic high-level third dead-time control signal.

[0034] For example, when the dead time control module is configured so that its output dead time signal acts on the cathode of a single-photon avalanche diode (i.e., it is subjected to a dead time signal), and correspondingly, the anode of the single-photon avalanche diode is connected to a negative voltage (i.e., is subjected to a negative high voltage), since the reverse bias voltage across the single-photon avalanche diode can only be lower than the avalanche breakdown voltage and enter the dead time when the dead time signal is at a logic low level, the logic level of the third dead time control signal must be at a logic low level for the dead time control module to generate a valid dead time signal accordingly. In this case, the logic gate module can be implemented using "OR" logic gates, so that the presence of either the first or second dead time control signal can generate a logic low third dead time control signal.

[0035] To better understand the above, the truth tables for the first, second, and third dead-time control signals and dead-time signal states corresponding to different logic gate modules are provided below:

[0036] (Logic "1" represents a logic high level, and logic "0" represents a logic low level.) In response to the third dead-time control signal output by the logic gate module, the dead-time control module can output a valid dead-time signal, for example, when either the first or second dead-time control signal is present. By acting on, for example, a single-photon avalanche diode, this signal can lower the reverse bias voltage across the single-photon avalanche diode below the avalanche breakdown voltage, thus actively quenching the avalanche current and controlling the single-photon avalanche diode to exit "linear mode." When the dead-time signal is in an invalid state, the reverse bias voltage across the single-photon avalanche diode is actively restored, re-entering "Gegege mode" to prepare for single-photon detection, thereby achieving dead-time control of the single-photon detector.

[0037] As described above, in the single-photon detector system of this invention, by setting a logic gate module, a third dead-time control signal is obtained through logic gate operations on the first dead-time control signal directly output from the avalanche signal discrimination module and the second dead-time control signal actively configured by the main control module. This achieves the required dead-time control. Therefore, the avalanche current can be actively quenched directly using the control signal with minimal transmission delay directly output by the avalanche signal discrimination module. This effectively reduces the delay time from avalanche generation to active quenching, optimizes the post-pulse probability, and improves the maximum saturation count rate of the detector. Simultaneously, it supports active dead-time configuration, enabling low-latency active dead-time configuration. This allows the single-photon detector system to adapt well to the dead-time requirements of various application scenarios. For example, in applications with high saturation count rate requirements, this invention allows for flexible setting of the pulse width of the second dead-time control signal output by the main control module after an avalanche detection event to zero, using only the first dead-time control signal obtained after avalanche signal discrimination (broadening) for dead-time control, maximizing the saturation count rate. For example, this invention can enable the main control module to control the operating state of the single-photon avalanche diode through an active dead-time control signal, thereby reducing the impact of stray light with known timing on the performance of the single-photon detector.

[0038] Although the present invention has been described above with reference to the accompanying drawings and specific embodiments, those skilled in the art will readily recognize that the above embodiments are merely exemplary and used to illustrate the principles of the present invention. They do not limit the scope of the present invention. Those skilled in the art can make various combinations, modifications and equivalent substitutions to the above embodiments without departing from the spirit and scope of the present invention.

Claims

1. A single-photon detector system with low-latency, actively configurable dead time, characterized in that, It includes a single-photon avalanche diode module, an avalanche signal discrimination module, a main control module, a logic gate module, and a dead time control module; The single-photon avalanche diode module is configured to generate an avalanche signal in response to the input of a single-photon signal; The avalanche signal discrimination module is configured to discriminate the avalanche signal and output a detection signal and a first dead time control signal in response to the discriminated avalanche signal; The main control module is configured to generate and output a second dead time control signal, as well as to identify and / or count the detection signal; The logic gate module is connected to the avalanche signal discrimination module and the main control module respectively, and is configured to output a third dead time control signal to the dead time control module by means of logic gate operation when either the first dead time control signal or the second dead time control signal exists. The dead time control module is configured to output an effective dead time signal to the single-photon avalanche diode module in response to the third dead time control signal, so that it enters the dead time.

2. The single-photon detector system as described in claim 1, characterized in that, The avalanche signal discrimination module is configured to broaden the discriminated avalanche signal to generate two signals, which are used as the detection signal and the first dead time control signal, respectively.

3. The single-photon detector system as described in claim 2, characterized in that, The main control module is configured to actively or based on the triggering of the detection signal to generate and output the second dead time control signal.

4. The single-photon detector system as described in claim 1, characterized in that, The logic gate module is configured to generate the third dead time control signal based on logic gate operations on the first dead time control signal and the second dead time control signal.

5. The single-photon detector system as described in claim 4, characterized in that, The logic gate operation is a "OR" logic gate operation, and the third dead time control signal is a logic low level.

6. The single-photon detector system as described in claim 5, characterized in that, The single-photon avalanche diode module is configured such that its anode is connected to a negative voltage and its cathode is connected to the dead time control module to receive the effective dead time signal.

7. The single-photon detector system as described in claim 4, characterized in that, The logic gate operation is an "OR" logic gate operation, and the third dead time control signal is a logic high level.

8. The single-photon detector system as described in claim 7, characterized in that, The single-photon avalanche diode module is configured such that its cathode is connected to a positive voltage and its anode is connected to the dead time control module to receive the effective dead time signal.

9. The single-photon detector system as described in claim 1, characterized in that, The pulse width of the second dead time control signal is configured to zero or another value.

10. The single-photon detector system as described in any one of claims 1-9, characterized in that, In response to the effective dead time signal, the reverse bias voltage across the single-photon avalanche diode module is lower than the avalanche breakdown voltage.

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