An integrating sphere-based light testing system and testing system

Abstract

The utility model discloses a kind of light testing system and test system based on integrating sphere, and light testing system includes integrating sphere, chip bearing station, first power supply device, second power supply device and light detection device: integrating sphere includes detachably connected upper shell and lower shell, upper shell is provided with first through-hole, lower shell is provided with second through-hole and third through-hole;Chip bearing station is set in lower shell, for placing the light chip to be measured;The first probe of first power supply device passes through second through-hole and is coupled with first pad, and the second probe of second power supply device passes through third through-hole and is coupled with second pad;First power supply device and second power supply device are respectively used to provide electrical signal to the light chip to be measured, so that the light chip to be measured emits light;Light detection device is set in first through-hole, for testing the light emitted by the light chip to be measured.The utility model does not need to carry out wire bonding, dismounting and other steps to unpackaged chip, reduce chip test loss rate, while reducing chip sample consumption.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to an optical testing system and testing system based on an integrating sphere. Background Technology

[0002] Traditional integrating spheres, as core devices in the field of optical measurement used to detect key optical parameters such as luminous flux, color temperature, and color rendering index of light sources, operate on the premise of a stable connection between the light source and the power supply.

[0003] From an application perspective, the traditional integrating sphere was originally designed to adapt to mature light source products and pre-packaged chips that have already achieved standardized packaging. Mature light source products can be directly connected to power for testing, and most pre-packaged chips (such as LED chips with standard pins and interfaces) can be quickly connected to power for testing via standard interfaces or adapters. However, some pre-packaged chips are customized chips with non-standard interfaces (such as chips with irregularly shaped pins), which require additional customized adapters to connect to power for testing, resulting in higher testing costs and more complex operations.

[0004] However, using traditional integrating spheres to test unpackaged chips (such as Micro-LED bare dies) presents significant limitations due to the small size of unpackaged chips and their lack of standardized power interfaces common to traditional light sources. These limitations include: (1) Since unpackaged chips lack a standard power interface, if optical testing is to be performed on a traditional integrating sphere, extremely fine power lines (usually gold or copper wires with a diameter of 0.01-0.05 mm) must be precisely soldered to the positive and negative pins of the unpackaged chip by manual wire bonding to establish a circuit connection between the chip and the external power supply. After the wire bonding is completed, the unpackaged chip with the power lines must be fixed on a special fixture and then placed into the test area inside the integrating sphere. On the one hand, the unpackaged chip is small in size and fragile in structure, and the wire bonding operation requires high-precision equipment and experienced operators. Slight carelessness may cause damage to the chip electrodes. On the other hand, after the wire bonding is completed, the connection point between the power lines and the chip pins is extremely weak. During the process of transferring the chip to the integrating sphere, adjusting the test position, or removing it later, slight external force pulling (such as airflow disturbance or slight shaking of the fixture) may cause the power lines to break or even cause the solder joints to detach.

[0005] (2) The wire bonding operation performed to achieve power connection will have an irreversible impact on the original structure and performance of the unpackaged chip. The chip after wire bonding cannot be restored to its original unpackaged state. This means that after completing the traditional integrating sphere luminous flux and other parameter tests, the same batch of chips cannot be used for subsequent reliability tests (such as high and low temperature cycling, damp heat aging), electrical performance tests (such as volt-ampere characteristics, reverse leakage current) or packaging process verification, which is detrimental to the continuity of experiments. Utility Model Content

[0006] The purpose of this invention is to provide an integrating sphere-based optical testing system and testing system to solve the problem of chip damage caused when using a traditional integrating sphere to perform optical testing on unpackaged micro-chips (such as Micro-LED chips).

[0007] The objective of this utility model is achieved through the following technical solution: This utility model provides an optical testing system based on an integrating sphere, comprising: An integrating sphere includes an upper shell and a lower shell, which are connected to each other to form a hollow cavity. The upper shell is provided with a first through hole, and the lower shell is provided with a second through hole and a third through hole. A chip carrier stage is used to place the optical chip under test, which is disposed inside the lower housing; the light-emitting surface of the optical chip under test is provided with a first pad and a second pad; A first power supply device includes a first probe; The second power supply device includes a second probe; A light detection device is disposed in the first through hole; the light detection device is used to test the light emitted by the optical chip under test; The first probe passes through the second through-hole and is coupled to the first pad, and the second probe passes through the third through-hole and is coupled to the second pad; the first power supply device and the second power supply device are respectively used to provide electrical signals to the optical chip under test so that the optical chip under test emits light.

[0008] As a further improvement of one embodiment of this utility model, the optical chip to be tested is an unpackaged chip.

[0009] As a further improvement of one embodiment of this utility model, the optical chip to be tested is a packaged chip.

[0010] As a further improvement of one embodiment of the present invention, the first probe is fixedly connected to a first light-shielding plate near the second through hole. The side of the first light-shielding plate facing the second through hole is also connected to the inner side wall of the lower housing located around the second through hole. The first light-shielding plate is used to prevent the light emitted by the light chip under test from escaping from the second through hole. The second probe is fixedly connected to a second light-shielding plate near the third through hole. The side of the second light-shielding plate facing the third through hole is also connected to the inner side wall of the lower housing located around the third through hole. The second light-shielding plate is used to prevent the light emitted by the optical chip under test from escaping from the third through hole.

[0011] As a further improvement of one embodiment of the present invention, the upper shell and the lower shell are provided with a first end face and a second end face facing each other respectively. The first end face and the second end face are both provided with a wave-shaped structure, and when the upper shell and the lower shell are connected, the first end face and the second end face fit together.

[0012] As a further improvement of one embodiment of the present utility model, a plurality of first locking structures are uniformly arranged in the circumferential area of ​​the outer side wall of the upper shell near the first end face, and a plurality of second locking structures are uniformly arranged in the circumferential area of ​​the outer side wall of the lower shell near the second end face, wherein the first locking structure and the second locking structure correspond one-to-one. The optical testing system also includes multiple fasteners that correspond one-to-one with the first locking structure. When the upper housing and the lower housing are connected, the fasteners pass through the corresponding first locking structure and second locking structure to fix the relative positions of the upper housing and the lower housing.

[0013] As a further improvement of one embodiment of the present invention, the center of the first through hole is located on the central axis of the upper housing, and the center of the chip carrier is located on the central axis of the lower housing; And / or, the second through hole and the third through hole are symmetrically arranged relative to the chip carrier platform; And / or, the second through hole and the third through hole are higher than the chip carrier stage.

[0014] As a further improvement of one embodiment of this utility model, the inner diameter of the integrating sphere is 8cm-12cm, the relative distance between the side of the chip carrier platform facing the upper housing and the center of the bottom end of the lower housing is 2cm-5cm, and the relative distance between the center of the second through hole and the center of the third through hole and the center of the bottom end of the lower housing is 3.5cm-4.25cm respectively. And / or, the diameter of the first through hole is 1cm-3cm; And / or, the diameters of the second through hole and the third through hole are both 0.4cm-0.6cm.

[0015] As a further improvement of one embodiment of the present invention, the optical detection device has an optical interface, and a threaded interface is sealed and connected to the first through hole, and the optical interface is threadedly connected to the threaded interface. And / or, the optical testing system further includes light-blocking plates, which are spaced apart directly below the first through hole; And / or, the first probe extends through the second through-hole into the lower housing, and the first probe is movable such that the tip of the first probe connects to the first pad; the second probe extends through the third through-hole into the lower housing, and the second probe is movable such that the tip of the second probe connects to the second pad; And / or, the size of the optical chip under test is less than 70 μm.

[0016] This utility model also provides a testing system, which includes a power supply device and an integrating sphere-based optical testing system as described above. The first probe and the second probe are respectively coupled to the power supply device. The first probe is used to transmit a first electrical signal output by the power supply device to the first pad, and the second probe is used to transmit a second electrical signal output by the power supply device to the second pad.

[0017] As a further improvement of one embodiment of the present invention, the chip carrier stage is provided with a plurality of adsorption holes on one side facing the upper housing, and the testing system further includes a vacuum device, the vacuum pipe of the vacuum device being connected to the adsorption holes; And / or, the testing system further includes an operating table, on which the lower housing, the first power supply device, and the second power supply device are fixed; the testing system further includes an image observation device, which is fixed on the operating table and is used to observe the position of the optical chip under test, the first probe, and the second probe before the upper housing is closed on the lower housing.

[0018] As a further improvement of one embodiment of the present invention, the testing system further includes a processor and a display coupled to each other. The processor is coupled to the light detection device and is used to acquire and process the light test data obtained by the light detection device. The display is used to display the light test data processed by the processor.

[0019] Compared with the prior art, the beneficial effects of this utility model include at least the following: This utility model provides an optical testing system based on an integrating sphere, which includes an integrating sphere, a chip carrier stage, a first power supply device, a second power supply device, and a light detection device. The integrating sphere includes an upper shell and a lower shell, which are connected to each other to form a hollow cavity. The upper shell is provided with a first through hole, and the lower shell is provided with a second through hole and a third through hole. The chip carrier stage is used to place the optical chip under test and is disposed in the lower shell. The first power supply device includes a first probe, and the second power supply device includes a second probe. The light detection device is disposed in the first through hole and is used to test the light emitted by the optical chip under test. The first probe passes through the second through hole and is coupled to a first pad, and the second probe passes through the third through hole and is coupled to a second pad. The first power supply device and the second power supply device are respectively used to provide electrical signals to the optical chip under test so that the optical chip under test emits light. Compared to testing unpackaged chips using traditional integrating spheres, the optical testing system provided by this invention can not only test unpackaged optical chips under test, but also eliminate the need for complex steps such as wire bonding and desoldering during the entire testing process. This maximizes the protection of the structural and performance integrity of the optical chip under test, significantly reduces chip testing loss rate, reduces chip sample consumption, and lowers testing costs. Furthermore, this solution can also test packaged chips, making it more adaptable. Attached Figure Description Figure 1 This is a schematic diagram of the structure of an optical testing system according to one embodiment of the present invention; Figure 2 This is a cross-sectional view of an upper shell according to one embodiment of the present utility model; Figure 3 This is a schematic diagram of the structure of a lower shell according to one embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a lower housing according to one embodiment of the present invention (showing the chip carrier and the second power supply device). Figure 5 This is a top view of an upper shell according to one embodiment of the present utility model; Figure 6 This is a structural schematic diagram of a first power supply device / second power supply device according to one embodiment of the present utility model; Figure 7 This is a schematic diagram of the structure of an integrating sphere according to one embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of an image observation device according to one embodiment of the present invention; Figure 9This is a schematic diagram of the structure of a testing system according to one embodiment of the present invention (the upper shell is closed before the lower shell, and the image observation device is shown).

[0020] In the diagram: 1. Integrating sphere; 11. Upper housing; 111. First through hole; 112. First end face; 113. First locking structure; 114. Fastener; 12. Lower housing; 121. Second through hole; 122. Third through hole; 123. Second end face; 124. Second locking structure; 2. Chip carrier platform; 21. Support part; 22. Carrier part; 3. First power supply device; 31. First probe holder; 32. First probe; 4. Second power supply device; 41. Second probe holder; 42. Second probe; 5. Light detection device; 61. First light shield; 62. Second light shield; 7. Image observation equipment; 71. Adjustment device; 72. Image magnification device; 73. Light source; 74. Handle; 8. Light blocking plate; 9. Processor; 10. Display. Detailed Implementation

[0021] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted.

[0022] The terms used to describe position and direction in this utility model are illustrated with the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of this utility model.

[0023] See also Figures 1-7 This utility model provides an optical testing system based on an integrating sphere, which includes an integrating sphere 1, a chip carrier stage 2, a first power supply device 3, a second power supply device 4, and a light detection device 5.

[0024] like Figure 1 As shown, the integrating sphere 1 includes a detachably connected upper shell 11 and a lower shell 12, which are connected to each other to form a hollow cavity. The upper shell 11 and the lower shell 12 are hemispherical shells with the same shape and size. When the upper shell 11 and the lower shell 12 are connected, the upper shell 11 is located directly above the lower shell 12, and the hollow cavity formed by the connection of the upper shell 11 and the lower shell 12 is a hollow sphere. The center of the hollow sphere is located in the plane where the connection between the upper shell 11 and the lower shell 12 is located.

[0025] Specifically, the inner diameter of the integrating sphere 1 is 8cm-12cm, meaning that the inner wall diameter of both the upper shell 11 and the lower shell 12 is 8cm-12cm. For example, the inner diameter of the integrating sphere 1 can be 8cm, 8.3cm, 8.5cm, 8.8cm, 9cm, 9.3cm, 9.5cm, 9.8cm, 10cm, 10.3cm, 10.5cm, 10.8cm, 11cm, 11.3cm, 11.5cm, 11.8cm, or 12cm.

[0026] like Figures 1 to 3 As shown, the upper housing 11 is provided with a first through hole 111, and the lower housing 12 is provided with a second through hole 121 and a third through hole 122. The first through hole 111 is used to install the photodetector 5, the second through hole 121 is used to install the first power supply device 3, and the third through hole 122 is used to install the second power supply device 4.

[0027] Specifically, the diameter of the first through hole 111 is 1cm-3cm. For example, the diameter of the first through hole 111 can be 1cm, 1.3cm, 1.5cm, 1.8cm, 2cm, 2.3cm, 2.5cm, 2.8cm or 3cm.

[0028] Specifically, the diameters of the second through hole 121 and the third through hole 122 are both 0.4cm-0.6cm. For example, the diameters of the second through hole 121 and the third through hole 122 can be 0.4cm, 0.43cm, 0.45cm, 0.48cm, 0.5cm, 0.53cm, 0.55cm, 0.58cm or 0.6cm.

[0029] See Figure 2 and Figure 3 The upper housing 11 and the lower housing 12 are provided with a first end face 112 and a second end face 123 facing each other, respectively. Both the first end face 112 and the second end face 123 are designed with a wavy structure. When the upper housing 11 and the lower housing 12 are connected, the first end face 112 and the second end face 123 fit together, that is, the wavy structure of the first end face 112 and the wavy structure of the second end face 123 are complementary. Specifically, the cross-section of the first end face 112 and the second end face 123 along the vertical plane is a wavy structure. In this way, when the upper housing 11 and the lower housing 12 are assembled together, the first end face 112 and the second end face 123 can "interlock" with each other, which can further prevent the light emitted by the optical chip under test from escaping from the integrating sphere 1.

[0030] For example, the first end face 112 and the second end face 123 can be configured as wavy surfaces with a "sin" shape. Here, "sin" shape refers to the shape of the sine curve corresponding to the sine function.

[0031] like Figure 4As shown, the chip carrier stage 2 is used to place the optical chip under test, and it is disposed inside the lower housing 12. The chip carrier stage 2 includes a support part 21 and a carrier part 22 fixedly connected. The support part 21 is fixedly connected to the inner sidewall of the lower housing 12, and the carrier part 22 is located above the support part 21. The light-emitting surface of the optical chip under test is provided with a first pad and a second pad, which can be positive and negative electrodes, respectively. When the optical chip under test is placed on the chip carrier stage 2, the light-emitting surface of the optical chip under test is the side of the optical chip facing away from the chip carrier stage 2.

[0032] In one embodiment, the optical chip to be tested can be a packaged chip, such as a packaged chip with a non-standard interface or irregular package. After packaging, there are no general pins, and only tiny test pads (i.e., the first pad and the second pad) are reserved on the package surface.

[0033] In another embodiment, the light chip to be tested can be an unpackaged chip, such as an unpackaged Micro-LED (micro light-emitting diode) chip, OLED (organic light-emitting diode) chip, or QLED (quantum dot light-emitting diode) chip.

[0034] Compared to manual wire bonding, the optical testing system provided by this invention can directly test unpackaged chips without the need for manual wire bonding, simplifying operation. Furthermore, since the unpackaged chip under test is first placed in an integrating sphere and then electrically connected using two probes (i.e., the first probe and the second probe), adverse consequences (such as power cable breakage or solder joint detachment) caused by external force during various stages (e.g., transferring the chip to the integrating sphere, adjusting the test position, or subsequent removal) are avoided. This eliminates the need for repeated wire bonding, improving testing efficiency and convenience. Moreover, because manual wire bonding and desoldering of the unpackaged chip are eliminated, there is no irreversible impact on the original structure and performance of the unpackaged chip under test, allowing for direct subsequent reliability testing and reducing chip testing loss rate.

[0035] In one embodiment, the size of the optical chip under test is less than 70 μm. Understandably, the size of the optical chip under test can also be greater than 70 μm, for example, 80 μm, as long as the integrating sphere 1 can accommodate it.

[0036] In this embodiment, the support portion 21 is a support column, which includes a lower end face fixedly connected to the inner wall of the lower housing 12 and an upper end face fixedly connected to the support portion 22. The support portion 22 is a support platform fixed to the upper end face of the support column, and the upper end face of the support column is located at the center of the support platform. The side of the support portion 22 facing away from the support portion 21 is a support surface, which is used to place the optical chip under test. Of course, the size of the support surface is larger than the size of the optical chip under test, that is, when the optical chip under test is placed on the support surface, the projection of the optical chip under test on the support surface falls completely into the support surface.

[0037] Specifically, the relative distance between the side of the chip carrier 2 facing the upper housing 11 and the center of the bottom end of the lower housing 12 is 2cm-5cm, that is, the relative distance between the bearing surface of the chip carrier 2 and the center of the bottom end of the lower housing 12 is 2cm-5cm. For example, the relative distance between the side of the chip carrier 2 facing the upper housing 11 and the center of the bottom end of the lower housing 12 can be 2cm, 2.3cm, 2.5cm, 2.8cm, 3cm, 3.3cm, 3.5cm, 3.8cm, 4cm, 4.3cm, 4.5cm, 4.8cm or 5cm.

[0038] Combination Figure 6The first power supply device 3 includes a first probe holder 31 and a first probe 32 connected to the first probe holder 31. The first probe holder 31 is used to support the first probe 32 and adjust the position of the first probe 32. The first probe 32 passes through the second through hole 121 and is coupled to the first pad of the optical chip under test. That is, the first probe 32 extends through the second through hole 121 into the lower housing 12. The first probe 32 can be moved so that the tip of the first probe 32 connects to the first pad. Specifically, the position of the first probe 32 in the lower housing 12 can be adjusted by adjusting the first probe holder 31 so that the tip of the first probe 32 contacts the first pad of the optical chip under test. The second power supply device 4 includes a second probe holder 41 and a second probe 42 connected to the second probe holder 41. The second probe holder 41 is used to support the second probe 42 and adjust the position of the second probe 42. The second probe 42 passes through the third through hole 122 and is coupled to the second pad of the optical chip under test. That is, the second probe 42 extends through the third through hole 122 into the lower housing 12. The second probe 42 can be moved so that the tip of the second probe 42 connects to the second pad. Specifically, the position of the second probe 42 in the lower housing 12 can be adjusted by adjusting the second probe holder 41 so that the tip of the second probe 42 contacts the second pad of the optical chip under test. In actual operation, the position of the first probe 32 is adjusted by the first probe holder 31 so that the first probe 32 moves to contact the surface of the first pad and slides a distance on the surface of the first pad, ensuring stable contact between the first probe 32 and the first pad and allowing the first probe 32 to apply a first electrical signal to the first pad. Similarly, the position of the second probe 42 is adjusted by the second probe holder 41 so that the second probe 42 moves to contact the surface of the second pad and slides a distance on the surface of the second pad, ensuring stable contact between the second probe 42 and the second pad and allowing the second probe 42 to apply a second electrical signal to the second pad.

[0039] In this embodiment, both the first probe holder 31 and the second probe holder 41 are mechanical adjustment devices. Specifically, the positions of the first probe 32 and the second probe 42 on the X-axis, Y-axis and Z-axis can be adjusted by different knobs set on the first probe holder 31 and the second probe holder 41, respectively.

[0040] The first power supply device 3 and the second power supply device 4 are respectively used to provide electrical signals to the optical chip under test, that is, the first power supply device 3 and the second power supply device 4 are respectively connected to an external power supply device. Specifically, the first probe holder 31 is provided with a first conductive structure, which is used to electrically connect with the first probe 32. The first probe holder 31 is also provided with a first external wiring port for connecting the first conductive structure. By connecting the first external wiring port to the external power supply device, the external power supply device can transmit a first electrical signal to the first probe 32. Similarly, the second probe holder 41 is provided with a second conductive structure, which is used to electrically connect with the second probe 42. The second probe holder 41 is also provided with a second external wiring port for connecting the second conductive structure. By connecting the second external wiring port to the external power supply device, the external power supply device can transmit a second electrical signal to the second probe 42. In this way, the first electrical signal is applied to the first pad by the first probe 32, and the second electrical signal is applied to the second pad by the second probe 42, so that the optical chip under test emits light. For example, a positive voltage signal is applied to the first pad (connected to the P-region of the PN junction inside the optical chip under test) via the first probe 32, and a reference voltage signal is applied to the second pad (connected to the N-region of the PN junction inside the optical chip under test) via the second probe 42. This creates a positive bias electric field between the first and second pads, driving current to flow from the first pad through the PN junction inside the optical chip under test to the second pad, forming a closed loop. Under the action of the positive current, holes in the P-region and electrons in the N-region of the PN junction migrate to the depletion region and recombine. The energy released during recombination is output in the form of photons, thereby illuminating the optical chip under test.

[0041] Understandably, the first probe 32 and the second probe 42 can also be directly connected to an external power supply device. That is, the first probe holder 31 does not have a first conductive structure for connecting the first probe 32 to the external power supply, and the second probe holder 41 does not have a second conductive structure for connecting the second probe 42 to the external power supply. The first probe 32 and the second probe 42 are directly connected to the external power supply device via cables.

[0042] In this embodiment, the second through hole 121 and the third through hole 122 are symmetrically arranged relative to the chip carrier 2, and the line connecting the center of the second through hole 121 and the center of the third through hole 122 intersects the extended line of the center of the support portion 21 of the chip carrier 2. That is, the first power supply device 3 and the second power supply device 4 are symmetrically arranged relative to the chip carrier 2.

[0043] In this embodiment, the second through-hole 121 and the third through-hole 122 are higher than the chip carrier stage 2, that is, the center of the second through-hole 121 and the center of the third through-hole 122 are both higher than the carrier surface of the carrier portion 22. When the optical chip under test is placed on the carrier surface, the initial positions of the first probe 32 and the second probe 42 are both higher than the optical chip under test, which makes it easier to control the first probe holder 31 to adjust the position of the first probe 32 so that the first probe 32 is coupled to the first pad, and to control the second probe holder 41 to adjust the position of the second probe 42 so that the second probe 42 is coupled to the second pad.

[0044] Specifically, the relative distances between the centers of the second through hole 121 and the third through hole 122 and the center of the bottom end of the lower housing 12 are 3.5cm-4.25cm. For example, the relative distances between the centers of the second through hole 121 and the third through hole 122 and the center of the bottom end of the lower housing 12 can be 3.5cm, 3.55cm, 3.6cm, 3.65cm, 3.7cm, 3.75cm, 3.8cm, 3.85cm, 3.9cm, 3.95cm, 4cm, 4.05cm, 4.1cm, 4.15cm, 4.2cm, or 4.25cm.

[0045] For example, the inner diameter of the integrating sphere 1 is 10cm, the relative distance between the side of the chip carrier stage 2 facing the upper housing 11 and the center of the bottom end of the lower housing 12 is 3.5cm, and the relative distance between the centers of the second through hole 121 and the third through hole 122 and the center of the bottom end of the lower housing 12 is 3.75cm. The diameter of the first through hole 111 is 2cm, and the diameters of the second through hole 121 and the third through hole 122 are both 0.5cm.

[0046] Of course, the inner walls of the upper housing 11 and the lower housing 12 are both provided with a high diffuse reflection coating, such as a reflective coating made of barium sulfate, polytetrafluoroethylene, etc., so that when the optical chip under test is lit up and the upper housing 11 and the lower housing 12 are connected to form an integrating sphere 1, the light emitted by the optical chip under test can undergo multiple diffuse reflections on the inner wall surface of the integrating sphere 1, forming a uniform light field in the integrating sphere 1. That is, the light intensity at any position and in any direction in the integrating sphere 1 is basically the same, eliminating the problem of the initial light emission direction difference and intensity unevenness of the optical chip under test.

[0047] A photodetector 5 is disposed within the first through-hole 111. The photodetector 5 is used to receive and test the light emitted by the optical chip under test. Thus, the optical chip under test is placed on the chip carrier stage 2, and the first power supply device 3 and the second power supply device 4 are used to power the optical chip. The light emitted by the optical chip under test undergoes multiple diffuse reflections through the inner wall of the integrating sphere 1, forming a uniform light field inside the integrating sphere 1. The photodetector 5 receives the light signal in the uniform light field and measures its optical parameters (such as luminous flux, operating wavelength, and spectral half-width). In other words, throughout the entire testing process, there is no need for complex steps such as wire bonding and desoldering of the optical chip under test, maximizing the protection of the structural and performance integrity of the unpackaged chip, significantly reducing chip testing loss rate, reducing chip sample consumption, and lowering testing costs.

[0048] Specifically, the light detection device 5 has an optical interface, and a threaded interface is sealed and connected at the first through hole 111. The optical interface and the threaded interface are threadedly connected. When the light chip under test is lit, the light detection device 5 is installed at the first through hole 111. The optical interface of the light detection device 5 completely seals the threaded interface at the first through hole 111, preventing the light emitted by the light chip under test from escaping from the first through hole 111. The threaded interface at the first through hole 111 is a standard interface for a light source receiver, which can be matched with different types of light source receivers.

[0049] The light detection device 5 can be a spectrometer or a photodetector.

[0050] In this embodiment, the center of the first through hole 111 is located on the central axis of the upper housing 11, and the center of the chip carrier 2 is located on the central axis of the lower housing 12. That is, the center of the first through hole 111 is located at the top center of the upper housing 11, and the chip carrier 2 is located directly below the first through hole 111. In other words, in the vertical direction, the center of the projection of the first through hole 111 onto the carrier surface of the chip carrier 2 coincides with the center of the carrier surface. In other words, when the photodetector 5 is installed at the first through hole 111, the optical interface of the photodetector 5 is located directly above the chip carrier 2 (the photodetector chip under test).

[0051] It should be noted that, as Figure 2 As shown, the optical testing system in this embodiment also includes a light-blocking plate 8, which is spaced apart directly below the first through hole 111. The light-blocking plate 8 is used to prevent the optical detection device 5 from directly receiving the direct light emitted by the optical chip under test, and to ensure that the optical detection device 5 receives the uniform diffuse reflected light.

[0052] This invention does not limit the fixing method of the light-blocking plate 8. It can be fixed to the inner wall of the upper housing 11 by a fixing structure, ensuring that the light-blocking plate 8 is fixed parallel to the bottom of the first through hole 111 and has a certain distance from the first through hole 111. Of course, this invention does not limit the shape and size of the light-blocking plate 8, as long as the surface size of the light-blocking plate 8 is larger than the radial size of the first through hole 111; and in the vertical direction, the projection of the first through hole 111 onto the surface of the light-blocking plate 8 falls completely on the surface of the light-blocking plate 8, so as to completely avoid the possibility of the photodetector 5 receiving direct light from the photochip under test.

[0053] Combination Figure 4 and Figure 9 A first light-shielding plate 61 is fixedly connected to the first probe 32 near the second through hole 121. The side of the first light-shielding plate 61 facing the second through hole 121 is also connected to the inner wall of the lower housing 12 located around the second through hole 121. Specifically, the curvature of the side of the first light-shielding plate 61 facing the second through hole 121 matches the curvature of the inner wall of the lower housing 12 located around the second through hole 121. The first light-shielding plate 61 completely blocks the gap between the second through hole 121 and the first probe 32 on the inner wall of the lower housing 12, preventing light emitted by the optical chip under test from escaping through the second through hole 121. A second light-shielding plate 62 is fixedly connected to the second probe 42 near the third through hole 122. The side of the second light-shielding plate 62 facing the third through hole 122 is also connected to the inner wall of the lower housing 12 located around the third through hole 122. Specifically, the curvature of the side of the second light-shielding plate 62 facing the third through hole 122 matches the curvature of the inner wall of the lower housing 12 located around the third through hole 122. The second light-shielding plate 62 completely blocks the gap between the third through hole 122 and the second probe 42 on the inner wall of the lower housing 12, preventing light emitted from the optical chip under test from escaping through the third through hole 122.

[0054] Specifically, the first light-shielding plate 61 and the second light-shielding plate 62 are flexible light-shielding plates. Since the side of the first light-shielding plate 61 facing the second through-hole 121 is fixedly connected to the inner wall of the lower housing 12, it can be stretched and deformed during the adjustment of the position of the first probe 32 using the first probe seat 31. Similarly, since the side of the second light-shielding plate 62 facing the third through-hole 122 is fixedly connected to the inner wall of the lower housing 12, it can be stretched and deformed during the adjustment of the position of the second probe 42 using the second probe seat 41. By making the first light-shielding plate 61 and the second light-shielding plate 62 flexible light-shielding plates, they possess a certain elastic deformation capability, ensuring that the second through-hole 121 and the third through-hole 122 are completely blocked without affecting the movement of the first probe 32 and the second probe 42.

[0055] Of course, it should be noted that in this embodiment, the initial positions of the tip of the first probe 32 and the tip of the second probe 42 are close to the bearing surface of the chip carrier stage 2. That is, in subsequent testing, only a small degree of adjustment is needed to the positions of the first probe 32 and the second probe 42. The deformation of the first light shield 61 and the second light shield 62 during the adjustment of the first probe 32 and the second probe 42 is small.

[0056] In one embodiment, the first light-shielding plate 61 and the second light-shielding plate 62 are made of silicone.

[0057] In another embodiment, the upper housing 11 and the lower housing 12 are made of metal, such as iron or copper, and the first light-shielding plate 61 and the second light-shielding plate 62 are made of soft magnetic material. That is, the side of the first light-shielding plate 61 facing the second through hole 121 is magnetically connected to the inner wall of the lower housing 12 located around the second through hole 121, and the side of the second light-shielding plate 62 facing the third through hole 122 is magnetically connected to the inner wall of the lower housing 12 located around the third through hole 122.

[0058] Further, see Figures 3-5 , Figure 7 The outer side wall of the upper housing 11 has a plurality of first locking structures 113 evenly arranged in the circumferential area near the first end face 112, and the outer side wall of the lower housing 12 has a plurality of second locking structures 124 evenly arranged in the circumferential area near the second end face 123. The first locking structures 113 and the second locking structures 124 correspond one-to-one. The optical testing system also includes a plurality of fasteners 114 corresponding one-to-one with the first locking structures 113. When the upper housing 11 and the lower housing 12 are connected, the fasteners 114 pass through the corresponding first locking structures 113 and second locking structures 124 to fix the relative positions of the upper housing 11 and the lower housing 12.

[0059] In this embodiment, the number of first locking structures 113 and second locking structures 124 is set to four. The four first locking structures 113 are evenly distributed on the outer side wall of the upper housing 11, that is, the angle formed by the line connecting two adjacent first locking structures 113 and the center of the integrating sphere is 90°; the four second locking structures 124 are evenly distributed on the outer side wall of the lower housing 12, that is, the angle formed by the line connecting two adjacent second locking structures 124 and the center of the integrating sphere is 90°.

[0060] In this embodiment, the number of fasteners 114 is also set to four, and the fasteners 114 can be bolts. The first locking structure 113 and the second locking structure 124 are also provided with threaded structures that cooperate with the bolts.

[0061] Of course, this utility model does not limit the number of the first locking structure 113, the second locking structure 124 and the fastener 114, or the type of the fastener 114, as long as the fastener 114 can fix the first locking structure 113 and the second locking structure 124.

[0062] This utility model also provides a testing system, which includes a power supply device and an optical testing system based on an integrating sphere as described in any of the above embodiments. The first probe 32 and the second probe 42 are respectively coupled to the power supply device. Specifically, the first probe 32 and the second probe 42 are respectively signal connected to the power supply device. The first probe 32 is used to transmit the first electrical signal output by the power supply device to the first pad, and the second probe 42 is used to transmit the second electrical signal output by the power supply device to the second pad.

[0063] In this embodiment, the power supply device is a source meter. The source meter transmits a first electrical signal to the first probe 32 and a second electrical signal to the second probe 42. The first probe 32 transmits the first electrical signal to the first pad, and the second probe 42 transmits the second electrical signal to the second pad.

[0064] Furthermore, in this embodiment, the testing system also includes a vacuum device. The chip carrier 2 has multiple adsorption holes on one side (i.e., the carrier surface) facing the upper housing 11. The vacuum device's vacuum pipe is connected to these adsorption holes. When the chip under test is placed on the carrier surface, the chip completely covers the multiple adsorption holes on the carrier surface (or, if the chip is small enough to cover only a portion of the adsorption holes, the remaining holes can be temporarily covered with tape or stickers). The vacuum device is then activated, and the vacuum pipe is used to evacuate the multiple adsorption holes, thus fixing the chip under test onto the carrier surface and preventing it from moving when the first probe 32 is coupled to the first pad and the second probe 42 is coupled to the second pad.

[0065] Of course, in this embodiment, the testing system also includes an operating table, and the lower housing 12, the first power supply device 3, and the second power supply device 4 are all fixed to the operating table. Specifically, the lower housing 12 can be integrally formed with the tabletop of the operating table, or the lower housing 12 can be magnetically fixed to the operating table by an external magnetic attraction device. The first probe holder 31 of the first power supply device 3 and the second probe holder 41 of the second power supply device 4 can be provided with magnetic attraction devices inside, that is, the first probe holder 31 and the second probe holder 41 are magnetically fixed to the operating table by their internal magnetic attraction devices.

[0066] Further, see Figure 8 and Figure 9In this embodiment, the testing system also includes an image observation device 7, which is fixed on the operating table. The image observation device 7 is used to observe the position of the optical chip under test, the first probe 32, and the second probe 42 before the upper housing 11 is closed to the lower housing 12.

[0067] Specifically, the image observation device 7 includes an adjustment device 71, an image magnification device 72, a light source 73, and a handle 74. The image magnification device 72 is fixedly connected to the adjustment device 71. The adjustment device 71 is adjusted by the handle 74 to adjust the position of the image magnification device 72 in the horizontal and vertical directions. The light source 73 is a ring light source, which can be arranged around the periphery of the image magnification device 72 to brighten the image screen of the image magnification device 72. After fixing the optical chip under test onto the chip carrier stage 2, the image magnification device 72 can be moved using the adjustment device 71 to a position directly above the optical chip under test. Using the image transmitted in real-time by the image magnification device 72, the relative distance between the image magnification device 72 and the optical chip under test can be readjusted until the specific positions of the first and second pads of the optical chip under test can be clearly observed (or the magnification of the image magnification device 72 can be adjusted until the specific positions of the first and second pads of the optical chip under test can be clearly observed). Using the image transmitted in real-time by the image magnification device 72, the positions of the first probe 32 and the second probe 42 can be adjusted until the first probe 32 is coupled to the first pad of the optical chip under test and the second probe 42 is coupled to the second pad of the optical chip under test. After confirming that the optical chip under test is lit, the image magnification device 72 can be moved away again using the adjustment device 71.

[0068] More specifically, the image magnification device 72 is a CCD camera.

[0069] Furthermore, such as Figure 1 As shown, the test system also includes a processor 9 and a display 10 coupled to each other, specifically, the processor 9 and the display 10 are signal-connected. The processor 9 is coupled to the photodetector 5, specifically, the processor 9 and the photodetector 5 are signal-connected. The processor 9 is used to acquire and process the light test data obtained by the photodetector 5, and the display 10 is used to display the light test data processed by the processor 9.

[0070] This utility model provides a brief description of the testing steps for testing an optical chip under test using a testing system: S1: Disassemble the upper housing 11 from the lower housing 12 and fix the optical chip to be tested on the chip carrier stage 2, so that the light-emitting surface of the optical chip to be tested is away from the chip carrier stage.

[0071] S2: Move the image magnification device 72 directly above the optical chip under test by adjusting the device 71, and observe the positions of the first and second pads, the first probe 32 and the second probe 42 of the optical chip under test.

[0072] S3: Based on the image transmitted in real time by the image magnification device 72, adjust the first probe holder 31 and the second probe holder 32 so that the first probe 32 is connected to the first pad and the second probe 42 is connected to the second pad.

[0073] S4: Turn on the power supply to illuminate the light chip under test.

[0074] S5: Move the image magnification device 72 out of the lower housing 12 by adjusting the device 71.

[0075] S6: Cover the upper housing 11 with the lower housing 12, and use fasteners 114 to connect the first locking structure 113 and the second locking structure 124 to fix the relative positions of the upper housing 11 and the lower housing 12.

[0076] S7: Install a photodetector 5 at the first through hole 111.

[0077] S8: Connect the processor 9 to the light detection device 5, and use the processor 9 to acquire and process the light test data of the light detection device 5.

[0078] In summary, the optical testing system based on an integrating sphere provided by this utility model includes an integrating sphere, a chip carrier stage, a first power supply device, a second power supply device, and a light detection device. The integrating sphere includes an upper shell and a lower shell, which are connected to each other to form a hollow cavity. The upper shell has a first through hole, and the lower shell has a second through hole and a third through hole. The chip carrier stage is used to place the optical chip under test and is disposed within the lower shell. The first power supply device includes a first probe, and the second power supply device includes a second probe. The light detection device is disposed within the first through hole and is used to test the light emitted by the optical chip under test. The first probe passes through the second through hole and is coupled to a first pad, and the second probe passes through the third through hole and is coupled to a second pad. The first power supply device and the second power supply device are respectively used to provide electrical signals to the optical chip under test, so that the optical chip under test emits light. This utility model has the following advantages: First, compared with testing unpackaged chips using a traditional integrating sphere, the optical testing system provided by this invention eliminates the need for complex steps such as wire bonding and desoldering during the entire testing process of unpackaged chips. This maximizes the protection of the structural and performance integrity of the unpackaged chip, significantly reduces chip testing loss rate, and also reduces chip sample consumption and testing costs.

[0079] Secondly, by setting the first and second light-shielding plates, light from the integrating sphere can be prevented from escaping through the second and third through holes. Furthermore, by setting a threaded interface at the first through hole, the optical interface of the optical detection device can be sealed and installed at the threaded interface, preventing light from the integrating sphere from escaping through the first through hole. In other words, the integrating sphere in the optical testing system provided by this utility model is a sealed sphere, which can avoid the risk of light emitted by the optical chip under test escaping and improve the accuracy of optical chip testing.

[0080] Third, by nesting the first and second probes within the integrating sphere, it is possible to directly power and emit light from unpackaged micron-sized light-emitting chips (such as Micro-LED bare dies), overcoming the limitation of traditional integrating spheres that can only test ordinary light sources or some packaged chips. Simultaneously, this solution can also test packaged chips, offering high compatibility and wider adaptability.

[0081] Fourth, the integrating sphere, the first power supply device, the second power supply device, the image observation device, and the light detection device are integrated on the same operating platform. During the testing of the optical chip under test using the integrating sphere, the optical parameters can be tested without moving the optical chip under test, thus avoiding chip damage caused by moving the optical chip under test. At the same time, the testing process is simplified and the testing efficiency is improved.

[0082] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and alterations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention, and all such changes should fall within the protection scope of the claims of the present invention.

Claims

1. A light testing system based on an integrating sphere, characterized in that, include: An integrating sphere includes an upper shell and a lower shell, which are connected to each other to form a hollow cavity. The upper shell is provided with a first through hole, and the lower shell is provided with a second through hole and a third through hole. A chip carrier stage is used to place the optical chip under test, which is disposed inside the lower housing; the light-emitting surface of the optical chip under test is provided with a first pad and a second pad; A first power supply device includes a first probe; The second power supply device includes a second probe; A light detection device is disposed in the first through hole; the light detection device is used to test the light emitted by the optical chip under test; The first probe passes through the second through-hole and is coupled to the first pad, and the second probe passes through the third through-hole and is coupled to the second pad; the first power supply device and the second power supply device are respectively used to provide electrical signals to the optical chip under test so that the optical chip under test emits light.

2. The optical testing system based on an integrating sphere according to claim 1, characterized in that, The first probe is fixedly connected to a first light-shielding plate near the second through hole. The side of the first light-shielding plate facing the second through hole is also connected to the inner side wall of the lower housing located around the second through hole. The first light-shielding plate is used to prevent the light emitted by the optical chip under test from escaping from the second through hole. The second probe is fixedly connected to a second light-shielding plate near the third through hole. The side of the second light-shielding plate facing the third through hole is also connected to the inner side wall of the lower housing located around the third through hole. The second light-shielding plate is used to prevent the light emitted by the optical chip under test from escaping from the third through hole.

3. The optical testing system based on an integrating sphere according to claim 1, characterized in that, The upper housing and the lower housing are provided with a first end face and a second end face facing each other respectively. Both the first end face and the second end face are provided with a wave-shaped structure, and when the upper housing and the lower housing are connected, the first end face and the second end face fit together.

4. The optical testing system based on an integrating sphere according to claim 3, characterized in that, Multiple first locking structures are uniformly arranged in the circumferential area of ​​the outer side wall of the upper shell near the first end face, and multiple second locking structures are uniformly arranged in the circumferential area of ​​the outer side wall of the lower shell near the second end face. The first locking structure and the second locking structure correspond one-to-one. The optical testing system also includes multiple fasteners that correspond one-to-one with the first locking structure. When the upper housing and the lower housing are connected, the fasteners pass through the corresponding first locking structure and second locking structure to fix the relative positions of the upper housing and the lower housing.

5. The optical testing system based on an integrating sphere according to claim 1, characterized in that, The center of the first through hole is located on the central axis of the upper housing, and the center of the chip carrier stage is located on the central axis of the lower housing; And / or, the second through hole and the third through hole are symmetrically arranged relative to the chip carrier platform; And / or, the second through hole and the third through hole are higher than the chip carrier stage.

6. The optical testing system based on an integrating sphere according to claim 5, characterized in that, The inner diameter of the integrating sphere is 8cm-12cm, the relative distance between the side of the chip carrier platform facing the upper housing and the center of the bottom end of the lower housing is 2cm-5cm, and the relative distance between the center of the second through hole and the center of the third through hole and the center of the bottom end of the lower housing is 3.5cm-4.25cm respectively. And / or, the diameter of the first through hole is 1cm-3cm; And / or, the diameters of the second through hole and the third through hole are both 0.4cm-0.6cm.

7. The optical testing system based on an integrating sphere according to claim 1, characterized in that, The optical detection device has an optical interface, and a threaded interface is sealed and connected to the first through hole. The optical interface is threadedly connected to the threaded interface. And / or, the optical testing system further includes light-blocking plates, which are spaced apart directly below the first through hole; And / or, the first probe extends through the second through-hole into the lower housing, and the first probe is movable such that the tip of the first probe connects to the first pad; the second probe extends through the third through-hole into the lower housing, and the second probe is movable such that the tip of the second probe connects to the second pad; And / or, the size of the optical chip under test is less than 70 μm.

8. A testing system, characterized in that, The testing system includes a power supply device and an integrating sphere-based optical testing system as described in any one of claims 1-7. The first probe and the second probe are respectively coupled to the power supply device. The first probe is used to transmit a first electrical signal output by the power supply device to the first pad, and the second probe is used to transmit a second electrical signal output by the power supply device to the second pad.

9. The testing system according to claim 8, characterized in that, The chip carrier stage has multiple adsorption holes on one side facing the upper housing. The testing system also includes a vacuum device, and the vacuum pipe of the vacuum device is connected to the adsorption holes. And / or, the testing system further includes an operating table, on which the lower housing, the first power supply device, and the second power supply device are fixed; the testing system further includes an image observation device, which is fixed on the operating table and is used to observe the position of the optical chip under test, the first probe, and the second probe before the upper housing is closed on the lower housing.

10. The testing system according to claim 8, characterized in that, The testing system also includes a processor and a display coupled to each other. The processor is coupled to the light detection device and is used to acquire and process the light test data obtained by the light detection device. The display is used to display the light test data processed by the processor.

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