A node positioning structure for impedance testing of a server PCB board

Abstract

The utility model relates to impedance test field, the utility model discloses a kind of node positioning structure of server PCB internal impedance test, including measured PCB and node positioning structure;The surface of measured PCB is equipped with several measured impedance lines, and both ends of measured impedance line are equipped with measured point;Node positioning structure includes film base sheet, and film base sheet is equipped with mark area, and each mark area inside is equipped with mark line, and one contrast impedance line is arranged in each mark line, and contrast impedance line and measured impedance line are symmetrically arranged about the plane where film base sheet is located, and both ends of contrast impedance line are equipped with test point, and test point is the through-hole structure that penetrates film base sheet, and test point and measured point are coaxially arranged. Filin can be directly covered and pasted on measured PCB, and only test point position is exposed, and the position of the impedance line to be measured is identified by contrast impedance line, so that artificial finding point time can be saved to directly test, and test efficiency can be effectively improved and the accuracy of test is guaranteed.

Description

Technical Field

[0001] This utility model relates to the field of impedance testing, and in particular to a node positioning structure for impedance testing within a server PCB board. Background Technology

[0002] Server PCBs, or server motherboards, are one of the core components of a server. Defect detection in PCBs is crucial to product quality and reliability. PCB inspection refers to a series of checks and tests performed on the printed circuit board (PCB) to ensure it meets design specifications and quality standards. Therefore, the quality of the PCB directly affects the reliability and performance of the final product.

[0003] Impedance testing is a method of calculating the impedance in a circuit by measuring the phase relationship and amplitude between current and voltage. It is commonly used to evaluate the response of circuits, devices, or systems to AC signals, providing crucial information about circuit performance, stability, and adaptability. To maintain the integrity of signal transmission, impedance testing is required during the design and manufacturing process of PCBs to ensure impedance matching.

[0004] Due to the complexity and diversity of PCB panel layouts, and the often dense nodes of impedance lines (especially those connected to the processor), locating the test node of the impedance line to be tested is quite difficult. Furthermore, the impedance testing probes are prone to accidentally touching nodes of adjacent impedance lines. This makes probe and test point positioning during testing challenging, and manual point location inefficient, resulting in low testing efficiency and accuracy. Utility Model Content

[0005] The purpose of this invention is to provide a node positioning structure for impedance testing on a server PCB board. During impedance testing, the PCB to be tested is covered, the impedance line to be tested is marked, and only the test point to be tested is exposed, which facilitates the contact between the probe and the test point and avoids accidental contact.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: a node positioning structure for impedance testing of a server PCB board, comprising the PCB under test and the node positioning structure; The surface of the PCB under test is provided with several impedance lines to be measured, and each impedance line under test has a test point at both ends. The node positioning structure includes a film substrate with marking areas. Each marking area contains a marking line, which is hollow. Each marking line contains a reference impedance line, which is symmetrically arranged with the measured impedance line about the plane of the film substrate. Both ends of the reference impedance line have test points for positioning probes. The test points are through-hole structures that penetrate the film substrate. The test points correspond one-to-one with the measured points and are coaxially arranged.

[0007] Preferably, one end of the marking line is located at the center of the film substrate, and the other end of the marking line extends toward the corner of the substrate.

[0008] Preferably, the edge of the film substrate is provided with a pad marking area, and the pad marking area is provided with a plurality of pad marking points.

[0009] Preferably, the film substrate and the PCB under test are detachably connected by a first pin, and a first positioning target is provided at the edge of the film substrate for the first pin to pass through, and a target hole is provided at the edge of the PCB under test for the first pin to pass through.

[0010] Preferably, each of the marked areas is provided with a marking ring for marking the test point, and the test point and the marking ring correspond one-to-one and are coaxially arranged.

[0011] Preferably, both the film substrate and the marking area are transparent films.

[0012] Preferably, the film substrate and the marking area are integrally formed.

[0013] Preferably, the marking area, the film substrate, and the PCB under test are detachably connected by a second pin, and a second positioning target is provided in the open area of ​​the PCB under test for the second pin to pass through.

[0014] Preferably, the marking line includes a first curve and a second curve, with the two ends of the first curve and the second curve respectively connected to two marking rings.

[0015] The beneficial effects of this invention are as follows: Based on the positions of the test point and the impedance line to be tested, a positioning target and the test point are drilled out on the film using mechanical drilling. Marking lines and reference impedance lines are pre-printed on the film substrate. The impedance line to be tested is identified using the marking lines and reference impedance lines, and the test point is marked and exposed. The film substrate can be directly applied to the PCB under test, exposing only the test point position. The position of the impedance line to be tested is marked using the reference impedance lines, thus saving manual point-finding time and allowing direct testing, effectively improving testing efficiency and ensuring testing accuracy. Attached Figure Description

[0016] The accompanying drawings further illustrate the present invention, but the embodiments in the drawings do not constitute any limitation on the present invention.

[0017] Figure 1 This is a schematic diagram of a structure provided for an embodiment of the present utility model; Figure 2 for Figure 1 A magnified view of region A in the image; The markings in the diagram are: 1: Film substrate; 2: Identified area; 3: Positioning target; 4: Identification line; 5: Reference impedance line; 6: Test point. Detailed Implementation

[0018] The specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of this utility model.

[0019] It should be noted that, in this utility model, unless otherwise stated, when an element is referred to as "fixed to" or "set on" another element, it can be directly on the other element or an intervening element may be present simultaneously. When an element is referred to as "connected to" another element, it can be directly connected to the other element or an intervening element may be present simultaneously.

[0020] like Figures 1-2 As shown in the figure, an embodiment of the present invention provides a node positioning structure for impedance testing of a server PCB board, including the PCB under test and the node positioning structure. The surface of the PCB under test is provided with several impedance lines to be measured, and each impedance line under test has a test point at both ends, and the test point has an exposed copper structure. The node positioning structure includes a film substrate 1 (i.e., a film without a chemical coating), on which an array of marking areas 2 are provided. Each marking area 2 has a marking line 4 printed inside. The marking line 4 is a hollow structure. Each marking line 4 has a reference impedance line 5 printed inside. The reference impedance line 5 and the measured impedance line are symmetrically arranged about the plane of the film substrate 1. Each end of the reference impedance line 5 has a test point 6 for positioning the probe. The test point 6 is a through-hole structure that penetrates the film substrate 1. The test point 6 corresponds one-to-one with the measured point and is coaxially arranged.

[0021] One end of the marking line 4 is positioned at the center of the film substrate 1, and the other end extends towards the corner of the board. The pads at the center of the product are relatively dense; the test point 6 at one end of the marking line 4 marks the location of the test point, improving screening and alignment speed. Impedance lines on the product are usually quite dense; the marking line 4 outlines the approximate range of the impedance line to be tested, and the reference impedance line 5 inside the marking line 4 indicates the position of the impedance line to be tested, facilitating automatic positioning by visual recognition equipment.

[0022] The film substrate 1 has a pad marking area at its edge, and the pad marking area contains several pad marking points. The pad positions are used to confirm the correct orientation of the film substrate 1 when it is placed, preventing it from being placed backwards. Simultaneously, the number of pad marking points within the pad marking area helps identify the pads and product type.

[0023] The film substrate 1 is detachably connected to the PCB under test via a first pin. A first positioning target 3 is provided at the edge of the film substrate 1 for the first pin to pass through, and a target hole is provided at the edge of the PCB under test for the first pin to pass through. After aligning the first positioning target 3 on the film substrate 1 with the target hole on the PCB under test, the reference impedance line 5 and the impedance line under test can be quickly aligned, ensuring that the test point 6 coincides with the test point.

[0024] Each of the marked areas 2 is provided with a marking ring for identifying the test point. Each test point 6 corresponds one-to-one with a marking ring and is coaxially arranged. The marking line 4 includes a first curve and a second curve, with the ends of the first and second curves respectively connected to two marking rings. The marking rings are circular rings with corresponding colors based on the object being tested. Since the aperture of the test point 6 is usually small, marking the position of the test point 6 with the marking rings facilitates checking whether the probe, test point 6, and test point are aligned.

[0025] Both the film substrate 1 and the marking area 2 are transparent films. When the node positioning structure is attached to the PCB under test, both the film substrate 1 and the marking area 2 are transparent, facilitating the observation of the impedance line under test on the PCB and whether the impedance line under test coincides with the reference impedance line 5. When the impedance line under test and the reference impedance line 5 completely coincide, the test point 6 is aligned with the test point and their centers are collinear; when the impedance line under test and the reference impedance line 5 do not coincide, the test point 6 is not aligned with the test point.

[0026] The film substrate 1 and the marking area 2 are integrally formed. The marking line 4, the reference impedance line 5, and the test point 6 are all directly printed on the film substrate 1. Through-hole structures for the test point 6 are drilled using a milling machine, which facilitates processing. The reference impedance line 5 and the test point 6 have high positional accuracy, making it easy to mark the impedance line and the test point being measured. Furthermore, the film substrate 1 is a single layer, making it more transparent and facilitating the observation of the impedance line and the test point being measured.

[0027] In one embodiment, the film substrate 1 and the marking area 2 are bonded together with adhesive tape. The marking area 2, the film substrate 1, and the PCB under test are detachably connected by a second pin. A second positioning target 3 is provided in an open area of ​​the PCB under test for the second pin to pass through. The marking line 4, the reference impedance line 5, and the test point 6 are all directly printed on the marking area 2. Since some PCBs of similar models have identical circuit structures, the corresponding marking area 2 can be selected based on the structure of the identical parts, and the corresponding marking area 2 can be attached and fixed to the film substrate 1, improving versatility.

[0028] In one embodiment, the area between the marker line 4 and the reference impedance line 5 is filled with a color consistent with the marker ring, and the colored portion is confirmed to be semi-transparent. After aligning the film substrate 1 with the PCB under test and fixing it with the first pin, the impedance line under test will be located inside the marker line 4 and coincide with the reference impedance line 5. At the same time, the colored portion blocks other impedance lines, facilitating visual inspection of the impedance line under test and preventing other impedance lines from interfering with the visual inspection process.

[0029] The technical features of the embodiments described above can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of this utility model, and these should all be considered to be within the scope of this specification.

Claims

1. A node positioning structure for impedance testing on a server PCB board, characterized in that: Including the PCB under test and the node positioning structure; The surface of the PCB under test is provided with several impedance lines to be measured, and each impedance line under test has a test point at both ends. The node positioning structure includes a film substrate with marking areas. Each marking area contains a marking line, which is hollow. Each marking line contains a reference impedance line, which is symmetrically arranged with the measured impedance line about the plane of the film substrate. Both ends of the reference impedance line have test points for positioning probes. The test points are through-hole structures that penetrate the film substrate. The test points correspond one-to-one with the measured points and are coaxially arranged.

2. The node positioning structure for impedance testing of server PCB board according to claim 1, characterized in that: One end of the marking line is located at the center of the film substrate, and the other end of the marking line extends toward the corner of the substrate.

3. The node positioning structure for impedance testing of server PCB board according to claim 1, characterized in that: The edge of the film substrate is provided with a pad marking area, and the pad marking area is provided with a number of pad marking points.

4. The node positioning structure for impedance testing of server PCB board according to claim 3, characterized in that: The film substrate and the PCB under test are detachably connected by a first pin. The film substrate, the PCB under test, and the pad marking area are all provided with positioning target holes through which the first pin passes.

5. The node positioning structure for impedance testing of a server PCB board according to claim 1, characterized in that: Each of the marked areas is provided with a marking ring for marking the test point, and the test point and the marking ring are coaxially arranged in a one-to-one correspondence.

6. The node positioning structure for impedance testing on a server PCB board according to claim 1, characterized in that: Both the film substrate and the marking area are transparent films.

7. The node positioning structure for impedance testing of server PCB board according to claim 1, characterized in that: The film substrate and the marking area are integrally formed.

8. The node positioning structure for impedance testing of server PCB board according to claim 1, characterized in that: The marking area, film substrate, and PCB under test are detachably connected by a second pin, and a second positioning target is provided in the open area of ​​the PCB under test for the second pin to pass through.

9. The node positioning structure for impedance testing of a server PCB board according to claim 5, characterized in that: The marking line includes a first curve and a second curve, with the two ends of the first curve and the second curve respectively connected to two marking rings.

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