Test load board, interface substrate, and test system

Abstract

The present disclosure relates to a test load board, an interface substrate and a test system, the test load board comprising a test substrate and an interface substrate, wherein the test substrate comprises a first electrical connection part and at least one chip mounting part for mounting a chip assembly to be tested, the chip mounting part is electrically connected to the first electrical connection part, a structure substrate is detachably connected to the test substrate, the interface substrate comprises a second electrical connection part and a debugging interface for connecting a test device, the debugging interface is electrically connected to the second electrical connection part, and the second electrical connection part is detachably electrically connected to the first electrical connection part. In this way, when different types of chips need to be tested, the test load board does not need to be replaced as a whole, and the test substrate can be directly replaced without replacing the interface substrate, thereby saving costs.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor testing technology, and more specifically, to a test load board, an interface substrate, and a testing system. Background Technology

[0002] After chip production is completed, functional and performance verification is required using automated test equipment (ATE) to screen out defective products and ensure the quality of chips leaving the factory. During chip testing, the chips need to be mounted on a test loadboard. Depending on the chip size and pin configuration, the test loadboard needs to be customized; that is, different test load boards are required for testing different chips, resulting in high costs. Utility Model Content

[0003] The purpose of this disclosure is to provide a test load board, an interface substrate, and a test system that eliminates the need to replace the entire test load board when testing different types of chips, thereby saving costs.

[0004] To achieve the above objectives, a first aspect of this disclosure provides a test load board, comprising: a test substrate, including a first electrical connection portion and at least one chip mounting portion, wherein the chip mounting portion is used for mounting a chip assembly to be tested, and the chip mounting portion is electrically connected to the first electrical connection portion; and An interface substrate is detachably connected to the test substrate. The interface substrate includes a second electrical connection portion and a debugging interface for connecting to a test device. The debugging interface is electrically connected to the second electrical connection portion, and the second electrical connection portion is detachably electrically connected to the first electrical connection portion.

[0005] Optionally, the debugging interface includes at least one of a UART interface, an SPI interface, a JTAG interface, and a BIF interface.

[0006] Optionally, the test substrate includes a first mounting portion, and the interface substrate includes a second mounting portion, the second mounting portion being detachably connected to the first mounting portion.

[0007] Optionally, the first mounting part is configured as one of a male and a female snap-fit, and the second mounting part is configured as the other of the male and female snap-fit, wherein the male and female snap-fit ​​engage to allow the interface substrate to be detachably snapped onto the test substrate.

[0008] Optionally, the first mounting portion includes a first magnetic member, and the second mounting portion includes a second magnetic member. The first magnetic member and the second magnetic member magnetically engage to enable a detachable connection between the interface substrate and the test substrate.

[0009] Optionally, the test load plate further includes fasteners; The first mounting portion includes a first mounting hole provided on the test substrate, and the second mounting portion includes a second mounting hole provided on the interface substrate and corresponding to the first mounting hole. The fastener passes through the first mounting hole and the second mounting hole to detachably connect the interface substrate to the test substrate.

[0010] Optionally, at least one of the first mounting hole and the second mounting hole is configured as a threaded hole, and the fastener is configured as a screw, which passes through the first mounting hole and the second mounting hole and is threadedly connected to the first mounting hole and / or the second mounting hole.

[0011] Optionally, there are multiple first mounting holes and multiple second mounting holes, and the multiple first mounting holes and multiple second mounting holes correspond one-to-one.

[0012] Optionally, a groove corresponding to the interface substrate is formed on the test substrate, and the interface substrate is mounted on the groove.

[0013] The second aspect of this disclosure provides an interface substrate for testing a load board. The interface substrate includes a second electrical connection portion and a debugging interface for connecting to a test device. The debugging interface is electrically connected to the second electrical connection portion. The second electrical connection portion can be detachably electrically connected to the test substrate. With this configuration, the interface substrate 20 can be detachably electrically connected to different test substrates 10, thereby increasing the versatility (or reusability) of the interface substrate 20.

[0014] Optionally, the debugging interface includes at least one of a UART interface, an SPI interface, a JTAG interface, and a BIF interface.

[0015] Optionally, the interface substrate includes a second mounting portion for detachably connecting to the test substrate.

[0016] Optionally, the second mounting part is configured as one of a male snap-on and a female snap-on; and / or The second mounting part is constructed as a magnetic suction element; and / or The second mounting part is constructed as a mounting hole.

[0017] A third aspect of this disclosure provides a test system, including a test device and a test load board as described in the first aspect of this disclosure, wherein the test device is electrically connected to the debugging interface.

[0018] With the above technical solution, the test load board includes a test substrate and an interface substrate. The chip mounting part of the test substrate is used to install and connect the chip assembly to be tested. The interface substrate is detachably connected to the test substrate and can be electrically connected to the test substrate separately. With this configuration, when different types of chips need to be tested, it is not necessary to replace the entire test load board. Only the test substrate needs to be replaced directly, and there is no need to replace the interface substrate, which can save costs.

[0019] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the overall structure of the test load board provided in some exemplary embodiments of this disclosure; Figure 2 This is a schematic diagram of the structure of a test substrate provided in some exemplary embodiments of this disclosure; Figure 3 This is a schematic diagram of the interface substrate and fasteners provided in some exemplary embodiments of this disclosure; Figure 4 This is a schematic diagram of the overall structure of the test load board provided in some other exemplary embodiments of this disclosure; Figure 5 This is a schematic diagram of the structure of the test substrate provided in some other exemplary embodiments of this disclosure; Figure 6 This is a schematic diagram of the structure of the interface substrate provided in some other exemplary embodiments of this disclosure; Figure 7 This is a schematic diagram of the structure of a test load board provided in some exemplary embodiments of the present disclosure; Figure 8 This is a schematic diagram of the structure of a test substrate provided in some exemplary embodiments of this disclosure; Figure 9 This is a schematic diagram of the structure of the interface substrate provided in some exemplary embodiments of this disclosure.

[0021] Explanation of reference numerals in the attached figures 10-Test substrate; 11-Chip mounting portion; 12-First board body; 121-Groove portion; 13-First electrical connection portion; 14-First mounting portion; 141-First mounting hole; 142-First magnetic clasp; 143-Press female buckle; 20-Interface substrate; 21-Debug interface; 211-UART interface; 212-SPI interface; 213-JTAG interface; 214-BIF interface; 22-Second board body; 23-Second mounting portion; 231-Second mounting hole; 232-Second magnetic clasp; 233-Press male buckle; 24-Second electrical connection portion; 30-Chip assembly under test; 40-Fastener; 41-Screw. Detailed Implementation

[0022] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0023] Unless otherwise stated, directional terms such as "inner" and "outer" refer to the inner and outer contours relative to the outline of the component or structure itself. Furthermore, it should be noted that terms such as "first" and "second" are used to distinguish one element from another and do not indicate sequence or importance. Additionally, in the description with reference to the accompanying drawings, the same reference numerals in different drawings denote the same element.

[0024] like Figures 1 to 9 As shown, the first aspect of this disclosure provides a test load board, which includes a test substrate 10 and an interface substrate 20. The test substrate 10 includes a first electrical connection portion 13 and at least one chip mounting portion 11. The chip mounting portion 11 is used for mounting a chip assembly 30 to be tested and is electrically connected to the first electrical connection portion 13. The interface substrate 20 is detachably connected to the test substrate 10 and includes a second electrical connection portion 24 and a debugging interface 21 for connecting to a test device. The debugging interface 21 is electrically connected to the second electrical connection portion 24, and the second electrical connection portion 24 is detachably electrically connected to the first electrical connection portion 13.

[0025] In the above embodiments, the test load board includes a test substrate 10 and an interface substrate 20. The chip mounting part 11 of the test substrate 10 is used to mount and connect the chip assembly 30 to be tested. The interface substrate 20 is detachably electrically connected to the test substrate 10. With this configuration, when different types of chips need to be tested, it is not necessary to replace the entire test load board. The test substrate 10 can be replaced directly without replacing the interface substrate 20, which can save costs.

[0026] In addition, the interface substrate 20 can be electrically connected to different test substrates 10, which can increase the versatility (or reusability) of the interface substrate 20.

[0027] In some possible implementations, the interface substrate 20 can be electrically connected to the test substrate 10 separately. When the test substrate 10 is replaced, there is no need to redesign the circuit designed on the interface substrate 20, saving manpower and resources.

[0028] It should be noted that the first electrical connection portion 13 and the second electrical connection portion 24 can be constructed in any suitable form. For example, the first electrical connection portion 13 can be constructed as a socket, and the second electrical connection portion 24 can be constructed as a plug. The plug can be detachably inserted into the socket, enabling the interface substrate 20 to be detachably electrically connected to the test substrate 10.

[0029] In some other possible implementations, the debugging interface 21 of the interface substrate 20 is used for electrical connection with the automated test equipment of the chip. The debugging interface 21 and the plug of the automated test equipment of the chip need to be plugged and unplugged frequently. Long-term use can easily damage the debugging interface 21. When the debugging interface 21 is damaged, the interface substrate 20 can be replaced directly, and the test substrate 10 does not need to be replaced, thus reducing the replacement cost.

[0030] In some embodiments, the debugging interface 21 of the interface substrate 20 may include various forms. For example, the debugging interface 21 may include at least one of a UART interface 211, an SPI interface 212, a JTAG interface 213, and a BIF interface 214. In the above embodiments, an automated testing device for the chip can be electrically connected to the aforementioned interface provided on the interface substrate 20 and used to test the chip assembly 30 to be tested provided on the test substrate 10 electrically connected to the interface substrate 20. Specific testing operations can be referred to in related technologies and will not be elaborated here.

[0031] To meet device debugging requirements, the debugging interface 21 can be configured with multiple interface types, including but not limited to UART interface 211, SPI interface 212, JTAG interface 213, and BIF interface 214. In practical applications, the debugging interface 21 does not need to integrate all four interfaces simultaneously. Instead, it can select and integrate at least one interface based on the device's debugging function requirements, hardware design costs, and the complexity of the usage scenario to achieve debugging operations such as program burning, data transmission, fault detection, and status monitoring. The selection of the above interface types needs to be determined in conjunction with the specific application scenario: for example, the UART interface 211 is suitable for low-cost, low-speed serial data transmission scenarios and can meet basic debugging command interaction requirements; the SPI interface 212 has high-speed synchronous serial communication capabilities and is suitable for scenarios with high requirements for debugging data transmission rates; the JTAG interface 213 is an industry-standard debugging interface that enables direct access to the chip's internal registers and memory, facilitating in-depth fault diagnosis; and the BIF interface 214 can provide customized debugging communication support according to the specific device's hardware architecture and debugging protocol, improving debugging flexibility.

[0032] As Figure 1 , Figure 4 as well as Figure 7 As shown, the interface substrate 20 includes a UART interface 211, an SPI interface 212, a JTAG interface 213, and a BIF interface 214. When the interface substrate 20 is connected to the test substrate 10, the second electrical connection portion 24 of the interface substrate 20 is inserted into the first electrical connection portion 13 of the test substrate 10, so that the automated test equipment of the chip can test the chip assembly 30 installed on the test substrate 10 through the interface substrate 20 and the test substrate 10.

[0033] Furthermore, the chip mounting portion 11 on the test substrate 10 can be constructed using any suitable structural form. For example... Figure 2 , Figure 5 as well as Figure 8 As shown, the chip mounting portion 11 on the test substrate 10 may include metal pads, and the chip assembly 30 to be tested includes a socket, a top cover, and a chip mounted on the socket. The socket is disposed on the first plate 12 of the test substrate 10 and is electrically connected to the metal pads. After the chip is mounted on the socket, the top cover is then placed on top.

[0034] In some implementations, such as Figure 1 , Figure 4 as well as Figure 7As shown, a recess 121 corresponding to the interface substrate 20 is formed on the test substrate 10. The interface substrate 20 is mounted in the recess 121 so that when the interface substrate 20 is mounted on the test substrate 10, the interface substrate 20 can be at least partially hidden in the recess 121, thereby avoiding the test load board from occupying too much space and making the appearance more aesthetically pleasing.

[0035] In addition, the size of the interface substrate 20 matches the size of the recess 121. Thus, when the interface substrate 20 is installed in the recess 121, at least a portion of the sidewall of the interface substrate 20 can fit against the sidewall of the recess 121, thereby saving the area occupied by the recess 121 on the test substrate 10. At the same time, the recess 121 that matches the interface substrate 20 can also achieve auxiliary positioning during the installation of the interface substrate 20, thereby improving the installation efficiency.

[0036] Of course, in other embodiments, the size of the groove 121 is larger than the size of the interface substrate 20. With this arrangement, the groove 121 provides more operating space for the installation of the interface substrate 20 and makes it easier to install the interface substrate 20.

[0037] It should be noted that the detachable connection between the interface substrate 20 and the test substrate 10 can adopt any suitable structural form.

[0038] In some embodiments, the test substrate 10 may include a first mounting portion 14, and the interface substrate 20 may include a second mounting portion 23, which is detachably connected to the first mounting portion 14. This arrangement allows for a detachable connection between the interface substrate 20 and the test substrate 10, facilitating the replacement of either the test substrate 10 or the interface substrate 20.

[0039] In some embodiments, the first mounting portion 14 may be provided in the recessed portion 121. When the second mounting portion 23 of the interface substrate 20 is detachably connected to the first mounting portion 14, the interface substrate 20 can be detachably mounted in the recessed portion 121 of the test substrate 10.

[0040] It should be understood that the first mounting part 14 and the second mounting part 23 can be constructed in any suitable form. In some embodiments, such as Figures 7 to 9 As shown, the first mounting part 14 can be configured as one of the male snap fastener 233 and the female snap fastener 143, and the second mounting part 23 can be configured as the other of the male snap fastener 233 and the female snap fastener 143, wherein the male snap fastener 233 and the female snap fastener 143 are engaged to allow the interface substrate 20 to be detachably connected to the test substrate 10.

[0041] In the above embodiments, the first mounting part 14 and the second mounting part 23 are respectively configured as a male snap fastener 233 and a female snap fastener 143, which facilitates the assembly and disassembly between the test substrate 10 and the interface substrate 20, and the assembly and disassembly process is relatively simple.

[0042] like Figures 7 to 9 As shown, the first mounting portion 14 of the test substrate 10 can also be configured as a female snap-fit ​​143, and the second mounting portion 23 of the interface substrate 20 can be configured as a male snap-fit ​​233. When the interface substrate 20 needs to be mounted on the test substrate 10, the second electrical connection portion 24 on the interface substrate 20 can be aligned with the first electrical connection portion 13 on the test substrate 10, and then pressed. This allows the second electrical connection portion 24 of the interface substrate 20 to be inserted into the first electrical connection portion 13 of the test substrate 10, and the male snap-fit ​​233 to be inserted into the female snap-fit ​​143. The male snap-fit ​​233 and the female snap-fit ​​143 are engaged to mount the interface substrate 20 on the test substrate 10. Multiple male snap-fits 233 and multiple female snap-fits 143 can be used, with each male snap-fit ​​233 corresponding to a different female snap-fit ​​143. This improves the stability of the interface substrate 20 when connected to the test substrate 10.

[0043] like Figures 7 to 9 As shown, the interface substrate 20 includes a second board 22, one or more debugging interfaces 21, male push-buttons 233, and second electrical connection parts 24 are respectively disposed on the second board 22. The number of male push-buttons 233 is four and they are respectively disposed near the corner of the second board 22. The test substrate 10 includes a first board 12, and a groove 121 is provided on the first board. The chip mounting part 11, the first electrical connection part 13, and the female push-buttons 143 are disposed on the first board 12. The first board 12 is provided with four female push-buttons 143 that correspond one-to-one with the male push-buttons 233, and all four female push-buttons 143 are disposed in the groove 121.

[0044] It should be noted that the aforementioned male snap fastener 233 and female snap fastener 143 can be any snap fastener commonly used in related technologies, and there are no restrictions here.

[0045] In other implementations, such as Figures 4 to 6 As shown, the first mounting part 14 includes a first magnetic member 142, and the second mounting part 23 includes a second magnetic member 232. The first magnetic member 142 and the second magnetic member 232 magnetically engage to make the interface substrate 20 detachably connected to the test substrate 10.

[0046] In the above embodiments, the first mounting part 14 and the second mounting part 23 can be respectively configured as a first magnetic suction member 142 and a second magnetic suction member 232, which can facilitate the assembly and disassembly between the test substrate 10 and the interface substrate 20, and the assembly and disassembly process is also relatively simple.

[0047] It should be understood that both the first magnetic element 142 and the second magnetic element 232 can be constructed as magnets, and the two can be detachably connected by magnetic attraction.

[0048] like Figures 4 to 6 As shown, there can be multiple first magnetic attractors 142 and multiple second magnetic attractors 232, with each first magnetic attractor 142 and each second magnetic attractor 232 corresponding to one another, and the corresponding first magnetic attractors 142 and second magnetic attractors 232 attracting each other. This arrangement makes the connection between the interface substrate 20 and the test substrate 10 more stable.

[0049] like Figures 4 to 6 As shown, the interface substrate 20 includes a second board body 22, and one or more debugging interfaces 21, second magnetic clasps 232 and second electrical connection parts 24 are respectively disposed on the second board body 22. The number of second magnetic clasps 232 is four and they are respectively disposed near the corner of the second board body 22. The test substrate 10 includes a first board body 12, and the first board body 12 also includes a groove 121. The chip mounting part 11, the first electrical connection part 13 and the first magnetic clasps 142 are disposed on the first board body 12. The number of first magnetic clasps 142 is four and they are all disposed in the groove 121. The four first magnetic clasps 142 correspond one-to-one with the four second magnetic clasps 232 on the second board body 22. When it is necessary to mount the interface substrate 20 onto the test substrate 10, the second electrical connection portion 24 of the interface substrate 20 can be inserted into the first electrical connection portion 13 of the test substrate 10, and then the interface substrate 20 can be pressed toward the test substrate 10. The second magnetic member 232 of the interface substrate 20 and the first magnetic member 142 of the test substrate 10 magnetically engage, so that the interface substrate 20 can be detachably mounted on the groove portion 121 of the test substrate 10.

[0050] In some implementations, such as Figures 1 to 4 As shown, the test load board may also include a fastener 40. The first mounting portion 14 includes a first mounting hole 141 provided on the test substrate 10, and the second mounting portion 23 includes a second mounting hole 231 provided on the interface substrate 20 and corresponding to the first mounting hole 141. The fastener 40 passes through the first mounting hole 141 and the second mounting hole 231 to detachably connect the interface substrate 20 to the test substrate 10.

[0051] In the above embodiments, the interface substrate 20 is detachably connected to the test substrate 10 by the fastener 40, which facilitates the assembly and disassembly of the interface substrate 20 and the test substrate 10. Furthermore, the assembly and disassembly process of detachably connecting the interface substrate 20 to the test substrate 10 by the fastener 40 is relatively simple and facilitates the assembly and disassembly of the interface substrate 20 and the test substrate 10.

[0052] It should be understood that the fastener 40 can be constructed in any suitable form. The fastener 40 can be constructed as a screw 41, with at least one of the first mounting hole 141 and the second mounting hole 231 being a threaded hole. The screw 41 passes through the first mounting hole 141 and the second mounting hole 231 and is threadedly connected to the first mounting hole 141 and / or the second mounting hole 231, so that the interface substrate 20 is detachably connected to the test substrate 10.

[0053] It should be noted that when the fastener 40 includes a screw 41, the screw 41 includes a nut portion and a body portion. The body portion is provided with external threads, and one end of the body portion is connected to the nut portion. When one of the corresponding first mounting hole 141 and second mounting hole 231 is constructed as a threaded hole, the screw 41 passes through the corresponding first mounting hole 141 and second mounting hole 231 and is threadedly connected to the first mounting hole 141 or the second mounting hole 231 that is constructed as a threaded hole. The nut is close to the first mounting hole 141 or the second mounting hole 231 that is not constructed as a threaded hole. In this way, the interface substrate 20 and the test substrate 10 can be detachably connected together by the screw 41.

[0054] When the fastener 40 includes a screw 41, and both the first mounting hole 141 and the second mounting hole 231 are constructed as threaded holes, the screw 41 can be inserted into the first mounting hole 141 and the second mounting hole 231, and the screw 41 is threadedly connected to the first mounting hole 141 and the second mounting hole 231.

[0055] In some embodiments, there are multiple first mounting holes 141 and multiple second mounting holes 231, and the multiple first mounting holes 141 and multiple second mounting holes 231 correspond one-to-one. In addition, there may also be multiple fasteners 40, which are respectively inserted into the corresponding first mounting holes 141 and second mounting holes 231 to connect the interface substrate 20 to the test substrate 10, thereby making the connection between the interface substrate 20 and the test substrate 10 more stable.

[0056] like Figures 1 to 3As shown, the interface substrate 20 includes a second plate 22, a second electrical connection portion 24 disposed on the second plate 22, and one or more debugging interfaces 21. The four corners of the second plate 22 are respectively provided with second mounting holes 231 constructed as threaded holes, that is, the second plate 22 is provided with four second mounting holes 231. The test substrate 10 includes a first plate 12, a first electrical connection portion 13 disposed on the first plate 12, and a chip mounting portion 11 disposed on the first plate 12. The first plate 12 is provided with a groove portion 121, and the groove portion 121 provided on the first plate 12 is also provided with four first mounting holes 141. The four first mounting holes 141 correspond one-to-one with the four second mounting holes 231 on the second plate 22. The four first mounting holes 141 can all be constructed as threaded holes. The fastener 40 is constructed as a screw 41. There are four fasteners 40. The four fasteners 40 correspond to four sets of corresponding first mounting holes 141 and second mounting holes 231 respectively. When it is necessary to install the interface substrate 20 and the test substrate 10 together, the second connecting part of the interface substrate 20 can be inserted into the first electrical connecting part 13 of the test substrate 10 firstly, and then the screw 41 is inserted into the corresponding first mounting hole 141 and second mounting hole 231 and threadedly connected to the first mounting hole 141 and second mounting hole 231 so as to detachably install the interface substrate 20 into the groove 121 of the test substrate 10.

[0057] A second aspect of this disclosure provides an interface substrate 20 for use with a test substrate 10 for testing a load board, such as... Figure 3 , Figure 6 as well as Figure 9 As shown, the interface substrate 20 includes a second electrical connection portion 24 and a debugging interface 21 for connection with a test device. The debugging interface 21 is electrically connected to the second electrical connection portion 24, and the second electrical connection portion 24 can be detachably electrically connected to the test substrate 10. The test substrate 10 can be used to mount the chip assembly 30 to be tested.

[0058] In the above embodiments, the second electrical connection portion 24 of the interface substrate 20 is used to be detachably electrically connected to the test substrate 10. In this way, the interface substrate 20 can be detachably electrically connected to different test substrates 10, which can increase the versatility (or reusability) of the interface substrate 20.

[0059] In addition, different test substrates 10 can be used to mount different chip components 30 under test. The interface substrate 20 can be electrically connected to different test substrates 10 in a separable manner to complete the testing of different chip components 30 under test.

[0060] It should be noted that, as Figures 1 to 9As shown, the test substrate 10 may include a first electrical connection portion 13 that is detachably plugged into the second electrical connection portion 24. The first electrical connection portion 13 and the second electrical connection portion 24 are plugged into each other to realize the electrical connection between the interface substrate 20 and the test substrate 10.

[0061] As mentioned in the first subject matter of this disclosure, the first electrical connection 13 and the second electrical connection 24 can be configured in any suitable form. For example, the first electrical connection 13 can be configured as a socket and the second electrical connection 24 can be configured as a plug, with the plug being detachably plugged into the socket, enabling the interface substrate 20 to be detachably electrically connected to the test substrate 10.

[0062] In addition, the first electrical connection part 13 can be configured as a female connector and the second electrical connection part 24 can be configured as a male connector. By the insertion and mating of the male and female connectors, a separable electrical connection between the interface substrate 20 and the test substrate 10 can be realized.

[0063] In some embodiments, the debugging interface 21 of the interface substrate 20 may include various forms. For example, as mentioned in the first aspect of this disclosure, the debugging interface 21 may include at least one of a UART interface 211, an SPI interface 212, a JTAG interface 213, and a BIF interface 214. In the above embodiments, an automated testing device for the chip can be electrically connected to the aforementioned interface provided on the interface substrate 20 and used to test the chip assembly 30 to be tested provided on the test substrate 10 electrically connected to the interface substrate 20. Specific testing operations can be referred to in related art, and will not be elaborated here.

[0064] To meet device debugging requirements, the debugging interface 21 can be configured with various interface types, as mentioned in the first aspect of this disclosure. Specifically, the debugging interface 21 may include, but is not limited to, UART interface 211, SPI interface 212, JTAG interface 213, and BIF interface 214. In practical applications, the debugging interface 21 does not need to integrate all four interfaces simultaneously. Instead, it can select and integrate at least one interface based on the device's debugging function requirements, hardware design costs, and the complexity of the usage scenario to achieve debugging operations such as program burning, data transmission, fault detection, and status monitoring. The selection of the above interface types needs to be determined in conjunction with the specific application scenario: for example, the UART interface 211 is suitable for low-cost, low-speed serial data transmission scenarios and can meet basic debugging command interaction requirements; the SPI interface 212 has high-speed synchronous serial communication capabilities and is suitable for scenarios with high requirements for debugging data transmission rates; the JTAG interface 213 is an industry-standard debugging interface that enables direct access to the chip's internal registers and memory, facilitating in-depth fault diagnosis; and the BIF interface 214 can provide customized debugging communication support according to the specific device's hardware architecture and debugging protocol, improving debugging flexibility.

[0065] In some implementations, such as Figure 3 , Figure 6 as well as Figure 9 As shown, the interface substrate 20 includes a second mounting portion 23, which is used to detachably connect to the test substrate 10, so as to facilitate the replacement of the test substrate 10.

[0066] In the above embodiments, the test substrate 10 for detachably connecting with the interface substrate 20 includes a first mounting portion 14, which is detachably connected with a second mounting portion 23, so that the interface substrate 20 and the test substrate 10 are detachably connected.

[0067] It should be noted that the second mounting part 23 can be constructed in any suitable structure.

[0068] In some implementations, such as Figures 7 to 9 As shown, the second mounting part 23 is configured as one of the male snap fastener 233 and the female snap fastener 143, while the first mounting part 14 on the test substrate 10 that cooperates with the second mounting part 23 can be configured as the other of the male snap fastener 233 and the female snap fastener 143. Through the snap-fit ​​cooperation of the male snap fastener 233 and the female snap fastener 143, the interface substrate 20 is detachably connected to the test substrate 10.

[0069] For example, such as Figures 7 to 9 As shown, the first mounting portion 14 of the test substrate 10 can be configured as a female snap-fit ​​143, and the second mounting portion 23 of the interface substrate 20 can be configured as a male snap-fit ​​233. When it is necessary to mount the interface substrate 20 onto the test substrate 10, the second electrical connection portion 24 on the interface substrate 20 can be aligned with the first electrical connection portion 13 on the test substrate 10, and then pressed. This allows the second electrical connection portion 24 of the interface substrate 20 to be inserted into the first electrical connection portion 13 of the test substrate 10, and allows the male snap-fit ​​233 to be inserted into the female snap-fit ​​143. The male snap-fit ​​233 and the female snap-fit ​​143 are engaged to mount the interface substrate 20 onto the test substrate 10.

[0070] In other implementations, such as Figures 4 to 6 As shown, the second mounting portion 23 can be configured as a magnetic member, wherein the second mounting portion 23 can be configured as a second magnetic member 232, and the first mounting portion 14 on the test substrate 10 that cooperates with the second mounting portion 23 can be configured as a first magnetic member 142. The first magnetic member 142 and the second magnetic member 232 are magnetically engaged to make the interface substrate 20 and the test substrate 10 detachably connected.

[0071] It should be understood that, as mentioned in the first subject matter of this disclosure, both the first magnetic member 142 and the second magnetic member 232 can be constructed as magnets, and the two can be detachably connected by magnetic attraction.

[0072] In other implementations, such as Figures 1 to 3 As shown, the second mounting portion 23 can be configured as a mounting hole, wherein the second mounting portion 23 can be configured as a second mounting hole 231, and the first mounting portion 14 of the test substrate 10 that cooperates with the second mounting portion 23 can be configured as a first mounting hole 141. Fasteners 40 can be inserted through the first mounting hole 141 and the second mounting hole 231 to allow the interface substrate 20 to be detachably connected to the test substrate 10.

[0073] In the above embodiments, the second mounting hole 231 can be constructed as a threaded hole, and the first mounting hole 141 on the test substrate 10 that mates with the second mounting hole 231 can also be constructed as a threaded hole. The fastener 40 can be constructed as a screw 41, which can be inserted into the first mounting hole 141 and the second mounting hole 231, so that the screw 41 is threadedly connected to the first mounting hole 141 and the second mounting hole 231.

[0074] A third aspect of this disclosure provides a test system, including a test device and a test load board as described in the first aspect of this disclosure, wherein the test device is electrically connected to a debug interface 21.

[0075] In the above embodiment, the debugging interface 21 is the debugging interface 21 of the interface substrate 20 in the test load board, the test equipment is an automatic test equipment, the chip assembly 30 to be tested is mounted on the test substrate 10, the test equipment is electrically connected to the debugging interface 21 of the interface substrate 20, the second electrical connection part 24 of the interface substrate 20 is inserted into the first electrical connection part 13 of the test substrate 10, and then the screw 41 is passed through the corresponding first mounting hole 141 and second mounting hole 231. The first mounting hole 141 and the second mounting hole 231 are both constructed as threaded holes, and the screw is threadedly connected to the first mounting hole 141 and the second mounting hole 231 respectively, so as to detachably connect the interface substrate 20 and the test substrate 10 together, and then the chip assembly 30 to be tested is tested by the test equipment.

[0076] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0077] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0078] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A test load board, characterized in that, include: The test substrate includes a first electrical connection portion and at least one chip mounting portion, wherein the chip mounting portion is used for mounting a chip assembly to be tested, and the chip mounting portion is electrically connected to the first electrical connection portion. as well as An interface substrate is detachably connected to the test substrate. The interface substrate includes a second electrical connection portion and a debugging interface for connecting to a test device. The debugging interface is electrically connected to the second electrical connection portion, and the second electrical connection portion is detachably electrically connected to the first electrical connection portion.

2. The test load board according to claim 1, characterized in that, The debugging interface includes at least one of the following: UART interface, SPI interface, JTAG interface, and BIF interface.

3. The test load board according to claim 1, characterized in that, The test substrate includes a first mounting portion, and the interface substrate includes a second mounting portion, the second mounting portion being detachably connected to the first mounting portion.

4. The test load board according to claim 3, characterized in that, The first mounting part is constructed as one of a male and a female snap-fit, and the second mounting part is constructed as the other of the male and female snap-fit. The male and female snap-fit ​​engage to allow the interface substrate to be detachably snapped onto the test substrate.

5. The test load board according to claim 3, characterized in that, The first mounting portion includes a first magnetic member, and the second mounting portion includes a second magnetic member. The first magnetic member and the second magnetic member magnetically engage to enable a detachable connection between the interface substrate and the test substrate.

6. The test load board according to claim 3, characterized in that, The test load board also includes fasteners; The first mounting portion includes a first mounting hole provided on the test substrate, and the second mounting portion includes a second mounting hole provided on the interface substrate and corresponding to the first mounting hole. The fastener passes through the first mounting hole and the second mounting hole to detachably connect the interface substrate to the test substrate.

7. The test load board according to claim 6, characterized in that, At least one of the first mounting hole and the second mounting hole is configured as a threaded hole, and the fastener is configured as a screw, which passes through the first mounting hole and the second mounting hole and is threadedly connected to the first mounting hole and / or the second mounting hole.

8. The test load board according to claim 7, characterized in that, There are multiple first mounting holes and multiple second mounting holes, and the multiple first mounting holes and multiple second mounting holes correspond one-to-one.

9. The test load board according to any one of claims 1 to 8, characterized in that, The test substrate has a groove corresponding to the interface substrate, and the interface substrate is mounted on the groove.

10. An interface substrate, a test substrate for testing load boards, characterized in that, It includes a second electrical connection portion and a debugging interface for connecting to a test device, the debugging interface being electrically connected to the second electrical connection portion, the second electrical connection portion being detachably electrically connected to the test substrate.

11. The interface substrate according to claim 10, characterized in that, The debugging interface includes at least one of the following: UART interface, SPI interface, JTAG interface, and BIF interface.

12. The interface substrate according to claim 10 or 11, characterized in that, The interface substrate includes a second mounting portion for detachably connecting to the test substrate.

13. The interface substrate according to claim 12, characterized in that, The second mounting part is constructed as one of a male snap-on snap and a female snap-on snap; and / or The second mounting part is constructed as a magnetic suction element; and / or The second mounting part is constructed as a mounting hole.

14. A testing system, characterized in that, It includes a test device and a test load board as described in any one of claims 1-9, wherein the test device is electrically connected to the debugging interface.

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