A miniaturized coded source for secondary surveillance radar equipment testing

Abstract

The utility model discloses a kind of miniaturization coding sources applied to secondary monitoring radar equipment test, it is related to signal coding equipment, to solve the problem such as high cost, less channel of traditional coding source.Precoding source includes power conversion circuit, control circuit and modulation source circuit;Power conversion circuit converts external alternating current into working direct current power supply;Modulation source circuit includes phase-locked loop, amplifier, modulator and first filter;Control circuit includes FPGA, and the memory, interface driver chip and at least one input link connected with the FPGA.This application's precoding source has the characteristics of simple structure, small, low in cost, multiple channels, wide range of application.

Description

Technical Field

[0001] This utility model relates to a signal encoding device, and more particularly to a miniaturized encoding source used in the testing of secondary surveillance radar equipment. Background Technology

[0002] Secondary Surveillance Radar (SSR) is a radio-electronic location and identification system that uses ground-based interrogation radar and aircraft-based transponder radar to identify and locate aerial targets. The basic working principle is as follows: the ground-based interrogation radar transmits interrogation signals with a specific coded pattern; the aircraft's transponder radar receives these signals, decodes them, and transmits a response signal encoded in a specific pattern. The ground-based radar, upon receiving the response signal, also decodes it to extract information such as the aircraft's identification code, altitude, bearing, range, and speed.

[0003] Therefore, when debugging and testing secondary surveillance radar equipment such as transmitters, receivers, and processing boards, it is necessary to provide codes that meet certain technical requirements in order to control the operation of the secondary surveillance radar equipment or simulate the coded signals used in actual work.

[0004] Traditional encoding sources offer dual or quad outputs. If more encoded signals are needed, multiple encoding sources must be used synchronously. The encoded signals must be set according to the instrument's operating specifications, requiring familiarity with the instrument's operation. All operations are generally completed via button switching, and the setup process is time-consuming. Traditional encoding sources only output low-frequency encoded signals; the radio frequency (RF) and intermediate frequency (IF) signals required for testing receivers or processing boards must be provided by additional instruments, such as an RF signal generator.

[0005] In general, traditional encoding sources are expensive, have few output channels, are large in size, are inconvenient to carry, and are complicated to operate. They can only provide digital encoded signals and are not suitable for secondary surveillance radar equipment that requires radio frequency signals. Utility Model Content

[0006] The purpose of this invention is to provide a miniaturized encoding source for testing secondary surveillance radar equipment, thereby solving the aforementioned problems of traditional encoding sources.

[0007] The technical solution adopted in this utility model is as follows: A miniaturized encoding source for testing secondary surveillance radar equipment includes a power conversion circuit, a control circuit, and a modulation source circuit. The power conversion circuit converts external AC power into working DC power, which powers the control circuit and the modulation source circuit respectively. The control circuit includes a programmable gate array (FPGA), a memory, an interface driver chip, and at least one input link connected to the FPGA; the input link includes a multi-channel gating switch, a driver, and an analog-to-digital converter (ADC) connected in sequence, and the ADC is connected to the FPGA; an external panel is connected to the interface driver chip, and the external panel includes external connectors and input / output devices; The modulation source circuit includes a phase-locked loop, an amplifier, a modulator, and a first filter connected in sequence. The phase-locked loop is connected to the FPGA, and the first filter is connected to the external connector.

[0008] Furthermore, the external connector includes a serial port, an Ethernet interface, and a discrete debugging interface.

[0009] Furthermore, the modulator includes an inverter, a fully controlled switch, and a driving circuit; the driving circuit receives a carrier signal; the input of the inverter is connected to the driving circuit, and the output is connected to the enable terminal of the fully controlled switch; the input of the fully controlled switch is connected to the amplifier, and the output is connected to the first filter.

[0010] Furthermore, a DC blocking capacitor and an attenuator are connected to the input terminal of the fully controlled switch.

[0011] Furthermore, the power conversion circuit includes an EMI filter circuit, a first AC / DC conversion circuit, a multi-channel DC / DC conversion circuit, and an enable circuit; the EMI filter circuit is connected to the external AC power supply; the input terminal of the first AC / DC conversion circuit is connected to the output terminal of the EMI filter circuit, and the output terminal of the first AC / DC conversion circuit is connected to the input terminal of each DC / DC conversion circuit, with each DC / DC conversion circuit having a different transformation ratio; the output terminal of the enable circuit is connected to the enable terminal of each DC / DC conversion circuit, and the input terminal of the enable circuit is connected to a switch control level.

[0012] Furthermore, the power conversion circuit also includes a power control panel; the power control panel is connected to an external AC power source through a second AC / DC conversion circuit; the power control panel is connected to the enable circuit, and the power control panel generates the switch control level through a DIP switch and / or an interactive interface.

[0013] Furthermore, the DC / DC conversion circuit includes a DC / DC power supply module and a power filter circuit; the input terminal of the power filter circuit is connected to the output terminal of the DC / DC power supply module, and the output terminal of the power filter circuit outputs working DC power.

[0014] Furthermore, the power supply filtering circuit includes a common-mode inductor, with its four terminals grounded through four Y capacitors, and X capacitors connected across the two input terminals and the two output terminals of the common-mode inductor.

[0015] Furthermore, it also includes a temperature sensor chip, which is connected to the FPGA.

[0016] Furthermore, it also includes voltage monitoring circuits and current monitoring circuits; The voltage monitoring circuit includes a first ADC, which is connected to at least one monitored voltage and connected to the FPGA; The current monitoring circuit includes a second ADC and at least one current detector. Each current detector is connected to a monitored current and is connected to the second ADC, which is connected to the FPGA.

[0017] In summary, due to the adoption of the above technical solution, the beneficial effects of this utility model are: The miniaturized encoding source proposed in this application features a simple structure, few components, compact size, and low manufacturing cost. Based on FPGA-based fully digital pulse signal generation, it exhibits high precision and high stability. The encoding source supports the generation of multiple time-dependent pulse codes, greatly facilitating the debugging, testing, and other needs of secondary surveillance radar equipment. Equipped with a modulation source circuit, the encoding source can output the RF signals required for testing secondary surveillance radar equipment. The encoding source also features a power conversion circuit, enabling direct access to the required DC power supply without the need for a separate DC regulated power supply. Furthermore, the encoding source is equipped with external connectors to adapt to various application environments. Attached Figure Description

[0018] Figure 1 It is the construction diagram of the encoding source.

[0019] Figure 2 It is the circuit design diagram of the control circuit.

[0020] Figure 3 This is the circuit diagram for an RS232 interface.

[0021] Figure 4 This is an Ethernet interface circuit diagram.

[0022] Figure 5 This is a diagram of the encoding source S-mode query signal format.

[0023] Figure 6 This is a diagram of the signal format of the encoding source's conventional response mode.

[0024] Figure 7 This is a diagram of the format of the S-mode response signal from the encoded source.

[0025] Figure 8 This is the design diagram of the modulation source circuit.

[0026] Figure 9 This is a power conversion circuit design diagram.

[0027] Figure 10 This is a power supply filter circuit design diagram.

[0028] Figure 11 These are design diagrams for voltage monitoring circuits and current monitoring circuits. Detailed Implementation

[0029] The present invention will now be described in detail with reference to the accompanying drawings.

[0030] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0031] To address the problems of traditional encoding sources, such as large size, high cost, few channels, complicated operation, inability to provide radio frequency signals, and unstable output voltage, this application provides a miniaturized encoding source for testing secondary surveillance radar equipment. It aims to provide an encoding source with multiple outputs, small size, low cost, simple operation, and the ability to output radio frequency signals and regulated power supplies.

[0032] like Figure 1 As shown, the miniaturized encoding source used for testing secondary surveillance radar equipment includes a control circuit, a modulation source circuit, and a power conversion circuit. The control circuit is responsible for generating all control signals within the encoding source, encoding output, status monitoring, and communication interface conversion. The modulation source circuit outputs the necessary interrogation or response radio frequency signals. The power conversion circuit converts the input 220VAC AC power into DC power required by the encoding source or external devices for equipment testing.

[0033] I. Control Circuit like Figure 2 As shown, the control circuit includes a programmable gate array (FPGA), a memory connected to the FPGA, an interface driver chip, and at least one input link. The input link includes a multi-channel gating switch, a driver, and an analog-to-digital converter (ADC) connected in sequence, with the ADC connected to the FPGA. An external panel is connected to the interface driver chip, and this external panel includes external connectors and input / output devices. These input / output devices include, for example, toggle switches, buttons, indicator lights, etc., to respond to coded level signals (button input), level signals (toggle switch input), or signals output by the FPGA (such as indicator lights illuminating).

[0034] The driver isolates the coded signals from the drive inputs, converting the signals input by the multi-channel gating switch into signals within a standard voltage range to facilitate accurate sampling by the ADC and reduce ADC sampling errors. Typically, the multi-channel gating switch has eight inputs. After the gating switch selects the input signal of a specific channel in a time-division multiplexing manner, the signal is converted to voltage by the driver, sampled by the ADC for analog-to-digital conversion, and then passed to the FPGA for further processing. If more input channels are needed, additional input links can be added accordingly.

[0035] The interface driver chip is responsible for driving the external panel, especially the external connectors on the external panel. Obviously, different interface driver chips are required to drive different interfaces. As an optional implementation, external connectors include serial ports, Ethernet interfaces, and discrete debugging interfaces, to adapt to different usage environments. For example, after the discrete debugging interface's driving capability is enhanced by the interface driver chip, it outputs the generated interrogation mode code and response mode code to the peripheral connected to the external connector. Serial ports and Ethernet interfaces output corresponding data using their respective serial port protocols and TCP / IP protocols.

[0036] The encoding source also includes a reference clock, which connects the FPGA and the modulation source circuitry to provide a reference clock for operation.

[0037] Specifically, the main controller of the encoding source is an FPGA, which can complete multi-channel data acquisition and processing in real time. Generating pulse signals based on an FPGA offers significant advantages in speed, accuracy, and stability compared to traditional digital pulse generators.

[0038] The ADC front end is connected to a multi-channel gating switch, which can perform fast channel switching. When operating in time-division multiplexing mode, it can acquire a total of 8 RF signals from 2 input links (the same applies to more input links).

[0039] Flash memory can be used as the storage device. Flash memory can store data (such as calibration parameters, threshold parameters, status parameters, etc.) to prevent data loss after power failure.

[0040] Toggle switches, buttons, indicator lights, and external connectors serve as peripheral controls and indicators. Toggle switches and buttons control whether coded signals are output or toggled; indicator lights indicate power supply and operating status. External connectors are signal output ports, featuring multiple connector interfaces, including serial ports, Ethernet interfaces, discrete debugging interfaces, low-frequency D-series rectangular connector interfaces, and RF interfaces.

[0041] Specifically, the external connector includes the following interfaces: (1) RS232 interface The RS232 driver is model MAX3232. The MAX3232 uses a proprietary low-dropout transmitter and a dual charge pump to achieve RS232 signal communication while powered by a 3.0–5.5V supply. The device requires only four 0.1μF charge pump capacitors, ensuring RS232 output at a data rate of 120Kbps. The hardware block diagram is shown below. Figure 3 As shown.

[0042] (2) Ethernet interface The network module integrates complex networking functions into the serial port device, with a maximum serial port transmission rate of 921.6kbps and support for 10 / 100Mbps Ethernet. It also offers several ready-to-use operating modes, converting devices with standard serial ports into Ethernet devices. The hardware block diagram is shown below. Figure 4 As shown.

[0043] (3) Discrete debugging interface Commonly used secondary monitoring radar encoded signals and synchronization signals are output through BNC connectors. BNC connectors are easy to use as they can be quickly plugged in and out. Most digital encoding sources and oscilloscopes use this type of connector.

[0044] (4) Low-frequency D-series rectangular connector interface Multiple IO signals from the FPGA are converted by the driver and output as discrete debug interfaces, connecting to DC-37 / DD-50 series connectors.

[0045] (5) Radio frequency interface The modulation source circuit outputs via an SMA connector, allowing for easy connection to test equipment such as receivers and processing boards.

[0046] The characteristics of a pulse signal are reflected in its pulse width, number of pulses, and period. The pulse width is a high-level signal of a certain duration or a low-level signal of a certain duration. A single transmitted signal consists of multiple pulses, with time intervals between them. Multiple pulses form a pulse train, and the relatively large time interval between one pulse train is called the pulse period. Using an FPGA to generate pulse signals, the generation of a pulse is controlled by two down-counters that control the duration of the high and low levels. The first down-counter is initially loaded with the high-level duration and then decreases its count with the clock cycle, stopping when it reaches zero. Simultaneously, the second down-counter is started, with its initial value being the low-level duration, also stopping when it reaches zero. This generates the pulse. By alternately controlling the high and low level durations with the two down-counters, the required pulse code can be generated.

[0047] The encoding source includes commonly used codes for secondary surveillance radar, including interrogation mode codes and response mode codes. According to ICAO (International Civil Aviation Organization) regulations, there are six conventional interrogation modes, designated as modes 1, 2, 3 / A, B, C, and D. The timing relationships of the P1 and P2 pulses, and the P1 and P3 pulses for each mode are shown in Table 1. The first pulse is called P1, the second pulse is called P2, and the third pulse is called P3. The format for pulses P1, P2, and P3 is a pulse width of (0.8 ± 0.1) μs. Figure 5 The diagram shows the S-mode interrogation format. The first two pulses, P1 and P2, have a pulse width of 0.8 μs and an interval of 2.0 μs. After pulse P2, a long pulse P6 appears, lasting either 16.25 μs or 30.25 μs. The M1, M2, MA, and MC response signal formats are as follows: Figure 6 As shown, the S-mode response encoding format is as follows: Figure 7 As shown.

[0048] Table 1. Pulse Time Relationship for Six Inquiry Modes

[0049] The discrete debugging interface for the encoding source enhances its driving capability through an interface driver chip, outputting the generated interrogation mode and response mode encodings to an external connector. This allows for direct selection of the corresponding encoding when testing secondary surveillance radar devices, eliminating the need to reset the encoding source each time and greatly simplifying debugging and testing. Furthermore, parameters such as pulse width, interval, number of pulses, and period can be configured via a visual interface such as a computer, facilitating the generation of arbitrary pulse waveforms, which users can customize as needed.

[0050] II. Modulation Source Circuit The modulation source circuit includes a phase-locked loop (PLL), an amplifier, a modulator, and a first filter connected in sequence. The PLL generates a radio frequency (RF) signal. The amplifier amplifies the RF signal, the modulator modulates the video signal, and the first filter filters the modulated signal.

[0051] like Figure 8 As shown, the reference clock provides a reference signal for the phase-locked loop (PLL) circuit. Compared with DDS and frequency multiplier circuits, the PLL circuit has higher frequency accuracy and can output RF signals with frequencies of 1090MHz±0.01MHz / 1030MHz±0.01MHz. The output signal amplitude is approximately 0dBm, which is amplified to about 15dBm by an amplifier, and the operating voltage is +5V.

[0052] In one optional implementation, the modulator is a surface-mount modulator comprising an inverter, a fully controlled switch, and a drive circuit. The drive circuit receives the carrier signal; the input of the inverter is connected to the drive circuit, and its output is connected to the enable terminal of the fully controlled switch; the input of the fully controlled switch is connected to an amplifier, and its output is connected to a first filter. The modulator outputs secondary surveillance radar modulation codes through a control board circuit, which can perform amplitude and phase modulation on the carrier signal. Simultaneously, the control board circuit can control the frequency of the output interrogation signal or response signal. A DC blocking capacitor and an attenuator can be added between the modulator's input and output. Specifically, a DC blocking capacitor and an attenuator are connected to the input of the fully controlled switch, and an attenuator can also be connected to the output. The DC blocking capacitor prevents DC components from damaging the device, and the attenuator adjusts the power and performs impedance matching. Decoupling and filtering capacitors are added to the modulator's power supply to ensure stable output signal amplitude.

[0053] In addition, a second filter is connected between the amplifier and the modulator. This second filter filters the amplified radio frequency signal to improve the accuracy of the radio frequency signal.

[0054] III. Power Conversion Circuit The power conversion circuit converts external AC power into working DC power to power the control circuit and the modulation source circuit, and can even output DC power to peripheral devices.

[0055] The power conversion circuit includes an EMI filter circuit, a first AC / DC conversion circuit, a multi-channel DC / DC conversion circuit, and an enable circuit. The EMI filter circuit is connected to an external AC power supply. The input of the first AC / DC conversion circuit is connected to the output of the EMI filter circuit, and the output of the first AC / DC conversion circuit is connected to the input of each of the multiple DC / DC conversion circuits, each with a different transformation ratio. The output of the enable circuit is connected to the enable terminal of each of the multiple DC / DC conversion circuits, and the input of the enable circuit is connected to a switch control level.

[0056] The DC / DC conversion circuit includes a DC / DC power supply module and a power filter circuit. The input terminal of the power filter circuit is connected to the output terminal of the DC / DC power supply module, and the output terminal of the power filter circuit outputs the working DC power supply.

[0057] The power conversion circuit achieves local power control through hard switching. The input 220VAC power is switched on via a power switch. After passing through an EMI filter circuit and a first AC / DC conversion circuit, the 220VAC AC power is converted to 24VDC DC power. Then, through four isolated DC / DC power modules (this is just an example; other numbers may exist), the input 24V voltage is converted to the DC voltage type required by the load (such as 12V, 5V, 50V, etc.). Each DC / DC conversion circuit has a different transformation ratio, simultaneously achieving power input / output isolation. Figure 9 As shown. Each DC / DC power module can be a commercially available power module, giving the entire power conversion circuit advantages such as small size, high conversion efficiency, and low electromagnetic radiation.

[0058] The power conversion circuit may also include a power control panel. The power control panel connects to an external AC power source via a second AC / DC conversion circuit, converting 220VAC to the required DC power. The power control panel is connected to an enable circuit, which generates a switch control level via a DIP switch and / or an interactive interface. This switch control level controls the enable circuit to turn each DC / DC power module on or off.

[0059] The EMI filter circuit adopts a three-stage EMI filter structure, using a common-mode filter inductor in conjunction with a differential-mode and common-mode filter capacitor for filtering, which can ensure the normal operation of the equipment and have good electromagnetic compatibility.

[0060] The DC / DC power module adopts a flyback and synchronous rectification topology. Through the coupling and isolation of the power transformer, a quasi-square wave voltage is obtained on the secondary side. This voltage is then rectified and filtered to obtain the required output voltage. This voltage is then passed through a voltage feedback circuit to adjust the duty cycle, achieving a constant output voltage. The input is equipped with undervoltage and overvoltage protection circuits, while the output is equipped with overvoltage, overcurrent, and short-circuit protection circuits.

[0061] The power supply filtering circuit mainly consists of capacitors and a common-mode inductor. The capacitors are a combination of electrolytic and ceramic capacitors, which reduce low-frequency and high-frequency noise interference. Specifically, the power supply filtering circuit includes a common-mode inductor. The four terminals of the common-mode inductor are grounded through four Y capacitors. X capacitors are connected across the two input terminals and the two output terminals of the common-mode inductor, respectively. Figure 10 As shown.

[0062] The encoding source includes the following status monitoring: (1) Monitoring of plate-level operating temperature The encoding source also includes a temperature sensor chip, which is connected to the FPGA.

[0063] Temperature monitoring of the FPGA board, first / second ADC conversion circuits, and DC / DC power supply module areas is achieved using the AD7414 temperature sensor chip. This temperature sensor chip can measure temperatures from -55℃ to 125℃ and includes a bandgap temperature sensor and a 10-bit ADC for control and digitizing the temperature readings, with an accuracy of 0.25℃. Its on-chip temperature sensor can accurately measure ambient temperature with a measurement accuracy of ±0.5 degrees Celsius.

[0064] (2) Monitoring of working voltage and current The encoding source also includes voltage monitoring circuitry and current monitoring circuitry. The voltage monitoring circuitry includes a first ADC, which is connected to at least one monitored voltage and to the FPGA. The current monitoring circuitry includes a second ADC and at least one current detector, each connected to a monitored current and to the second ADC, which is connected to the FPGA.

[0065] The module power supply voltage, clock management operating voltage, FPGA core voltage, and other voltages are monitored and acquired using the ADS7828 (the first ADC). The module power supply current, clock management operating current, and FPGA core current are monitored and acquired using current detectors INA180 and ADS7828 (the second ADC), respectively. The first and second ADCs can be the same ADC. Figure 11 The diagram shown illustrates the circuit diagram where the voltage monitoring circuit and the current monitoring circuit use the same ADC.

[0066] The encoding source of this application has the following characteristics: 1) The pulse signals generated by FPGA-based full digitalization have the characteristics of high precision and high stability. The commonly used secondary monitoring radar encoded signals and synchronization signals are output through BNC connectors. Multiple FPGA IO signals are output through low-frequency connectors after level conversion. At the same time, multiple pulse codes with time-related arbitrary waveforms can be generated, which greatly facilitates the debugging and testing needs of secondary monitoring radar equipment and meets general requirements.

[0067] 2) The encoding source has a built-in small-signal radio frequency modulation source circuit, which can output radio frequency signals that meet the requirements of secondary monitoring radar. When using the encoding source of this application to test secondary monitoring radar equipment, there is no need to use an additional radio frequency signal source.

[0068] 3) The encoding source has a built-in power conversion circuit to convert to common DC power. When using the encoding source of this application to test secondary monitoring radar equipment, the need for a separate DC regulated power supply can be reduced or eliminated.

[0069] 4) The encoding source can be connected to a computer for debugging via serial port or network port, or it can run independently, adapting to different application environments. It is easy to operate and improves testing efficiency.

[0070] 5) Compared with existing signal generators, the encoding source of this application is designed with multiple functions in mind, resulting in a small size, full functionality, reduced manufacturing costs, and easy portability and use.

[0071] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A miniaturized encoding source for testing secondary surveillance radar equipment, characterized in that, Includes power conversion circuit, control circuit, and modulation source circuit; The power conversion circuit converts external AC power into working DC power, which powers the control circuit and the modulation source circuit respectively. The control circuit includes a programmable gate array (FPGA), a memory, an interface driver chip, and at least one input link connected to the FPGA; the input link includes a multi-channel gating switch, a driver, and an analog-to-digital converter (ADC) connected in sequence, and the ADC is connected to the FPGA; an external panel is connected to the interface driver chip, and the external panel includes external connectors and input / output devices; The modulation source circuit includes a phase-locked loop, an amplifier, a modulator, and a first filter connected in sequence. The phase-locked loop is connected to the FPGA, and the first filter is connected to the external connector.

2. The miniaturized encoding source as described in claim 1, characterized in that, The external connectors include serial ports, Ethernet interfaces, and discrete debugging interfaces.

3. The miniaturized encoding source as described in claim 1, characterized in that, The modulator includes an inverter, a fully controlled switch, and a driving circuit; the driving circuit receives a carrier signal; the input of the inverter is connected to the driving circuit, and the output is connected to the enable terminal of the fully controlled switch; the input of the fully controlled switch is connected to the amplifier, and the output is connected to the first filter.

4. The miniaturized encoding source as described in claim 3, characterized in that, A DC blocking capacitor and an attenuator are connected to the input terminal of the fully controlled switch.

5. The miniaturized encoding source as described in claim 1, characterized in that, The power conversion circuit includes an EMI filter circuit, a first AC / DC conversion circuit, a multi-channel DC / DC conversion circuit, and an enable circuit. The EMI filter circuit is connected to the external AC power supply. The input terminal of the first AC / DC conversion circuit is connected to the output terminal of the EMI filter circuit, and the output terminal of the first AC / DC conversion circuit is connected to the input terminal of each DC / DC conversion circuit. Each DC / DC conversion circuit has a different transformation ratio. The output terminal of the enable circuit is connected to the enable terminal of each DC / DC conversion circuit, and the input terminal of the enable circuit is connected to a switch control level.

6. The miniaturized encoding source as described in claim 5, characterized in that, The power conversion circuit also includes a power control panel; the power control panel is connected to an external AC power source through a second AC / DC conversion circuit; the power control panel is connected to the enable circuit, and the power control panel generates the switch control level through a DIP switch and / or an interactive interface.

7. The miniaturized encoding source as described in claim 5, characterized in that, The DC / DC conversion circuit includes a DC / DC power supply module and a power filter circuit; the input terminal of the power filter circuit is connected to the output terminal of the DC / DC power supply module, and the output terminal of the power filter circuit outputs working DC power.

8. The miniaturized encoding source as described in claim 7, characterized in that, The power supply filtering circuit includes a common-mode inductor, with its four terminals grounded through four Y capacitors. An X capacitor is connected between the two input terminals and between the two output terminals of the common-mode inductor.

9. The miniaturized encoding source as described in claim 1, characterized in that, It also includes a temperature sensor chip, which is connected to the FPGA.

10. The miniaturized encoding source as described in claim 1, characterized in that, It also includes voltage monitoring circuitry and current monitoring circuitry; The voltage monitoring circuit includes a first ADC, which is connected to at least one monitored voltage and connected to the FPGA; The current monitoring circuit includes a second ADC and at least one current detector. Each current detector is connected to a monitored current and is connected to the second ADC, which is connected to the FPGA.

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