Array substrate, display panel and display device

Abstract

The application provides an array substrate, comprising a plurality of pixel units, each pixel unit comprising a first sub-pixel, a second sub-pixel and a third sub-pixel, the first sub-pixel comprising a first pixel electrode unit, the second sub-pixel comprising a second pixel electrode unit, and the third sub-pixel comprising a third pixel electrode unit, the first pixel electrode unit, the second pixel electrode unit and the third pixel electrode unit each comprising a plurality of pixel electrodes, and the third sub-pixel being a blue sub-pixel. The width of the pixel electrodes in the third pixel electrode unit is less than or equal to the width of the pixel electrodes in the first pixel electrode unit and less than or equal to the width of the pixel electrodes in the second pixel electrode unit; and / or the slit width between the pixel electrodes in the third pixel electrode unit is greater than the slit width between the pixel electrodes in the first pixel electrode unit and greater than the slit width between the pixel electrodes in the second pixel electrode unit. The application also provides a display panel and a display device.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate, a display panel having the array substrate, and a display device having the display panel. Background Technology

[0002] Liquid crystal displays (LCDs) are display devices that are controlled and stimulated by an external backlight source. They are widely used in the display industry due to their advantages such as low power consumption, no radiation, soft image quality, and low manufacturing cost. Liquid crystal efficiency, as the performance characteristic of an LCD during the display process, mainly includes indicators such as transmittance and response time. Since the backlight is mixed light, different colors of light have different wavelengths, and different wavelengths have corresponding transmittance. Theoretically, each of the three colors—red, green, and blue (RGB)—has an optimal transmittance Δnd, where Δn is the refractive index of the liquid crystal and d is the cell thickness.

[0003] To maximize transmittance, existing display devices typically design their transmittance Δnd to match the wavelength of green light. However, for blue light, Δnd exceeds the peak transmittance of blue light. Therefore, as the viewing angle increases, the corresponding Δnd for blue light also increases, causing the brightness of blue light to initially increase and then decrease. This often results in a yellowish color shift on the screen at large viewing angles, reducing image quality and ultimately affecting the display's performance.

[0004] Therefore, how to solve the color shift phenomenon that frequently occurs in existing liquid crystal display devices is a problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0005] In view of the shortcomings of the prior art, the purpose of this application is to provide an array substrate, a display panel having the array substrate, and a display device having the display panel, which aims to solve the color shift problem of yellowish tint at wide viewing angles that often occurs in existing liquid crystal display devices.

[0006] To address the aforementioned technical problems, this application provides an array substrate comprising multiple pixel units. Each pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel includes a first pixel electrode unit, the second sub-pixel includes a second pixel electrode unit, and the third sub-pixel includes a third pixel electrode unit. Each of the first, second, and third pixel electrode units includes multiple pixel electrodes, and the third sub-pixel is a blue sub-pixel. The width of the pixel electrode within the third pixel electrode unit is less than or equal to the width of the pixel electrode within the first pixel electrode unit and less than or equal to the width of the pixel electrode within the second pixel electrode unit; and / or, the slit width between adjacent pixel electrodes within the third pixel electrode unit is greater than the slit width between adjacent pixel electrodes within the first pixel electrode unit and greater than the slit width between adjacent pixel electrodes within the second pixel electrode unit.

[0007] In summary, in the array substrate provided by this application, the width of the pixel electrode in the third pixel electrode unit is less than or equal to the width of the pixel electrode in the first pixel electrode unit and less than or equal to the width of the pixel electrode in the second pixel electrode unit; and / or, the slit width of adjacent pixel electrodes in the third pixel electrode unit is greater than the slit width of adjacent pixel electrodes in the first pixel electrode unit and greater than the slit width of adjacent pixel electrodes in the second pixel electrode unit. Therefore, for different sub-pixels in each pixel unit, the width of the strip pixel electrode of the blue sub-pixel and / or the slit width between adjacent strip pixel electrodes can be designed accordingly to improve the transmittance of the sub-pixel as needed, for example, by reducing the width of the pixel electrode of the blue sub-pixel and / or increasing the slit width between adjacent pixel electrodes of the blue sub-pixel, so that the liquid crystal efficiency of the third sub-pixel is less than that of the first sub-pixel and the second sub-pixel, solving the color shift phenomenon of yellowish tint that usually occurs in screen displays at large viewing angles, increasing the display quality of the display device containing the array substrate, and thus improving the display effect of the display device.

[0008] In an exemplary embodiment, the first pixel electrode unit includes four first pixel electrode regions and a plurality of first pixel electrodes, the plurality of first pixel electrodes being located within the first pixel electrode regions, and the plurality of first pixel electrodes located within the same first pixel electrode region being arranged parallel and spaced apart; the second pixel electrode unit includes four second pixel electrode regions and a plurality of second pixel electrodes, the plurality of second pixel electrodes being located within the second pixel electrode regions, and the plurality of second pixel electrodes located within the same second pixel electrode region being arranged parallel and spaced apart; the third pixel electrode unit includes four third pixel electrode regions and a plurality of third pixel electrodes, the plurality of third pixel electrodes being located within the third pixel electrode regions, and the plurality of third pixel electrodes located within the same third pixel electrode region being arranged parallel and spaced apart.

[0009] In an exemplary embodiment, the sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between adjacent third pixel electrodes is greater than the sum of the width of the first pixel electrode in the first pixel electrode unit and the slit width between adjacent first pixel electrodes, and the width of the third pixel electrode in the third pixel electrode unit is equal to the width of the first pixel electrode in the first pixel electrode unit; the sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between adjacent third pixel electrodes is greater than the sum of the width of the second pixel electrode in the second pixel electrode unit and the slit width between adjacent second pixel electrodes, and the width of the third pixel electrode in the third pixel electrode unit is equal to the width of the second pixel electrode in the second pixel electrode unit; the width of the first pixel electrode in the first pixel electrode unit is equal to the slit width between the first pixel electrodes, and the width of the second pixel electrode in the second pixel electrode unit is equal to the slit width between the second pixel electrodes.

[0010] In an exemplary embodiment, the sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between adjacent third pixel electrodes is greater than the sum of the width of the first pixel electrode in the first pixel electrode unit and the slit width between adjacent first pixel electrodes, and the width of the third pixel electrode in the third pixel electrode unit is less than the width of the first pixel electrode in the first pixel electrode unit; the sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between adjacent third pixel electrodes is greater than the sum of the width of the second pixel electrode in the second pixel electrode unit and the slit width between adjacent second pixel electrodes, and the width of the third pixel electrode in the third pixel electrode unit is less than the width of the second pixel electrode in the second pixel electrode unit.

[0011] In an exemplary embodiment, the sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between adjacent third pixel electrodes is greater than the sum of the width of the first pixel electrode in the first pixel electrode unit and the slit width between adjacent first pixel electrodes. The width of the first pixel electrode in the first pixel electrode unit is greater than half the sum of the width of the first pixel electrode in the first pixel electrode unit and the slit width between the first pixel electrodes. The width of the third pixel electrode in the third pixel electrode unit is less than half the sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between the third pixel electrodes, and is less than the width of the first pixel electrode in the first pixel electrode unit. The width of the third pixel electrode in the third pixel electrode unit is greater than the sum of the width of the second pixel electrode in the second pixel electrode unit and the slit width between adjacent third pixel electrodes. The width of the second pixel electrode in the second pixel electrode unit is greater than half the sum of the width of the second pixel electrode in the second pixel electrode unit and the slit width between adjacent second pixel electrodes. The width of the third pixel electrode in the third pixel electrode unit is less than half the sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between adjacent second pixel electrodes, and is less than the width of the second pixel electrode in the second pixel electrode unit.

[0012] In an exemplary embodiment, the sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between the third pixel electrode is greater than the sum of the width of the first pixel electrode in the first pixel electrode unit and the slit width between the first pixel electrodes. The width of the first pixel electrode in the first pixel electrode unit is less than half the sum of the width of the first pixel electrode in the first pixel electrode unit and the slit width between the first pixel electrodes. Furthermore, the sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between the third pixel electrode is greater than the sum of the width of the second pixel electrode in the second pixel electrode unit and the slit width between the second pixel electrodes. The width of the second pixel electrode in the second pixel electrode unit is less than half the sum of the width of the second pixel electrode in the second pixel electrode unit and the slit width between the second pixel electrodes. And the width of the third pixel electrode in the third pixel electrode unit is less than the width of the second pixel electrode in the second pixel electrode unit.

[0013] In an exemplary embodiment, the sum of the width of the third pixel electrode within the third pixel electrode unit and the slit width between adjacent third pixel electrodes is equal to the sum of the width of the first pixel electrode within the first pixel electrode unit and the slit width between adjacent first pixel electrodes. The width of the first pixel electrode within the first pixel electrode unit is greater than or equal to half the sum of the width of the first pixel electrode within the first pixel electrode unit and the slit width between the first pixel electrodes. Furthermore, the width of the third pixel electrode within the third pixel electrode unit is less than the sum of the width of the third pixel electrode within the third pixel electrode unit and the slit width between adjacent third pixel electrodes. The sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between adjacent third pixel electrodes is equal to the sum of the width of the second pixel electrode in the second pixel electrode unit and the slit width between adjacent second pixel electrodes. The width of the second pixel electrode in the second pixel electrode unit is greater than or equal to half the sum of the width of the second pixel electrode in the second pixel electrode unit and the slit width between adjacent second pixel electrodes. The width of the third pixel electrode in the third pixel electrode unit is less than half the sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between adjacent third pixel electrodes.

[0014] In an exemplary embodiment, the ratio of the width of the third pixel electrode within the same third pixel electrode region of the third pixel electrode unit to the slit width between adjacent third pixel electrodes is less than 1.

[0015] Based on the same technical concept, this application embodiment also provides a display panel, the display panel including a color filter substrate, a liquid crystal layer and the above-mentioned array substrate, the array substrate being opposite to and spaced apart from the color filter substrate, and the liquid crystal layer being disposed between the array substrate and the color filter substrate.

[0016] Based on the same technical concept, this application embodiment also provides a display device, the display device including a backlight module and the above-mentioned display panel, the display panel being disposed on the light-emitting side of the backlight module, and the backlight module being used to emit backlight light to the display panel.

[0017] In summary, the display device provided in this application includes a backlight module and a display panel. The display panel is disposed on the light-emitting side of the backlight module, and the backlight module is used to emit backlight light to the display panel. The display panel includes a color filter substrate, a liquid crystal layer, and an array substrate, with the liquid crystal layer disposed between the array substrate and the color filter substrate. The array substrate includes a plurality of pixel units, each pixel unit including a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel includes a first pixel electrode unit, the second sub-pixel includes a second pixel electrode unit, and the third sub-pixel includes a third pixel electrode unit. Each of the first, second, and third pixel electrode units includes a plurality of pixel electrodes, and the third sub-pixel is a blue sub-pixel. The width of the pixel electrode in the third pixel electrode unit is less than or equal to the width of the pixel electrode in the first pixel electrode unit and less than or equal to the width of the pixel electrode in the second pixel electrode unit; and / or, the slit width of adjacent pixel electrodes in the third pixel electrode unit is greater than the slit width of adjacent pixel electrodes in the first pixel electrode unit and greater than the slit width of adjacent pixel electrodes in the second pixel electrode unit. Therefore, for different sub-pixels in each pixel unit, the width of the strip-shaped pixel electrode of the blue sub-pixel and / or the slit width between adjacent strip-shaped pixel electrodes can be designed accordingly to improve the transmittance of the sub-pixel as needed. For example, reducing the width of the pixel electrode of the blue sub-pixel and / or increasing the slit width between adjacent pixel electrodes of the blue sub-pixel can reduce the liquid crystal efficiency of the third sub-pixel, making the liquid crystal efficiency of the third sub-pixel lower than that of the first sub-pixel and lower than that of the second sub-pixel. This solves the color shift phenomenon of yellowish tint that commonly occurs in screen displays at large viewing angles, increases the display quality of the display panel and display device, and thus improves the display effect of the display device. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the layer structure of the display device disclosed in the first embodiment of this application.

[0020] Figure 2 This is a schematic diagram of the circuit structure of the display device disclosed in the first embodiment of this application.

[0021] Figure 3 This is a front view structural diagram of the display panel disclosed in the second embodiment of this application.

[0022] Figure 4 This is a schematic diagram of the circuit structure of the array substrate disclosed in the third embodiment of this application.

[0023] Figure 5 for Figure 4 A schematic diagram of the first structure of pixel electrodes for different sub-pixels within the pixel unit shown.

[0024] Figure 6 for Figure 5 The diagram shows the dimensions of the pixel electrodes for different sub-pixels.

[0025] Figure 7 for Figure 4 The diagram shows a second structural schematic of the pixel electrodes of different sub-pixels within the pixel unit shown.

[0026] Figure 8 for Figure 7 The diagram shows the dimensions of the pixel electrodes for different sub-pixels.

[0027] Explanation of reference numerals in the attached figures: 1-Display device; 10-Backlight module; 30-Display panel; 50-Driving circuit unit; 51-Scan driving circuit; 52-Data driving circuit; 53-Timing control circuit; 30a-Display area; 30b-Non-display area; 001-First direction; 002-Second direction; DL-Scan line; GL-Data line; SP-Pixel unit; 32-Array substrate; 32a-First sub-pixel; 32b-Second sub-pixel; 32c-Third sub-pixel; 320-First pixel electrode unit; 322-Second pixel electrode unit; 324-Third pixel electrode unit; 3202-First pixel electrode area; 3204-First pixel electrode; 3222-Second pixel electrode area; 3224-Second pixel electrode; 3242-Third pixel electrode area; 3244-Third pixel electrode. Detailed Implementation

[0028] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0029] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. The component designations used herein, such as "first," "second," etc., are merely for distinguishing the described objects and have no sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages). Directional terms used in this application, such as "up," "down," "front," "back," "left," "right," "inner," "outer," "side," etc., are merely for reference to the accompanying illustrations. Therefore, the use of directional terms is for better and clearer explanation and understanding of this application, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.

[0030] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joint" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising," "may include," "include," or "may include" used in this application indicate the presence of the corresponding disclosed function, operation, element, etc., and do not limit one or more other functions, operations, elements, etc. Moreover, the terms "comprising" or "include" indicate the presence of the corresponding features, number, steps, operations, elements, components, or combinations thereof disclosed in the specification, but do not exclude the presence or addition of one or more other features, number, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusion. It is also important to understand that “at least one” as described in this article means one or more, such as one, two or three, while “multiple” means at least two, such as two or three, unless otherwise explicitly specified.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0032] Please see Figure 1 , Figure 1 This is a schematic diagram of the layer structure of the display device disclosed in the first embodiment of this application. In the embodiments of this application, Figure 1 The display device 1 shown may include a backlight module 10 and a display panel 30. The display panel 30 is disposed on the light-emitting side of the backlight module 10. The backlight module 10 is used to emit backlight light to the display panel 30. The display panel 30 is used to display images under the light provided by the backlight module 10.

[0033] In an exemplary embodiment, the backlight module 10 may be a direct-lit backlight module, or it may be an edge-lit backlight module; this application does not impose specific limitations on this. For ease of explanation and description, this application uses a direct-lit backlight module 10 as an example for illustration. The display panel 30 may be a Twisted Nematic (TN) display panel, a Vertical Alignment (VA) display panel, an In-Plane Switching (IPS) display panel, or a Fringe Field Switching (FFS) display panel; this application does not impose specific limitations on this.

[0034] Please see Figure 2 , Figure 2 This is a schematic diagram of the circuit structure of the display device disclosed in the first embodiment of this application. In this embodiment, the display device 1 further includes a driving circuit unit 50, which is electrically connected to the display panel 30. The driving circuit unit 50 is used to provide the display panel 30 with driving electrical signals required for displaying images. The driving circuit unit 50 may include a scan driving circuit 51, a data driving circuit 52, and a timing control circuit 53. The display panel 30 is electrically connected to both the scan driving circuit 51 and the data driving circuit 52, and the timing control circuit 53 is electrically connected to both the scan driving circuit 51 and the data driving circuit 52.

[0035] Specifically, the scan driving circuit 51 is used to output a scan signal to the display panel 30, and the data driving circuit 52 is used to output a data signal to the display panel 30. The timing control circuit 53 is used to output a timing control signal to the scan driving circuit 51 to control when the scan driving circuit 51 outputs the scan signal to the display panel 30, and the timing control circuit 53 is also used to output a timing control signal to the data driving circuit 52 to control when the data driving circuit 52 outputs the data signal to the display panel 30. The timing control signal includes a CLK signal and an STV signal.

[0036] It is understood that the data driving circuit 52 may include multiple data driving integrated circuits. These multiple data driving integrated circuits may be connected to bonding pads of a tape-on-glide (TAB) or chip-on-glass (COG) type display panel 30, or, depending on the situation, may be directly integrated into the display panel 30. Depending on the driving type, the scan driving circuit 51 may be located on only one side of the display panel 30, or two scan driving circuits 51 may be located on both sides of the display panel 30. Additionally, the scan driving circuit 51 may include multiple gate driving integrated circuits, and these gate driving integrated circuits may be connected to bonding pads of a TAB or COG type display panel 30. Alternatively, the gate driving integrated circuits may be implemented as gate-in-panel (GIP) type and may be directly located in the display panel 30. Depending on the situation, the gate driving integrated circuits may also be integrated into the display panel 30.

[0037] In other embodiments of this application, the driving circuit unit 50 may further include circuitry for driving the backlight module 10 to emit light.

[0038] In other embodiments of this application, the display device 1 may further include a processor and a memory. The processor is electrically connected to the display panel 30 and is used to control the display panel 30 to display content. The memory is electrically connected to the processor and is used to store program code required for the processor to run, control the display content of the display panel 30, etc.

[0039] In an exemplary embodiment, the memory may include volatile memory, such as random access memory (RAM); the memory may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory (FM), hard disk drive (HDD), or solid-state drive (SSD). The memory may also include combinations of the above types of memory.

[0040] In an exemplary embodiment, the processor includes one or more general-purpose processors, wherein the general-purpose processor can be any type of device capable of processing electronic instructions, including a central processing unit (CPU), microprocessor, microcontroller, main processor, and controller, etc. The processor is used to execute various types of digital storage instructions, such as software or firmware programs stored in the memory, which enable the computing device to provide a wide range of services.

[0041] In an exemplary embodiment, the display device 1 may also include other necessary components and parts such as a driver board, a power board, a high-voltage board, and a button control board. Those skilled in the art can supplement these components according to the specific type and actual function of the display device 1, and will not elaborate further here.

[0042] In this embodiment, the display device 1 can be a liquid crystal display (LCD). In an exemplary embodiment, the display device 1 can be a thin film transistor liquid crystal display (TFT-LCD).

[0043] Understandably, some display products need to be used both indoors and outdoors. To meet their indoor / outdoor application requirements, the display device 1 uses transflective display technology. Transflective display technology refers to using a portion of the pixel area as a reflective area and the remaining area as a transmittance area. It displays images by illuminating them with light from an external light source and a backlight built into the display device, thus enabling use both indoors and outdoors.

[0044] Understandably, the display device 1 can be used in electronic devices including but not limited to televisions, tablets, laptops, desktop computers, mobile phones, in-vehicle displays, smartwatches, smart bracelets, and smart glasses. According to the embodiments of this application, the specific type of the display device 1 is not particularly limited, and those skilled in the art can design it accordingly based on the specific usage requirements of the display device 1; further details will not be elaborated here.

[0045] Please see Figure 3 , Figure 3This is a front view schematic diagram of the display panel disclosed in the second embodiment of this application. In this embodiment, the display panel 30 includes a display area 30a and a non-display area 30b surrounding the display area 30a. The display area 30a is used to display images, and the non-display area 30b is used to house other auxiliary display components or driving circuits and signal lines to control the display area 30a to display images.

[0046] Understandably, in this embodiment, the display panel 30 further includes an array substrate, a liquid crystal layer, and a color filter substrate stacked together. The array substrate and the color filter substrate are disposed opposite to each other and spaced apart. The liquid crystal layer is disposed between the array substrate and the color filter substrate, i.e., the color filter substrate is disposed on the side of the liquid crystal layer facing away from the array substrate. Part of the array substrate is located in the display area 30a, and part of the array substrate is located in the non-display area 30b. The liquid crystal layer is located in the display area 30a, and part of the color filter substrate is located in the display area 30a and part of the color filter substrate is located in the non-display area 30b. The liquid crystal layer includes a plurality of liquid crystal molecules. The array substrate and the color filter substrate are used to form a preset electric field. The preset electric field is used to drive the plurality of liquid crystal molecules to deflect, thereby controlling the transmittance of the liquid crystal layer and enabling the display panel 30 to display different grayscale brightness levels.

[0047] Please see Figure 4 , Figure 4 This is a schematic diagram of the circuit structure of the array substrate disclosed in the third embodiment of this application. In this embodiment, Figure 4 The array substrate 32 shown includes multiple scan lines GL, multiple data lines DL, and multiple pixel units SP. The multiple scan lines GL extend along a first direction 001 and are arranged in parallel intervals along a second direction 002. The multiple data lines DL extend along the second direction 002 and are arranged in parallel intervals along the first direction 001. The pixel units SP are disposed between two adjacent scan lines GL and two adjacent data lines DL. The pixel units SP are electrically connected to the scan lines GL and the data lines DL, respectively. The scan lines GL are also electrically connected to the scan driving circuit 51, and the data lines DL are also electrically connected to the data driving circuit 52. The scan signal output by the scan driving circuit 51 is transmitted to the pixel unit SP through the scan lines GL, and the data signal output by the data driving circuit 52 is transmitted to the pixel unit SP through the data lines DL.

[0048] It is understood that one scan line GL intersects with and is insulated from multiple data lines DL, and one data line DL intersects with and is insulated from multiple scan lines GL, i.e., the multiple scan lines GL and multiple data lines DL are arranged in a grid pattern. One pixel unit SP is electrically connected to one scan line GL and one data line DL. Specifically, a pixel unit SP is disposed between any two adjacent scan lines GL and any two adjacent data lines DL; pixel units SP located in the same column are all electrically connected to the same data line DL; and pixel units SP located in the same row are all electrically connected to the same scan line GL. In this embodiment, the multiple pixel units SP are arranged in an array.

[0049] In an exemplary embodiment, the first direction 001 is perpendicular to the second direction 002, the plurality of scan lines GL are arranged at intervals and are insulated from each other, and the plurality of data lines DL are arranged at intervals and are insulated from each other.

[0050] In this embodiment, each pixel unit SP includes three sub-pixels for displaying different colors. The three sub-pixels emit red, green, and blue light respectively, enabling the pixel unit SP to display color. That is, the array substrate 32 includes multiple pixel units SP, and each pixel unit SP includes three sub-pixels. In other embodiments, each pixel unit SP may include four sub-pixels, for example, a red (R) sub-pixel, a green (G) sub-pixel, a blue (B) sub-pixel, and a white (W) sub-pixel. Each sub-pixel includes a pixel electrode unit, and each pixel electrode unit includes multiple pixel electrodes. The pixel electrodes may be strip-shaped to enhance edge field effects.

[0051] In a specific embodiment of this application, each pixel unit SP includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel, the second sub-pixel, and the third sub-pixel can emit red light, green light, and blue light, respectively, enabling the pixel unit SP to display color. That is, the first sub-pixel can be a red (R) sub-pixel, the second sub-pixel can be a green (G) sub-pixel, and the third sub-pixel can be a blue (B) sub-pixel. Each pixel unit SP includes a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. The first sub-pixel includes a first pixel electrode unit, the second sub-pixel includes a second pixel electrode unit, and the third sub-pixel includes a third pixel electrode unit, wherein each of the first pixel electrode unit, the second pixel electrode unit, and the third pixel electrode unit includes multiple pixel electrodes.

[0052] In this embodiment of the application, the sum of the width of the pixel electrode in the third pixel electrode unit and the slit width between adjacent pixel electrodes is greater than or equal to the sum of the width of the pixel electrode in the first pixel electrode unit and the slit width between the pixel electrodes; and / or, the width of the pixel electrode in the third pixel electrode unit is less than the width of the pixel electrode in the first pixel electrode unit and the second pixel electrode unit.

[0053] In this embodiment of the application, the width of the pixel electrode in the third pixel electrode unit is less than or equal to the width of the pixel electrode in the first pixel electrode unit and less than or equal to the width of the pixel electrode in the second pixel electrode unit; and / or, the slit width of adjacent pixel electrodes in the third pixel electrode unit is greater than the slit width of adjacent pixel electrodes in the first pixel electrode unit and greater than the slit width of adjacent pixel electrodes in the second pixel electrode unit.

[0054] In summary, the array substrate provided in this application includes multiple pixel units. Each pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel includes a first pixel electrode unit, the second sub-pixel includes a second pixel electrode unit, and the third sub-pixel includes a third pixel electrode unit. Each of the first, second, and third pixel electrode units includes multiple pixel electrodes, and the third sub-pixel is a blue sub-pixel. The width of the pixel electrode within the third pixel electrode unit is less than or equal to the width of the pixel electrode within the first pixel electrode unit and less than or equal to the width of the pixel electrode within the second pixel electrode unit; and / or, the slit width of adjacent pixel electrodes within the third pixel electrode unit is greater than the slit width of adjacent pixel electrodes within the first pixel electrode unit and greater than the slit width of adjacent pixel electrodes within the second pixel electrode unit. Therefore, for different sub-pixels in each pixel unit, the width of the strip pixel electrode of the blue sub-pixel and / or the slit width between adjacent strip pixel electrodes can be designed accordingly to improve the transmittance of the sub-pixel as needed. For example, the width of the pixel electrode of the blue sub-pixel can be reduced and / or the slit width between adjacent pixel electrodes of the blue sub-pixel can be increased, so that the liquid crystal efficiency of the third sub-pixel is less than that of the first sub-pixel and the second sub-pixel. This solves the color shift phenomenon that usually occurs when the screen display is yellowish at a large viewing angle, increases the display quality of the display device containing the array substrate, and thus improves the display effect of the display device.

[0055] It is understood that the width of the strip pixel electrode and the slit width of the strip pixel electrode are important parameters that determine the transmittance of the display panel containing the array substrate. By changing the width of the strip pixel electrode and the slit width of the strip pixel electrode, the transmittance of the display panel can be changed. The following is an explanation using a specific embodiment.

[0056] Please see Figure 5 and Figure 6 , Figure 5 for Figure 4 The diagram shows a first structural schematic of the pixel electrodes for different sub-pixels within the pixel unit shown. Figure 6 for Figure 5 The diagram shows the dimensions of the pixel electrodes for different sub-pixels. In this embodiment, each pixel unit SP includes a first sub-pixel 32a, a second sub-pixel 32b, and a third sub-pixel 32c. The first sub-pixel 32a, the second sub-pixel 32b, and the third sub-pixel 32c can emit red light, green light, and blue light, respectively, enabling the pixel unit SP to display color. That is, the first sub-pixel 32a can be a red (R) sub-pixel, the second sub-pixel 32b can be a green (G) sub-pixel, and the third sub-pixel 32c can be a blue (B) sub-pixel; thus, each pixel unit SP can include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel.

[0057] In this embodiment, the first sub-pixel 32a includes a first pixel electrode unit 320, the second sub-pixel 32b includes a second pixel electrode unit 322, and the third sub-pixel 32c includes a third pixel electrode unit 324. The first pixel electrode unit 320 can be rectangular in shape, and can be divided into four first pixel electrode regions 3202 by two straight lines parallel to the midpoints of two sets of opposite sides. Each first pixel electrode unit 320 includes a plurality of first pixel electrodes 3204, which are located within the first pixel electrode regions 3202. Each first pixel electrode 3204 can be strip-shaped, and the plurality of first pixel electrodes 3204 located within the same first pixel electrode region 3202 are parallel and spaced apart.

[0058] In this embodiment, the second pixel electrode unit 322 can be rectangular in shape. It can be divided into four second pixel electrode regions 3222 by two straight lines parallel to the midpoints of its two opposite sides. The second pixel electrode unit 322 includes multiple second pixel electrodes 3224, each located within a second pixel electrode region 3222. Each second pixel electrode 3224 can be strip-shaped, and multiple second pixel electrodes 3224 within the same second pixel electrode region 3222 are parallel and spaced apart. The third pixel electrode unit 324 can also be rectangular in shape. It can be divided into four third pixel electrode regions 3242 by two straight lines parallel to the midpoints of its two opposite sides. The third pixel electrode unit 324 includes a plurality of third pixel electrodes 3244, which are respectively located in the third pixel electrode region 3242. The third pixel electrode 3244 can be strip-shaped. The plurality of third pixel electrodes 3244 located in the same third pixel electrode region 3242 are parallel and spaced apart.

[0059] It is understandable that by setting the overall shape of the first pixel electrode 3204, the second pixel electrode 3224, and the third pixel electrode 3244 to a strip shape, the edge field effect can be increased.

[0060] Since each pixel electrode is strip-shaped, each pixel electrode within the three pixel electrode units has a certain electrode width, which is represented by W in this embodiment. Because the pixel electrodes within the pixel electrode area of ​​the pixel electrode unit are arranged in parallel intervals, there is a certain slit width between two adjacent pixel electrodes within the same pixel electrode area, which is represented by L in this embodiment.

[0061] like Figure 6 As shown in the embodiment of this application, the width of the first pixel electrode 3204 in the first pixel electrode unit 320 is W1, and the slit width between two adjacent first pixel electrodes 3204 located in the same first pixel electrode region 3202 is L1; the width of the second pixel electrode 3224 in the second pixel electrode unit 322 is W2, and the slit width between two adjacent second pixel electrodes 3224 located in the same second pixel electrode region 3222 is L2; ​​the width of the third pixel electrode 3244 in the third pixel electrode unit 324 is W3, and the slit width between two adjacent third pixel electrodes 3244 located in the same third pixel electrode region 3242 is L3.

[0062] In the embodiments of the present application, the dimensional parameter of the first pixel electrode 3204 is consistent with the dimensional parameter of the second pixel electrode 3224, that is, the dimensional parameter of the pixel electrode of the red (R) sub-pixel is consistent with the dimensional parameter of the pixel electrode of the green (G) sub-pixel. That is, the width W1 of the first pixel electrode 3204 is equal to the width W2 of the second pixel electrode 3224, and the slit width L1 between two adjacent first pixel electrodes 3204 is equal to the slit width L2 between two adjacent second pixel electrodes 3224. That is, W1+L1=W2+L2.

[0063] In the embodiments of the present application, the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between adjacent third pixel electrodes 3244 is greater than the sum of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the slit width L1 between adjacent first pixel electrodes 3204, and the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is equal to the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320. Correspondingly, the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between adjacent third pixel electrodes 3244 is greater than the sum of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 and the slit width L2 between adjacent second pixel electrodes 3224, and the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is equal to the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322.

[0064] In a specific embodiment of the present application, the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is equal to the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and equal to the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322, the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 is equal to the slit width L1 between the first pixel electrodes 3204, and the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 is equal to the slit width L2 between the second pixel electrodes 3224. That is, W1=L1=W2=L2=W3<L3. Therefore, in the third pixel electrode unit 324, the ratio of the width W3 of the strip-shaped blue (B) sub-pixel to the slit width L3 between two adjacent strip-shaped blue (B) sub-pixels is less than 1, that is, the blue (B) sub-pixel has a smaller width and a larger slit width, which can further improve the transmittance.

[0065] In this embodiment, the sum of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the slit width L1 between the first pixel electrode 3204 can be 5 μm, and the sum of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 and the slit width L2 between the second pixel electrode 3224 can be 5 μm. The width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 can both be 2.5 μm, and the slit width L1 between the first pixel electrodes 3204 and the slit width L2 between the second pixel electrodes 3224 can both be 2.5 μm. That is, W1=L1=W2=L2=W3=2.5um, which means that the ratio W1 of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 to the slit width L1 between adjacent first pixel electrodes 3204 is equal to 1, and the ratio W2 of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 to the slit width L2 between adjacent second pixel electrodes 3224 is equal to 1.

[0066] In this embodiment, the sum of the width W3 of the third pixel electrode 3244 within the third pixel electrode unit 324 and the slit width L3 between the third pixel electrodes 3244 can be greater than 5 μm and less than or equal to 6.5 μm, for example, 5.2 μm, 5.5 μm, 5.8 μm, 6 μm, 6.3 μm, 6.5 μm, or other values. This application does not impose specific limitations on this. Correspondingly, the ratio W3 / L3 of the width W3 of the third pixel electrode 3244 within the third pixel electrode unit 324 to the slit width L3 between adjacent third pixel electrodes 3244 can be 2.5 μm / 2.7 μm, 2.5 μm / 3 μm, 2.5 μm / 3.3 μm, 2.5 μm / 3.5 μm, 2.5 μm / 3.8 μm, or 2.5 μm / 4 μm.

[0067] In another embodiment of this application, the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between adjacent third pixel electrodes 3244 is greater than the sum of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the slit width L1 between adjacent first pixel electrodes 3204, and the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is less than the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320. Correspondingly, the sum of the width W3 of the third pixel electrode 3244 within the third pixel electrode unit 324 and the slit width L3 between adjacent third pixel electrodes 3244 is greater than the sum of the width W2 of the second pixel electrode 3224 within the second pixel electrode unit 322 and the slit width L2 between adjacent second pixel electrodes 3224, and the width W3 of the third pixel electrode 3244 within the third pixel electrode unit 324 is less than the width W2 of the second pixel electrode 3224 within the second pixel electrode unit 322. That is, W1=L1=W2=L2>W3, and W3 <L3。

[0068] For example, the sum of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the slit width L1 between the first pixel electrode 3204, and the sum of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 and the slit width L2 between the second pixel electrode 3224, is 5 μm. The sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between the third pixel electrode 3244 is 6 μm. The width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 are both 2.5 μm, and the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is 2 μm. That is, the ratio W1 of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 to the slit width L1 between adjacent first pixel electrodes 3204 is equal to 1, the ratio W2 of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 to the slit width L2 between adjacent second pixel electrodes 3224 is equal to 1, and the ratio W3 of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 to the slit width L3 between adjacent third pixel electrodes 3244 is less than 1.

[0069] In another embodiment of this application, the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between adjacent third pixel electrodes 3244 is greater than the sum of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the slit width L1 between adjacent first pixel electrodes 3204, i.e., (W3+L3)>(W1+L1). The width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 is greater than half the sum of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the slit width L1 between the first pixel electrodes 3204. The width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is less than half the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between the third pixel electrodes 3244, and is less than the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320. Correspondingly, the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between adjacent third pixel electrodes 3244 is greater than the sum of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 and the slit width L2 between adjacent second pixel electrodes 3224, i.e., (W3+L3)>(W2+L2). The width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 is greater than half the sum of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 and the slit width L2 between the second pixel electrodes 3224. The width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is less than half the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between the third pixel electrodes 3244, and is less than the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322.

[0070] For example, the sum of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the slit width L1 between the first pixel electrode 3204, and the sum of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 and the slit width L2 between the second pixel electrode 3224, are both 5 μm. The sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between the third pixel electrode 3244, is 6 μm. The width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 are both 2.8 μm, and the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is 2.5 μm. That is, the ratio W1 / L1 of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 to the slit width L1 between adjacent first pixel electrodes 3204 is greater than 1; the ratio W2 / L2 of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 to the slit width L2 between adjacent second pixel electrodes 3224 is greater than 1; and the ratio W3 / L3 of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 to the slit width L3 between adjacent third pixel electrodes 3244 is less than 1.

[0071] In another embodiment of this application, the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between the third pixel electrode 3244 is greater than the sum of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the slit width L1 between the first pixel electrode 3204, i.e., (W3+L3)>(W1+L1). The width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 is less than half the sum of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the slit width L1 between the first pixel electrode 3204. Furthermore, the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is less than the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320. Correspondingly, the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between the third pixel electrode 3244 is greater than the sum of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 and the slit width L2 between the second pixel electrode 3224, i.e., (W3+L3)>(W2+L2). The width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 is less than half the sum of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 and the slit width L2 between the second pixel electrode 3224. Furthermore, the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is less than the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322.

[0072] For example, the sum of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the slit width L1 between the first pixel electrode 3204, and the sum of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 and the slit width L2 between the second pixel electrode 3224, is 5 μm. The sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between the third pixel electrode 3244, is 6 μm. The width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 are both 2.4 μm, and the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is 2.3 μm. That is, the ratio W1 / L1 of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 to the slit width L1 between adjacent first pixel electrodes 3204 is less than 1; the ratio W2 / L2 of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 to the slit width L2 between adjacent second pixel electrodes 3224 is less than 1; and the ratio W3 / L3 of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 to the slit width L3 between adjacent third pixel electrodes 3244 is less than 1, and less than the ratio W1 / L1 or the ratio W2 / L2.

[0073] Please see Figure 7 and Figure 8 , Figure 7 for Figure 4 The diagram shows a second structure of pixel electrodes for different sub-pixels within a pixel unit. Figure 8 for Figure 7 The diagram shows the dimensions of the pixel electrodes for different sub-pixels. Figure 7 and Figure 8 The structure and size of the pixel electrodes of different sub-pixels shown are similar to Figure 5 and Figure 6 The main differences in the structure and size of the pixel electrodes of the different sub-pixels shown are as follows: the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between the adjacent third pixel electrode 3244 is equal to the sum of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the slit width L1 between the adjacent first pixel electrode 3204; the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between the adjacent third pixel electrode 3244 is equal to the sum of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 and the slit width L2 between the adjacent second pixel electrode 3224. Figure 7 and Figure 8 The structure and size of the pixel electrodes of different sub-pixels shown are similar to Figure 5 and Figure 6 For a description of the similarities in structure and size of the pixel electrodes of the different sub-pixels shown, please refer to the above. Figure 5 and Figure 6 The relevant descriptions will not be repeated here.

[0074] In this embodiment, each pixel unit SP includes a first sub-pixel 32a, a second sub-pixel 32b, and a third sub-pixel 32c. The first sub-pixel 32a, the second sub-pixel 32b, and the third sub-pixel 32c can emit red light, green light, and blue light, respectively, enabling the pixel unit SP to display color. That is, the first sub-pixel 32a can be a red (R) sub-pixel, the second sub-pixel 32b can be a green (G) sub-pixel, and the third sub-pixel 32c can be a blue (B) sub-pixel. Each pixel unit SP includes a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. The first sub-pixel 32a includes a first pixel electrode unit 320, the second sub-pixel 32b includes a second pixel electrode unit 322, and the third sub-pixel 32c includes a third pixel electrode unit 324.

[0075] In this embodiment, the first pixel electrode unit 320 can be rectangular in shape. It can be divided into four first pixel electrode regions 3202 by two straight lines parallel to the midpoints of its two opposite sides. The first pixel electrode unit 320 includes a plurality of first pixel electrodes 3204, which can be strip-shaped. Multiple first pixel electrodes 3204 located within the same first pixel electrode region 3202 are parallel and spaced apart. The second pixel electrode unit 322 can be rectangular in shape. It can be divided into four second pixel electrode regions 3222 by two straight lines parallel to the midpoints of its two opposite sides. The second pixel electrode unit 322 includes a plurality of second pixel electrodes 3224, which can be strip-shaped. Multiple second pixel electrodes 3224 located within the same second pixel electrode region 3222 are parallel and spaced apart. The third pixel electrode unit 324 can be rectangular in shape. It can be divided into four third pixel electrode regions 3242 by two straight lines parallel to the midpoints of two sets of opposite sides. The third pixel electrode unit 324 includes multiple third pixel electrodes 3244, which can be strip-shaped. Multiple third pixel electrodes 3244 located within the same third pixel electrode region 3242 are parallel and spaced apart.

[0076] It is understandable that by setting the overall shape of the first pixel electrode 3204, the second pixel electrode 3224, and the third pixel electrode 3244 to a strip shape, the edge field effect can be increased.

[0077] like Figure 8 As shown in the embodiment of this application, the width of the first pixel electrode 3204 in the first pixel electrode unit 320 is W1, and the slit width between two adjacent first pixel electrodes 3204 located in the same first pixel electrode region 3202 is L1; the width of the second pixel electrode 3224 in the second pixel electrode unit 322 is W2, and the slit width between two adjacent second pixel electrodes 3224 located in the same second pixel electrode region 3222 is L2; ​​the width of the third pixel electrode 3244 in the third pixel electrode unit 324 is W3, and the slit width between two adjacent third pixel electrodes 3244 located in the same third pixel electrode region 3242 is L3.

[0078] In this embodiment, the size parameters of the first pixel electrode 3204 are consistent with those of the second pixel electrode 3224, that is, the size parameters of the pixel electrode of the red (R) sub-pixel are consistent with those of the pixel electrode of the green (G) sub-pixel. Specifically, the width W1 of the first pixel electrode 3204 is equal to the width W2 of the second pixel electrode 3224, and the slit width L1 between two adjacent first pixel electrodes 3204 is equal to the slit width L2 between two adjacent second pixel electrodes 3224. In other words, W1 + L1 = W2 + L2.

[0079] In the embodiments of the present application, the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between adjacent third pixel electrodes 3244 is equal to the sum of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the slit width L1 between adjacent first pixel electrodes 3204, and the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is smaller than the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320, that is, (W3+L3)=(W1+L1), and W3<W1. Correspondingly, the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between adjacent third pixel electrodes 3244 is equal to the sum of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 and the slit width L2 between adjacent second pixel electrodes 3224, and the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is smaller than the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322. That is, (W3+L3)=(W2+L2), and W3<W2.

[0080] In a specific embodiment of the present application, the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is smaller than the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and smaller than the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322, the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 is equal to the slit width L1 between the first pixel electrodes 3204, and the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 is equal to the slit width L2 between the second pixel electrodes 3224, that is, the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 is equal to half of the sum of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the slit width L1 between the first pixel electrodes 3204, the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 is equal to half of the sum of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 and the slit width L2 between the second pixel electrodes 3224, and the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is smaller than half of the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between the adjacent third pixel electrodes 3244. That is, W1=L1=W2=L2>W3, and W3<L3. Alternatively described, the ratio W1 / L1 of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 to the slit width L1 between the adjacent first pixel electrodes 3204 is equal to 1, the ratio W2 / L2 of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 to the slit width L2 between the adjacent second pixel electrodes 3224 is equal to 1, and the ratio W3 / L3 of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 to the slit width L3 between the adjacent third pixel electrodes 3244 is less than 1. Therefore, in the third pixel electrode unit 324, the ratio of the width W3 of the strip-shaped blue (B) sub-pixel to the slit width L3 between two adjacent strip-shaped blue (B) sub-pixels is less than 1, that is, the width of the blue (B) sub-pixel is smaller and the slit width thereof is larger, so that the transmittance can be further improved.

[0081] In a specific embodiment of this application, the sum of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the slit width L1 between the first pixel electrode 3204 can be 5 μm; the sum of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 and the slit width L2 between the second pixel electrode 3224 can be 5 μm; and the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between the third pixel electrode 3244 can be 5 μm. The width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 can both be 2.5 μm, and the slit width L1 between the first pixel electrodes 3204 and the slit width L2 between the second pixel electrodes 3224 can both be 2.5 μm. That is, the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 is equal to half the sum of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the slit width L1 between the first pixel electrodes 3204, and the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 is equal to half the sum of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 and the slit width L2 between the second pixel electrodes 3224, i.e., W1=L1=W2=L2=2.5um. Therefore, the ratio W1 / L1 of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 to the slit width L1 between adjacent first pixel electrodes 3204 is equal to 1, and the ratio W2 / L2 of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 to the slit width L2 between adjacent second pixel electrodes 3224 is equal to 1.

[0082] In this embodiment, the width W3 of the third pixel electrode 3244 within the third pixel electrode unit 324 can be greater than or equal to 1.8 μm and less than 2.5 μm, for example, 1.8 μm, 2 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, or other values. This application does not impose specific limitations on this. Correspondingly, the ratio W3 / L3 of the width W3 of the third pixel electrode 3244 within the third pixel electrode unit 324 to the slit width L3 between adjacent third pixel electrodes 3244 can be 1.8 μm / 3.2 μm, 2 μm / 3 μm, 2.1 μm / 2.9 μm, 2.2 μm / 2.8 μm, 2.3 μm / 2.7 μm, or 2.4 μm / 2.6 μm. That is, the ratio W3 / L3 of the width W3 of the third pixel electrode 3244 within the third pixel electrode unit 324 to the slit width L3 between adjacent third pixel electrodes 3244 is less than 1.

[0083] In another embodiment of this application, the sum of the width W3 of the third pixel electrode 3244 within the third pixel electrode unit 324 and the slit width L3 between adjacent third pixel electrodes 3244 is equal to the sum of the width W1 of the first pixel electrode 3204 within the first pixel electrode unit 320 and the slit width L1 between adjacent first pixel electrodes 3204. The width W1 of the first pixel electrode 3204 within the first pixel electrode unit 320 is greater than the width of the first pixel electrode 3204 within the first pixel electrode unit 320. The width W1 of electrode 3204 is half the sum of the slit width L1 between the first pixel electrode 3204 and the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324. The width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is less than half the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between the adjacent third pixel electrode 3244. That is, (W3+L3)=(W1+L1), W1>(W1+L1) / 2, and W3<(W3+L3) / 2. Accordingly, the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between adjacent third pixel electrodes 3244 is equal to the sum of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 and the slit width L2 between adjacent second pixel electrodes 3224. The width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 is greater than half the sum of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 and the slit width L2 between the second pixel electrodes 3224. The width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is less than half the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between adjacent third pixel electrodes 3244. That is, (W3+L3)=(W2+L2), W2>(W2+L2) / 2, and W3<(W3+L3) / 2.

[0084] For example, the sum of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the slit width L1 between the first pixel electrode 3204 can be 5µm; the sum of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 and the slit width L2 between the second pixel electrode 3224 can be 5µm; and the sum of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 and the slit width L3 between the third pixel electrode 3244 can be 5µm. The width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 and the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 are both 2.8µm, i.e., W1 > (W1 + L1) / 2 and W2 > (W2 + L2) / 2; the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 is 2.3µm, i.e., W3 < (W3 + L3) / 2. That is, the ratio W1 / L1 of the width W1 of the first pixel electrode 3204 in the first pixel electrode unit 320 to the slit width L1 between adjacent first pixel electrodes 3204 is greater than 1; the ratio W2 / L2 of the width W2 of the second pixel electrode 3224 in the second pixel electrode unit 322 to the slit width L2 between adjacent second pixel electrodes 3224 is greater than 1; and the ratio W3 / L3 of the width W3 of the third pixel electrode 3244 in the third pixel electrode unit 324 to the slit width L3 between adjacent third pixel electrodes 3244 is less than 1.

[0085] In this embodiment, the width W1 of the first pixel electrode 3204 within the first pixel electrode unit 320 can be greater than or equal to 2.5 μm and less than or equal to 3.2 μm, for example, 2.5 μm, 2.6 μm, 2.8 μm, 2.9 μm, 3 μm, 3.1 μm, 3.2 μm, or other values. This application does not impose specific limitations on this. The width W2 of the second pixel electrode 3224 within the second pixel electrode unit 322 can be greater than or equal to 2.5 μm and less than or equal to 3.2 μm, for example, 2.5 μm, 2.6 μm, 2.8 μm, 2.9 μm, 3 μm, 3.1 μm, 3.2 μm, or other values. This application does not impose specific limitations on this.

[0086] In this embodiment, the pixel unit SP may further include a common electrode (not shown). The pixel electrode and the common electrode constitute the liquid crystal capacitor of the pixel unit SP, that is, the pixel electrode is the first terminal of the liquid crystal capacitor, and the common electrode is the second terminal of the liquid crystal capacitor. The pixel unit SP may further include an array substrate common electrode, which is disposed around the periphery of the pixel electrode. The pixel electrode and the array substrate common electrode constitute the storage capacitor of the pixel unit SP, that is, the pixel electrode is the first terminal of the storage capacitor, and the array substrate common electrode is the second terminal of the storage capacitor.

[0087] In summary, the display device provided in this application includes a backlight module and a display panel. The display panel is disposed on the light-emitting side of the backlight module, and the backlight module is used to emit backlight light to the display panel. The display panel includes a color filter substrate, a liquid crystal layer, and an array substrate. The array substrate and the color filter substrate are opposite to each other and spaced apart. The liquid crystal layer is disposed between the array substrate and the color filter substrate. The array substrate includes a plurality of pixel units. Each pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel includes a first pixel electrode unit, the second sub-pixel includes a second pixel electrode unit, and the third sub-pixel includes a third pixel electrode unit. Each of the first pixel electrode unit, the second pixel electrode unit, and the third pixel electrode unit includes a plurality of pixel electrodes. The third sub-pixel is a blue sub-pixel. The width of the pixel electrode in the third pixel electrode unit is less than or equal to the width of the pixel electrode in the first pixel electrode unit and less than or equal to the width of the pixel electrode in the second pixel electrode unit; and / or, the slit width of adjacent pixel electrodes in the third pixel electrode unit is greater than the slit width of adjacent pixel electrodes in the first pixel electrode unit and greater than the slit width of adjacent pixel electrodes in the second pixel electrode unit. Therefore, for different sub-pixels in each pixel unit, the width of the strip-shaped pixel electrode of the blue sub-pixel and / or the slit width between adjacent strip-shaped pixel electrodes can be designed accordingly to improve the transmittance of the sub-pixel as needed. For example, reducing the width of the pixel electrode of the blue sub-pixel and / or increasing the slit width between adjacent pixel electrodes of the blue sub-pixel can reduce the liquid crystal efficiency of the third sub-pixel, making the liquid crystal efficiency of the third sub-pixel lower than that of the first sub-pixel and lower than that of the second sub-pixel. This solves the color shift phenomenon of yellowish tint that commonly occurs in screen displays at large viewing angles, increases the display quality of the display panel and display device, and thus improves the display effect of the display device.

[0088] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0089] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims. Those skilled in the art will understand that implementing all or part of the processes of the above embodiments, and making equivalent changes according to the claims of this application, still falls within the scope of this application.

Claims

1. An array substrate comprising a plurality of pixel units, characterized in that, Each pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel includes a first pixel electrode unit, the second sub-pixel includes a second pixel electrode unit, and the third sub-pixel includes a third pixel electrode unit. The first pixel electrode unit, the second pixel electrode unit, and the third pixel electrode unit each include multiple pixel electrodes. The third sub-pixel is a blue sub-pixel. The width of the pixel electrode in the third pixel electrode unit is less than or equal to the width of the pixel electrode in the first pixel electrode unit and less than or equal to the width of the pixel electrode in the second pixel electrode unit; and / or, The slit width between adjacent pixel electrodes in the third pixel electrode unit is greater than the slit width between adjacent pixel electrodes in the first pixel electrode unit and greater than the slit width between adjacent pixel electrodes in the second pixel electrode unit.

2. The array substrate as described in claim 1, characterized in that, The first pixel electrode unit includes four first pixel electrode regions and multiple first pixel electrodes. The multiple first pixel electrodes are respectively located in the first pixel electrode regions. The multiple first pixel electrodes located in the same first pixel electrode region are parallel and spaced apart. The second pixel electrode unit includes four second pixel electrode regions and multiple second pixel electrodes. The multiple second pixel electrodes are respectively located in the second pixel electrode regions. The multiple second pixel electrodes located in the same second pixel electrode region are parallel and spaced apart. The third pixel electrode unit includes four third pixel electrode regions and multiple third pixel electrodes. The multiple third pixel electrodes are respectively located in the third pixel electrode regions, and the multiple third pixel electrodes located in the same third pixel electrode region are arranged in parallel and at intervals.

3. The array substrate as described in claim 2, characterized in that, The sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between adjacent third pixel electrodes is greater than the sum of the width of the first pixel electrode in the first pixel electrode unit and the slit width between adjacent first pixel electrodes, and the width of the third pixel electrode in the third pixel electrode unit is equal to the width of the first pixel electrode in the first pixel electrode unit. The sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between the adjacent third pixel electrodes is greater than the sum of the width of the second pixel electrode in the second pixel electrode unit and the slit width between the adjacent second pixel electrodes, and the width of the third pixel electrode in the third pixel electrode unit is equal to the width of the second pixel electrode in the second pixel electrode unit. The width of the first pixel electrode in the first pixel electrode unit is equal to the width of the slit between the first pixel electrodes, and the width of the second pixel electrode in the second pixel electrode unit is equal to the width of the slit between the second pixel electrodes.

4. The array substrate as described in claim 2, characterized in that, The sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between adjacent third pixel electrodes is greater than the sum of the width of the first pixel electrode in the first pixel electrode unit and the slit width between adjacent first pixel electrodes, and the width of the third pixel electrode in the third pixel electrode unit is less than the width of the first pixel electrode in the first pixel electrode unit. The sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between adjacent third pixel electrodes is greater than the sum of the width of the second pixel electrode in the second pixel electrode unit and the slit width between adjacent second pixel electrodes, and the width of the third pixel electrode in the third pixel electrode unit is less than the width of the second pixel electrode in the second pixel electrode unit.

5. The array substrate as described in claim 2, characterized in that, The sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between adjacent third pixel electrodes is greater than the sum of the width of the first pixel electrode in the first pixel electrode unit and the slit width between adjacent first pixel electrodes. The width of the first pixel electrode in the first pixel electrode unit is greater than half the sum of the width of the first pixel electrode in the first pixel electrode unit and the slit width between the first pixel electrodes. The width of the third pixel electrode in the third pixel electrode unit is less than half the sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between the third pixel electrodes, and is less than the width of the first pixel electrode in the first pixel electrode unit. The sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between adjacent third pixel electrodes is greater than the sum of the width of the second pixel electrode in the second pixel electrode unit and the slit width between adjacent second pixel electrodes. The width of the second pixel electrode in the second pixel electrode unit is greater than half the sum of the width of the second pixel electrode in the second pixel electrode unit and the slit width between the second pixel electrodes. The width of the third pixel electrode in the third pixel electrode unit is less than half the sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between the third pixel electrodes, and is less than the width of the second pixel electrode in the second pixel electrode unit.

6. The array substrate as described in claim 2, characterized in that, The sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between the third pixel electrode is greater than the sum of the width of the first pixel electrode in the first pixel electrode unit and the slit width between the first pixel electrodes. The width of the first pixel electrode in the first pixel electrode unit is less than half the sum of the width of the first pixel electrode in the first pixel electrode unit and the slit width between the first pixel electrodes. The width of the third pixel electrode in the third pixel electrode unit is less than the width of the first pixel electrode in the first pixel electrode unit. The sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between the third pixel electrode is greater than the sum of the width of the second pixel electrode in the second pixel electrode unit and the slit width between the second pixel electrode. The width of the second pixel electrode in the second pixel electrode unit is less than half the sum of the width of the second pixel electrode in the second pixel electrode unit and the slit width between the second pixel electrode. The width of the third pixel electrode in the third pixel electrode unit is less than the width of the second pixel electrode in the second pixel electrode unit.

7. The array substrate as described in claim 2, characterized in that, The sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between adjacent third pixel electrodes is equal to the sum of the width of the first pixel electrode in the first pixel electrode unit and the slit width between adjacent first pixel electrodes. The width of the first pixel electrode in the first pixel electrode unit is greater than or equal to half the sum of the width of the first pixel electrode in the first pixel electrode unit and the slit width between the first pixel electrodes. The width of the third pixel electrode in the third pixel electrode unit is less than half the sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between adjacent third pixel electrodes. The sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between adjacent third pixel electrodes is equal to the sum of the width of the second pixel electrode in the second pixel electrode unit and the slit width between adjacent second pixel electrodes. The width of the second pixel electrode in the second pixel electrode unit is greater than or equal to half the sum of the width of the second pixel electrode in the second pixel electrode unit and the slit width between the second pixel electrodes. The width of the third pixel electrode in the third pixel electrode unit is less than half the sum of the width of the third pixel electrode in the third pixel electrode unit and the slit width between adjacent third pixel electrodes.

8. The array substrate according to any one of claims 2 to 7, characterized in that, The ratio of the width of the third pixel electrode within the same third pixel electrode region of the third pixel electrode unit to the slit width between adjacent third pixel electrodes is less than 1.

9. A display panel, characterized in that, The invention includes a color filter substrate, a liquid crystal layer, and an array substrate as described in any one of claims 1-8, wherein the array substrate is disposed opposite to and spaced apart from the color filter substrate, and the liquid crystal layer is disposed between the array substrate and the color filter substrate.

10. A display device, characterized in that, It includes a backlight module and a display panel as described in claim 9, wherein the display panel is disposed on the light-emitting side of the backlight module, and the backlight module is used to emit backlight light to the display panel.

Images