Control system of peripheral device and chip testing machine

Abstract

The present disclosure provides a peripheral device control system and a chip testing machine, by setting an IO expansion module, the controller is connected with various peripheral devices in the test voltage control circuit and the chip driving circuit through the IO expansion module, the conduction state of the analog switch array is controlled through the first IO expansion unit, and / or the output voltage value of the power supply chip and the switch state of the selection switch are controlled through the second IO expansion unit, and / or the third IO expansion unit is connected with the alarm unit in the chip driving circuit, the corresponding alarm signal of the power supply chip is received, a plurality of peripheral devices can be controlled by using a small amount of IO pins, more control signals are provided for the peripheral devices under the condition that the IO resources of the controller are limited, the functions of adjusting and checking the test voltage and the driving voltage are realized, a structure for saving the IO resources of the controller and improving the IO resource utilization rate is provided, and the chip testing cost can be effectively reduced.

Description

Technical Field

[0001] This disclosure relates to automated testing technology, and in particular to a control system for peripheral devices and a chip testing machine. Background Technology

[0002] During chip testing, different input / output (IO) channels of the chip under test require different voltage values. The test machine needs to provide different input voltages to the chip under test. At the same time, in order to ensure the stable operation of the test machine, it is also necessary to verify the various test parameters in the test board and control the relays.

[0003] In traditional test board circuit design, peripheral devices such as relays, analog-to-digital converter (ADC) chips, and digital-to-analog converter (DAC) chips, which implement the above functions, are all controlled by a controller. For example, the input voltage of the chip under test is usually generated by a DAC chip, which then connects to a processing element (PE) chip via an analog switch. The controller chip and analog switch are both connected to and controlled by the controller to achieve the output of test voltages on different I / O pins. While this design ensures precise control of peripheral devices and improves their response speed, it consumes a large amount of I / O resources from the controller. With the development of test equipment, the complexity of test board functions on the test equipment has increased, and the number of chips that the test equipment needs to test in parallel is also increasing. Therefore, controllers with higher I / O resource requirements are needed, resulting in higher chip testing costs. Utility Model Content

[0004] This disclosure provides a control system for peripheral devices and a chip testing machine, which can save controller I / O resources, improve the utilization rate of controller I / O resources, reduce the complexity of chip testing circuits, and reduce chip testing costs.

[0005] In one aspect of this disclosure, a control system for a peripheral device is provided, including a controller, a communication bus, and an I / O expansion module, wherein the I / O expansion module is communicatively connected to the controller via the communication bus. The IO expansion module is provided with at least one of a first IO expansion unit, a second IO expansion unit, and a third IO expansion unit; The controller is connected to the analog switch array in the test voltage control circuit through the first IO expansion unit, and is used to control the conduction state of the analog switch array through the first IO expansion unit. The correspondence between each pin of the chip under test and the test voltage is different in different conduction states of the analog switch array. The controller is also connected to the power chip and the selection switch in the chip driver circuit through the second IO expansion unit, and is used to control the output voltage value of the power chip and the switching state of the selection switch through the second IO expansion unit. The switching state of the selection switch is used to control the cascading mode of the power chip and the voltage calibration path. Finally, the controller is connected to the alarm unit in the chip driver circuit through the third IO expansion unit, and is used to receive the alarm signal corresponding to the power chip through the alarm unit.

[0006] Optionally, the IO expansion module is provided with the first IO expansion unit, the first IO expansion unit includes a first IO expander, the communication bus includes a first communication bus, the first IO expander is connected to the controller through the first communication bus, and the test voltage control circuit includes the analog switch array and at least one processing unit chip; The control terminal of the analog switch array is connected to the extended IO pin of the first IO expander, and the output terminal of the analog switch array is connected to the input terminal of the at least one processing unit chip. The output terminals of at least one processing unit chip are respectively connected to the pins of the corresponding chip under test, and are used to output the test voltage to the pins of the corresponding chip under test based on the test voltage reference signal received through the analog switch array.

[0007] Optionally, the test voltage control circuit further includes a first digital-to-analog converter; The input terminal of the first digital-to-analog converter is connected to the controller, and the output terminal of the first digital-to-analog converter is connected to the voltage input terminal of the analog switch array, for outputting at least one test voltage reference signal to the analog switch array based on the first control signal of the controller.

[0008] Optionally, the IO expansion module is provided with a second IO expansion unit, the second IO expansion unit includes a communication bus expander, the communication bus includes a second communication bus, and the second IO expansion unit is connected to the controller through the second communication bus; At least one extended communication pin of the communication bus extender is connected to the control pin of at least one power chip via a corresponding third communication bus, for configuring the output voltage value of the at least one power chip based on the second control signal of the controller. The third communication bus has the same communication protocol as the second communication bus.

[0009] Optionally, the second IO expansion unit further includes a second IO expander, the communication bus includes a fourth communication bus, the second IO expander is connected to the controller through the fourth communication bus, and the chip driving circuit includes at least one first selection switch and at least one second selection switch; At least one extended IO pin of the second IO expander is connected to the control terminal of the at least one first selection switch and the control terminal of the at least one second selection switch, respectively, for controlling the conduction state of the at least one first selection switch based on the third control signal of the controller, and controlling the conduction state of the at least one second selection switch based on the fourth control signal of the controller. The cascading mode of the at least one power chip is different under different conduction states of the first selection switch, and the calibration path corresponding to the at least one power chip is different under different conduction states of the second selection switch.

[0010] Optionally, the IO expansion module includes a third IO expansion unit, the third IO expansion unit includes a third IO expander, the communication bus includes a fifth communication bus, the third IO expander is connected to the controller through the fifth communication bus, and the alarm unit includes a comparator array and a second digital-to-analog converter; The input terminal of the second digital-to-analog converter is connected to the controller, and at least one output terminal of the second digital-to-analog converter is connected to the first input terminal of at least one comparator in the comparator array, for outputting an alarm threshold to the comparator array based on the fifth control signal of the controller. The alarm threshold includes at least one of an overvoltage alarm threshold, an undervoltage alarm threshold, an overcurrent alarm threshold, and an open circuit alarm threshold. The second input terminal of the at least one comparator is connected to the output pin of the power chip, and the at least one comparator is used to output an alarm signal when the magnitude relationship between the input signal at the first input terminal and the input signal at the second input terminal meets a preset alarm condition. At least one extended IO pin of the third IO expander is connected to the output of at least one comparator in the comparator array, for transmitting the alarm signal output by the comparator array to the controller.

[0011] Optionally, the third IO expansion unit further includes a fourth IO expander, and the communication bus includes a sixth communication bus, through which the fourth IO expander is connected to the controller; At least one extended IO pin of the fourth IO expander is connected to the corresponding hardware alarm pin of the power chip to collect the over-temperature alarm signal of the power chip.

[0012] In another aspect of this disclosure, a chip testing machine is provided, which is equipped with a control system for peripheral devices as described above.

[0013] Based on the embodiments of this disclosure, by setting up an IO expansion module, the controller can be connected to various peripheral devices in the test voltage control circuit and the chip driver circuit through the IO expansion module. The first IO expansion unit controls the conduction state of the analog switch array, and / or the second IO expansion unit controls the output voltage value of the power chip and the switching state of the selector switch, and / or the third IO expansion unit connects to the alarm unit in the chip driver circuit to receive the alarm signal corresponding to the power chip. Only a few IO pins are needed to control multiple peripheral devices. Under the condition of limited controller IO resources, more control signals are provided to peripheral devices to realize functions such as adjustment and verification of test voltage and drive voltage. This provides a structure that saves controller IO resources and improves the utilization rate of controller IO resources. It solves the problem of excessive use of controller IO resources by peripheral devices on traditional test machines. It can effectively reduce the number of controllers required for chip testing, thereby reducing the complexity of chip test circuits and chip testing costs.

[0014] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0015] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0016] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein: Figure 1 A schematic diagram of the structure of a control system for a peripheral device provided as an exemplary embodiment of this disclosure; Figure 2 A schematic diagram of the structure of a control system for a peripheral device provided as another exemplary embodiment of this disclosure; Figure 3 A flowchart of a controller controlling a test voltage control circuit provided as an exemplary embodiment of this disclosure; Figure 4 A schematic diagram of the structure of a test voltage control circuit provided in an exemplary embodiment of this disclosure; Figure 5 A schematic diagram of the structure of a control system for a peripheral device provided as another exemplary embodiment of this disclosure; Figure 6 A flowchart illustrating voltage configuration and calibration of a controller control chip driver circuit provided for an exemplary embodiment of this disclosure; Figure 7 A schematic diagram of the structure of a chip driver circuit provided in an exemplary embodiment of this disclosure; Figure 8 A schematic diagram of the structure of a control system for a peripheral device provided as another exemplary embodiment of this disclosure; Figure 9 A flowchart illustrating an exemplary embodiment of this disclosure, showing a controller controlling an alarm unit to generate an abnormal alarm. Figure 10 This is a schematic diagram of the structure of an alarm unit provided in an exemplary embodiment of the present disclosure.

[0017] The attached figures are labeled as follows: 101-Controller; 102-Communication bus; 103-IO expansion module; 201-Test voltage control circuit; 301-Third communication bus; 302-Power supply chip; 802-Alarm matrix keypad 1021 - First communication bus; 1022 - Second communication bus; 1023 - Fourth communication bus; 1024 - Fifth communication bus; 1031 - First I / O expansion unit; 1032 - Second I / O expansion unit; 1033 - Third I / O expansion unit; 2011 - Analog switch array; 2012 - PE chip; 8011 - Comparator array; 8012 - Second digital-to-analog converter; 1031a - First I / O expander; 1032a - Communication bus expander; 1032b - Second I / O expander; 1033a - Third I / O expander. Detailed Implementation

[0018] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0019] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0020] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0021] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0022] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0023] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0024] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0025] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0026] Technologies and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such technologies and equipment should be considered part of the specification.

[0027] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0028] Figure 1 This is a schematic diagram of the structure of a control system for a peripheral device provided as an exemplary embodiment of this disclosure. For example... Figure 1 As shown, the control system of the peripheral device includes a controller 101, a communication bus 102, and an IO expansion module 103. The IO expansion module 103 is connected to the controller 101 via the communication bus 102.

[0029] The IO expansion module 103 includes at least one of a first IO expansion unit 1031, a second IO expansion unit 1032, and a third IO expansion unit 1033. Illustratively, each expansion unit in the controller 101 can be a single control chip or composed of multiple control chips. Each expansion unit can be, for example, at least one chip including, but not limited to, a Field Programmable Gate Array (FPGA), a Microcontroller Unit (MCU), or a Digital Signal Processing (DSP) chip. The communication bus 102 uses a communication line corresponding to the communication protocol supported by the expansion units in the controller 101, such as an Inter-Integrated Circuit (IIC) bus or a Serial Peripheral Interface (SPI) bus. The first IO expansion unit 1031, the second IO expansion unit 1032, and the third IO expansion unit 1033 are respectively connected to their corresponding peripheral devices via the communication bus 102.

[0030] The controller 101 is connected to the analog switch array in the test voltage control circuit via the first IO expansion unit 1031. The controller 101 controls the conduction state of the analog switch array through the first IO expansion unit 1031. The correspondence between the pins of the chip under test and the test voltage differs depending on the conduction state of the analog switch array. The test voltage control circuit provides the test voltage to the chip under test. The same chip under test may have multiple pins requiring specific test voltage inputs, and the test machine may simultaneously test multiple chips under test. Therefore, the test voltage control circuit needs to synchronously output multiple test voltages and adjust the test voltage when switching test vectors. In traditional test machines, each switch of the test voltage control circuit is communicatively connected to the controller 101, switching the switch state based on the control signals of the controller 101, resulting in a large demand for the controller 101's IO resources. In this embodiment of the present disclosure, the controller 101 is connected to the analog switch array in the test voltage control circuit through the first IO expansion unit 1031. The first IO expansion unit 1031 may be, for example, at least one IO expansion chip. Each IO expansion chip can be connected to 8 switches and control 8 transmission channels of test voltage. The controller 101 only needs to control the IO expansion chip through 2 IO interfaces.

[0031] And / or, the controller 101 is connected to the power chip and the selection switch in the chip driver circuit through the second IO expansion unit 1032, and is used to control the output voltage value of the power chip and the switching state of the selection switch through the second IO expansion unit 1032. The switching state of the selection switch is used to control the cascading mode of the power chips and the voltage calibration path. The chip driver circuit is a circuit used to provide drive voltage and drive current to the chip under test. When a single power chip cannot meet the drive voltage or drive current requirements of the chip under test, multiple power chips need to be cascaded to provide the corresponding drive voltage and drive current. In the control system of the peripheral device of this embodiment, the controller 101 is connected to the power chip and the selection switch through the second IO expansion unit 1032, and the control of the cascading mode of multiple power chips can be achieved with a small amount of IO resources. In addition, in order to ensure that the operating voltage and operating current of the chip under test are stable and can meet the requirements, the switching state of the selection switch is also controlled through the second IO expansion unit 1032, so that the calibration module polls and verifies the output voltage of each drive circuit, thereby calibrating the drive voltage or drive current that does not meet the requirements of the chip under test.

[0032] And / or, the controller 101 is connected to the alarm unit in the chip driver circuit through the third IO expansion unit 1033, for receiving alarm signals corresponding to the power chip through the alarm unit. The alarm unit includes a comparator array, where each comparator receives an alarm threshold signal and a voltage or current signal from the chip driver circuit. When the relationship between the voltage or current signal and the alarm threshold signal meets the alarm condition, an alarm signal is output. The controller 101 is connected to the comparator array through the third IO expansion unit 1033, sending corresponding alarm threshold signals to each comparator and receiving the alarm signals output by each comparator, and feeding the alarm signals back to the controller 101. This allows the controller 101 to detect alarms in a large number of driver circuits using only a few IO pins.

[0033] Based on the embodiments of this disclosure, by setting up an IO expansion module, the controller can be connected to various peripheral devices in the test voltage control circuit and the chip driver circuit through the IO expansion module. The first IO expansion unit controls the conduction state of the analog switch array, and / or the second IO expansion unit controls the output voltage value of the power chip and the switching state of the selector switch, and / or the third IO expansion unit connects to the alarm unit in the chip driver circuit to receive the alarm signal corresponding to the power chip. Only a few IO pins are needed to control multiple peripheral devices. Under the condition of limited controller IO resources, more control signals are provided to peripheral devices to realize functions such as adjustment and verification of test voltage and drive voltage. This provides a structure that saves controller IO resources and improves the utilization rate of controller IO resources. It solves the problem of excessive use of controller IO resources by peripheral devices on traditional test machines. It can effectively reduce the number of controllers required for chip testing, thereby reducing the complexity of chip test circuits and chip testing costs.

[0034] In one possible implementation, such as Figure 2 As shown, the IO expansion module includes a first IO expansion unit 1031, which includes a first IO expander 1031a. The communication bus 102 includes a first communication bus 1021. The first IO expander 1031a is connected to the controller 101 via the first communication bus 1021. The test voltage control circuit 201 includes an analog switch array 2011 and at least one processing element (PE) chip 2012. The control terminal of the analog switch array 2011 is connected to the expansion IO pins of the first IO expander 1031a, and the output terminal of the analog switch array 2011 is connected to the input terminal of at least one PE chip 2012. The output terminals of at least one PE chip 2012 are respectively connected to the pins of the corresponding chip under test, for outputting a test voltage to the pins of the corresponding chip under test based on the test voltage reference signal received through the analog switch array 2011.

[0035] The analog switch array 2011 can be implemented using analog switch chips, such as CD4051, HCF4051, CH486F, and other multi-channel analog switch chips. Its control terminal is connected to the expansion I / O pins of the first I / O expander 1031a, which can be, for example, an I / O expansion chip such as PCF8574 or TCA9539. Before the test begins, the controller 101 determines the corresponding test voltage for each chip under test based on the test data and generates a sixth control signal. The first I / O expander receives the sixth control signal sent by the controller 101 through the first communication bus 1021 and controls the conduction state of each switch in the analog switch array 2011 based on this sixth control signal, so that each chip under test receives the correct test voltage.

[0036] In one possible implementation, the test voltage control circuit 201 further includes a first digital-to-analog converter (DAC). The input of the first DAC is connected to the controller 101, and the output of the first DAC is connected to the voltage input of the analog switch array 2011, for outputting at least one test voltage reference signal to the analog switch array 2011 based on a first control signal from the controller 101.

[0037] The controller 101 determines the test voltage corresponding to each chip under test based on the test data, and then determines the voltage value of each output voltage of the first analog-to-digital converter, which is used to provide a reference voltage. On the other hand, the controller 101 sends a first control signal to the analog switch array 2011 through the first IO expander 1031a, thereby controlling the conduction state of each switch in the analog switch array 2011 to connect the pins of each chip under test to the corresponding reference voltage path. The reference voltage is further processed by the PE chip after being output by the analog switch chip, converted into the actual test voltage required by the chip under test, and transmitted to the chip under test.

[0038] The control circuit flow of controller 101 for controlling the test voltage is as follows: Figure 3As shown: After power-on, step 301 is executed to determine whether the voltage needs to be modified, i.e., whether the reference voltage output by the first analog-to-digital converter needs to be modified according to the test requirements of the chip under test. If yes, proceed to step 302; otherwise, proceed to step 304. Step 302: Set the input reference voltage (i.e., reference voltage) of the chip under test. Step 303: Determine whether the reference voltage setting is complete. If yes, proceed to step 304; otherwise, continue with step 302. Step 304: Determine whether the IO configuration needs to be modified, i.e., whether the pins of the chip under test and the first analog-to-digital converter need to be modified. If the connection relationship between the converter output channels is true, proceed to step 305; otherwise, proceed to step 307. Step 305: Simulate the input control signal to the analog switch array through the IO expansion chip (i.e., the first IO expander). Step 306: Determine whether the IO configuration is complete. If yes, proceed to step 307; otherwise, continue to step 305. Step 307: Enable the operation. Step 308: Run the test data. Step 309: Run the test once. Step 310: Determine whether the operation is complete. If yes, end the program; otherwise, proceed to step 301.

[0039] Indicative, Figure 4 A schematic diagram of a first I / O expansion unit 1031 and a test voltage control circuit 201 is shown. The controller 101 uses an FPGA chip, which communicates with the DAC chip via an SPI bus and with the I / O expansion chip via an IIC bus. The output of the I / O expansion chip is connected to the control terminal of an analog switch chip. The DAC chip is connected to the corresponding PE chip through the analog switch chip, and the pins of the PE chip correspond one-to-one with the pins of the chip under test. The FPGA adjusts the reference voltage corresponding to each PE chip by adjusting the conduction state of the analog switch chip through the I / O expansion chip.

[0040] Based on the embodiments of this disclosure, by setting a first IO expander in the control system of the peripheral device, the first IO expander is connected to the control terminal of the analog switch array of the peripheral device in the test voltage control circuit, so that the controller can control the conduction state of the analog switch array through the first IO expander, and adjust the test voltage of a large number of chip pins under test through a small number of IO interfaces, thereby expanding the actual control quantity of the controller and improving resource utilization efficiency.

[0041] In one possible implementation, such as Figure 5As shown, the IO expansion module includes a second IO expansion unit 1032, which includes a communication bus expander 1032a. The communication bus includes a second communication bus 1022, and the second IO expansion unit 1032 is connected to the controller 101 via the second communication bus 1022. At least one extended communication pin of the communication bus expander 1032a is connected to the control pin of at least one power chip 302 in the chip driver circuit via a corresponding third communication bus 301, for configuring the output voltage value of at least one power chip 302 based on the second control signal of the controller 101. The communication protocol of the third communication bus 301 is consistent with that of the second communication bus 1022.

[0042] The communication bus extender 1032a can be an extender corresponding to the communication bus type supported by the controller 101. For example, if the controller 101 supports the IIC communication bus, the communication bus extender 1032a can be an IIC extension chip. Correspondingly, the power supply chip 302 in the chip driver circuit can be implemented using a Dynamic Power Supply (DSP) chip. The communication bus type supported by the power supply chip 302 is the same as that supported by the controller 101; therefore, the communication protocol of the third communication bus 301 and the second communication bus 1022 is consistent. For example, both the third communication bus 301 and the second communication bus 1022 are IIC communication buses. By setting the communication bus extender 1032a, the controller 101 can control a large number of power supply chips 302 through a small number of I / O ports and the IIC bus.

[0043] In one possible implementation, such as Figure 5 As shown. The second IO expansion unit 1032 also includes a second IO expander 1032b. The communication bus includes a fourth communication bus 1023. The second IO expander 1032b is connected to the controller 101 through the fourth communication bus 1023. The chip driving circuit includes at least one first selection switch 303 and at least one second selection switch 304. At least one expansion IO pin of the second IO expander 1032b is connected to the control terminal of at least one first selection switch 303 and the control terminal of at least one second selection switch 304, respectively, for controlling the conduction state of at least one first selection switch 303 based on the third control signal of the controller 101, and controlling the conduction state of at least one second selection switch 304 based on the fourth control signal of the controller 101. The cascading mode of at least one power chip 302 is different under different conduction states of the first selection switch 303, and the calibration path corresponding to at least one power chip 302 is different under different conduction states of the second selection switch 304.

[0044] The power chip 302 is connected to the chip under test (DUT) on the test board via a first selection switch 303. Cascading mode refers to electrically connecting the outputs of two or more power chips 302 of the same model in parallel, so that they collectively power a load to meet its power requirements. The controller 101 can determine the cascading mode of the power chip 302 based on its output voltage and current, as well as the actual power requirements of the DUT, and adjust the cascading mode by controlling the conduction state of the first selection switch 303 through the second I / O expander 1032b. The second I / O expander 1032b can be, for example, an I / O expansion chip such as PCF8574 or TCA9539.

[0045] During the power supply process of power chip 302, factors such as internal circuit losses and temperature changes may cause a deviation between the actual output voltage of power chip 302 and the target voltage. By setting up a calibration module and a second selection switch 304, the output lines of each power chip 302 are connected to the calibration module through the second selection switch 304. The controller 101 can control the conduction state of the second selection switch 304 through the second IO expander 1032b, so that the calibration module calibrates the output voltage of each power chip 302 in sequence.

[0046] The process by which controller 101 configures and calibrates the voltage of the chip driver circuit is as follows: Figure 6 As shown: After power-on, step 601 is executed through the communication module (i.e., the second IO expansion unit 1032) to open the selection switch and configure the DPS compensation circuit and cascade mode; step 602, it is determined whether the configuration is complete. If yes, step 603 is executed; otherwise, step 601 is continued; step 603, the DPS chip output is configured sequentially through the IIC expander; step 604, it is determined whether calibration is required. If yes, step 606 is executed; otherwise, step 605 is executed and the process ends; step 605, normal output; step 606, wait for the voltage output to stabilize; step 607, voltage calibration verification is performed; step 608, calibration value is fed back.

[0047] Indicative, Figure 7A schematic diagram of a second I / O expansion unit and a chip driving circuit is shown. The second I / O expansion unit includes an IIC expansion chip and an I / O expansion chip. The controller FPGA chip sends second control signals to multiple DPS chips through the IIC expansion chip to configure parameters or provide calibration value feedback for the output voltage values ​​of the multiple DPS chips. On the other hand, the FPGA chip is connected to each selection switch through at least one I / O expansion chip. Some selection switches are used to adjust the cascading state of the DPS chips, for example, cascading DPS chip VS0 and DPS chip VS1 so that their common output is VS0+VS1. Other selection switches are used to select the connection relationship between each DPS chip and the calibration module, so that the calibration module sequentially receives the feedback voltage values ​​of each channel and performs calibration.

[0048] Based on the embodiments of this disclosure, by setting a communication bus extender and a second IO extender, the controller can connect to multiple communication buses through a small number of IO ports to communicate with multiple power chips, and control the conduction state of the first selection switch and the second selection switch through a small number of IO ports, thereby realizing the functions of power chip cascade mode adjustment and power supply voltage calibration.

[0049] In one possible implementation, such as Figure 8 As shown, the IO expansion module includes a third IO expansion unit 1033, which includes a third IO expander 1033a. The communication bus 102 includes a fifth communication bus 1024. The third IO expander 1033a is connected to the controller 101 via the fifth communication bus 1024. The alarm unit includes a comparator array 8011 and a second digital-to-analog converter 8012. The third IO expander 1033a can be, for example, an IO expansion chip such as PCF8574 or TCA9539.

[0050] The input terminal of the second digital-to-analog converter 8012 is connected to the controller 101, and at least one output terminal of the second digital-to-analog converter 8012 is connected to the first input terminal of at least one comparator in the comparator array 8011, respectively, for outputting alarm thresholds to the comparator array 8011 based on the fifth control signal of the controller 101. The alarm thresholds include at least one of the following: over-voltage protection (OVP) alarm threshold, under-voltage protection (UVP) alarm threshold, over-current protection (OCP) alarm threshold, and over-current shutdown (OSD) alarm threshold.

[0051] At least one comparator has its second input connected to the output pin of the power supply chip 302. The comparator is used to output an alarm signal when the magnitude relationship between the input signal at the first input and the input signal at the second input meets a preset alarm condition. At least one extended I / O pin of the third I / O expander 1033a is connected to the output of at least one comparator in the comparator array 8011, and is used to transmit the alarm signal output by the comparator array 8011 to the controller 101.

[0052] Optionally, each comparator in the comparator array 8011 is used to output a corresponding type of alarm signal for the corresponding power supply chip. For example, the first input of the comparator is connected to the output of the second digital-to-analog converter 8012, receiving the OVP alarm threshold output by the second digital-to-analog converter 8012 based on the fifth control signal of the controller 101. The second input of the comparator is connected to the output pin of the power supply chip 302, receiving the output voltage of the power supply chip 302. When the voltage at the second input is lower than the voltage at the first input, the signal output by the comparator is, for example, low level; when the voltage at the second input is higher than the voltage at the first input, the signal output by the comparator is high level, i.e., an alarm signal. The output of each comparator in the comparator array 8011 is connected to the alarm matrix keyboard 802. After receiving an alarm signal, the alarm matrix keyboard 802 can determine the power supply chip and alarm type corresponding to the alarm signal, and feed it back to the controller 101 through the third IO expander 1033a.

[0053] The process by which controller 101 receives alarm signals from the alarm unit through the third IO expander is as follows: Figure 9 After power-on, the communication module (i.e., the third IO expander 1033a) executes step 901 to configure the DPS alarm threshold, i.e., at least one of the OVP alarm threshold, UVP alarm threshold, OCP alarm threshold, and OSD alarm threshold; step 902, determines whether an alarm signal is generated. If yes, proceed to step 903; if no, proceed to step 904; step 903, read the alarm and power off the protection; step 904, output normally; step 905, wait for power-off.

[0054] Indicative, Figure 10 A schematic diagram of an alarm unit is shown. The FPGA chip sends the OCP alarm threshold, OSD alarm threshold, OVP alarm threshold, and UVP alarm threshold to the comparators in the comparator array via the DAC chip. Another input of the comparator is connected to the output circuit of the DPS chip, and the output of the comparator is connected to the FPGA chip via the alarm matrix keypad in the comparator alarm collection module. When the comparator outputs an alarm signal, the FPGA chip receives the alarm signal, determines the corresponding DPS chip and alarm type, and performs a power-down operation. Figure 10As can be seen, in the alarm matrix keypad, switches in different rows correspond to different DSP chips, and switches in different columns correspond to different alarm types. That is, the "row lines" represent the channel number, and the number of "column lines" represents the alarm type. The FPGA chip can determine the corresponding DSP chip and alarm type by scanning the rows and columns corresponding to the alarm signals output from the alarm matrix keypad. In addition, the alarm unit can also perform over-temperature protection (OTP) alarms, such as... Figure 10 As shown, the fault alarm pins of each DPS chip are connected through the OTP alarm collection module. The OTP alarm collection module may include at least one IO expansion chip. When an OTP alarm signal is received, the corresponding DPS chip is determined and reported to the FPGA.

[0055] Based on the embodiments of this disclosure, the comparator array and the second digital-to-analog converter in the alarm unit are connected through the third IO expansion unit. The second digital-to-analog converter is controlled to output an alarm threshold to the comparator array and receive the alarm signal output by the comparator array. A large number of comparator alarm signals can be collected through a small number of IO pins to determine the abnormal chip and the type of abnormality. Among them, OVP alarm and UVP alarm usually monitor whether the power input voltage is abnormal, while OCP alarm and OSD alarm can detect the load status of the output terminal, thereby preventing damage to the chip under test and system failure.

[0056] In addition, this disclosure also provides a chip testing machine, which is equipped with a control system for peripheral devices as described in the above embodiments, as well as peripheral devices such as a test voltage control circuit and a chip driving circuit, so as to realize functions such as chip testing, voltage calibration and abnormal alarm.

Claims

1. A control system for peripheral devices, characterized in that, It includes a controller, a communication bus, and an I / O expansion module, wherein the I / O expansion module is communicatively connected to the controller via the communication bus; The IO expansion module is provided with at least one of a first IO expansion unit, a second IO expansion unit, and a third IO expansion unit; The controller is connected to the analog switch array in the test voltage control circuit through the first IO expansion unit, and is used to control the conduction state of the analog switch array through the first IO expansion unit. The correspondence between each pin of the chip under test and the test voltage is different in different conduction states of the analog switch array. The controller is also connected to the power chip and the selection switch in the chip driver circuit through the second IO expansion unit, and is used to control the output voltage value of the power chip and the switching state of the selection switch through the second IO expansion unit. The switching state of the selection switch is used to control the cascading mode of the power chip and the voltage calibration path. Finally, the controller is connected to the alarm unit in the chip driver circuit through the third IO expansion unit, and is used to receive the alarm signal corresponding to the power chip through the alarm unit.

2. The system according to claim 1, characterized in that, The IO expansion module is provided with the first IO expansion unit, the first IO expansion unit includes a first IO expander, the communication bus includes a first communication bus, the first IO expander is connected to the controller through the first communication bus, and the test voltage control circuit includes the analog switch array and at least one processing unit chip; The control terminal of the analog switch array is connected to the extended IO pin of the first IO expander, and the output terminal of the analog switch array is connected to the input terminal of the at least one processing unit chip. The output terminals of at least one processing unit chip are respectively connected to the pins of the corresponding chip under test, and are used to output the test voltage to the pins of the corresponding chip under test based on the test voltage reference signal received through the analog switch array.

3. The system according to claim 2, characterized in that, The test voltage control circuit also includes a first digital-to-analog converter; The input terminal of the first digital-to-analog converter is connected to the controller, and the output terminal of the first digital-to-analog converter is connected to the voltage input terminal of the analog switch array, for outputting at least one test voltage reference signal to the analog switch array based on the first control signal of the controller.

4. The system according to any one of claims 1 to 3, characterized in that, The IO expansion module is provided with a second IO expansion unit, the second IO expansion unit includes a communication bus expander, the communication bus includes a second communication bus, and the second IO expansion unit is connected to the controller through the second communication bus; At least one extended communication pin of the communication bus extender is connected to the control pin of at least one power chip via a corresponding third communication bus, for configuring the output voltage value of the at least one power chip based on the second control signal of the controller. The third communication bus has the same communication protocol as the second communication bus.

5. The system according to claim 4, characterized in that, The second IO expansion unit further includes a second IO expander, the communication bus includes a fourth communication bus, the second IO expander is connected to the controller through the fourth communication bus, and the chip driver circuit includes at least one first selection switch and at least one second selection switch; At least one extended IO pin of the second IO expander is connected to the control terminal of the at least one first selection switch and the control terminal of the at least one second selection switch, respectively, for controlling the conduction state of the at least one first selection switch based on the third control signal of the controller, and controlling the conduction state of the at least one second selection switch based on the fourth control signal of the controller. The cascading mode of the at least one power chip is different under different conduction states of the first selection switch, and the calibration path corresponding to the at least one power chip is different under different conduction states of the second selection switch.

6. The system according to any one of claims 1 to 3, characterized in that, The IO expansion module is provided with the third IO expansion unit, the third IO expansion unit includes a third IO expander, the communication bus includes a fifth communication bus, the third IO expander is connected to the controller through the fifth communication bus, and the alarm unit includes a comparator array and a second digital-to-analog converter; The input terminal of the second digital-to-analog converter is connected to the controller, and at least one output terminal of the second digital-to-analog converter is connected to the first input terminal of at least one comparator in the comparator array, for outputting an alarm threshold to the comparator array based on the fifth control signal of the controller. The alarm threshold includes at least one of an overvoltage alarm threshold, an undervoltage alarm threshold, an overcurrent alarm threshold, and an open circuit alarm threshold. The second input terminal of the at least one comparator is connected to the output pin of the power chip, and the at least one comparator is used to output an alarm signal when the magnitude relationship between the input signal at the first input terminal and the input signal at the second input terminal meets a preset alarm condition. At least one extended IO pin of the third IO expander is connected to the output of at least one comparator in the comparator array, for transmitting the alarm signal output by the comparator array to the controller.

7. The system according to claim 6, characterized in that, The third IO expansion unit further includes a fourth IO expander, and the communication bus includes a sixth communication bus. The fourth IO expander is connected to the controller through the sixth communication bus. At least one extended IO pin of the fourth IO expander is connected to the corresponding hardware alarm pin of the power chip to collect the over-temperature alarm signal of the power chip.

8. A chip testing machine, characterized in that, A control system equipped with peripheral devices as described in any one of claims 1 to 7.

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