A dosing circuit based on a pn bus

Abstract

The application discloses a kind of based on PN bus's batching circuit;Including core control module, dual-port module, power filter module, EMI protection module and clock module;Through dual-port module satisfies the communication demand of multiple equipment collaborative batching of industrial field;Through multistage capacitor filter architecture, power current fluctuation generated by batching system equipment start-stop can be effectively coped with, avoid power noise coupling to communication link;Through EMI protection module, avoid static damage core device, greatly reduce communication packet loss rate, guarantee signal high-speed, stable transmission under complex industrial electromagnetic environment;Through the lighting, extinguishing and flickering state of different color LED lamp, respectively, the link connection state and communication rate of double network port are visualized instruction, it is convenient and intuitive to judge network state, can quickly locate communication failure, improve the working efficiency and stability of batching system.

Description

Technical Field

[0001] This application relates to the field of communication technology for industrial batching systems, and in particular to a batching circuit based on a PN bus. Background Technology

[0002] PROFINET (PN) bus is the mainstream fieldbus in industrial automation, widely used for device interconnection and data exchange in batching systems. Traditional PN bus batching systems often use a single-port design for communication circuits, supporting only a single device connection. Furthermore, power filtering relies on a single-stage capacitor, making it susceptible to packet loss due to power ripple and high-frequency noise in the electromagnetic interference environment of industrial settings. Simultaneously, the lack of intuitive visual indicators for port operation status makes it difficult to quickly locate communication faults during on-site maintenance, severely impacting the efficiency and stability of the batching system. Utility Model Content

[0003] The main technical problem addressed by this application is to provide a dispensing circuit based on a PN bus to solve the problems of single-port limitation, weak anti-interference capability, and poor status visualization of traditional circuits.

[0004] To solve the above-mentioned technical problems, one technical solution adopted in this application is to provide a dispensing circuit based on a PN bus, comprising:

[0005] A dispensing circuit based on a PN bus includes a core control module, a two-port module, a power filtering module, an EMI protection module, and a clock module;

[0006] The core control module is connected to the dual-port module, the power filtering module and the clock module respectively. The dual-port module is provided with a link connection indicator interface and a port rate indicator interface.

[0007] The dual-port module is used to enable multiple device network ports to be connected to the PN bus dispensing system simultaneously;

[0008] The power filtering module uses dual power supply and multi-stage capacitor filtering to purify power supply noise.

[0009] The EMI protection module is positioned between the PE terminal and the GND terminal to suppress electromagnetic interference in the industrial environment.

[0010] The clock module provides a stable system clock for the core control module.

[0011] The dual-port module includes a first RJ45 network port J1A and a second RJ45 network port J1B. The first RJ45 network port J1A and the second RJ45 network port J1B are respectively connected to the corresponding differential signal pins on the core control module through their corresponding differential signal interfaces. A terminal matching network composed of resistors and capacitors is provided on the signal lines they are connected to reduce signal reflection and ensure the quality of long-distance transmission. The center tap on the first RJ45 network port J1A and the center tap on the second RJ45 network port J1B are both connected to a 3.3V power supply. The S1, S2 and S3 interfaces on the second RJ45 network port J1B are all connected to the PE terminal.

[0012] An EMI protection module is also provided between the PE terminal and the ground terminal GND. The EMI protection module includes a resistor and a capacitor connected in parallel to form an RC low-pass filter circuit.

[0013] Both the first RJ45 network port J1A and the second RJ45 network port J1B are equipped with a corresponding link connection indicator light interface and a port speed indicator light interface.

[0014] The positive terminals of the link connection indicator interfaces on the first RJ45 network port J1A and the second RJ45 network port J1B are both connected to a 3.3V power supply, and the negative terminals are connected in series with the corresponding current-limiting resistors and then connected to the corresponding link connection pins on the core control module.

[0015] The positive terminals of the port rate indicator interfaces on the first RJ45 network port J1A and the second RJ45 network port J1B are both connected to a 3.3V power supply, and the negative terminals are connected in series with the corresponding current-limiting resistors and then connected to the corresponding port rate pins on the core control module.

[0016] The link connection indicator light is a green LED. When the green LED is lit, it indicates that the corresponding first RJ45 network port J1A or second RJ45 network port J1B has established a link with the PN bus device. When it flashes, it indicates that there is batching data being sent and received.

[0017] The port speed indicator is a yellow LED. When the yellow LED is lit, it indicates that the corresponding first RJ45 network port J1A or second RJ45 network port J1B is working at a speed of 100Mbps. When it is off, it indicates that it is working at a speed of 10Mbps.

[0018] The power supply filtering module has two power supplies: a 3.3V power supply and a 1.8V power supply. A parallel capacitor is connected between the 3.3V power supply and GND to filter out high, medium and low frequency ripple in the power supply. A parallel capacitor is also connected between the 1.8V power supply and GND to decouple the low voltage domain of the chip core at high frequency.

[0019] The clock module includes a crystal oscillator Y1 and an external capacitor. The crystal oscillator Y1 and the external capacitor form a resonant circuit, which is connected to the input and output pins of the external oscillator on the core control module to provide a stable clock signal for the core control module U1.

[0020] The core control module uses the KSZ8863RLL chip U1. The core control module is grounded after being connected to an external pull-down resistor R19 through its reference clock input / output interface. The reference clock output interface is fed back to the MII interface to achieve clock synchronization with the PN bus master controller.

[0021] The reset pin on the core control module forms a power-on reset circuit through pull-up resistors, pull-down resistors, and energy storage capacitors to ensure that the chip completes initialization after power-on.

[0022] The core control module is interconnected with the main controller of the PN bus batching system through its MII interface to realize bidirectional transmission of batching formula data, silo weight data, and equipment start / stop signals; it completes the configuration of the PHY layer and adapts to the communication protocol requirements of the PN bus through an external pull-up resistor connected to its SMI interface; it is used for reading and writing chip registers through the SPI interface to realize flexible adjustment of communication parameters; and it reports chip status events to the processor through an interrupt interface pull-up resistor connected to the 3.3V power supply.

[0023] The beneficial effects of this application are:

[0024] 1. This application uses a dual-port module, namely the first RJ45 network port J1A and the second RJ45 network port J1B, which can simultaneously connect to at least two types of PN bus batching devices, including batching scales, silo controllers, and host computers. This breaks the limitation of traditional single-port circuits that only support the connection of a single device, effectively improves the device interconnection and scalability of the PN bus batching system, and meets the communication needs of multi-device collaborative batching in industrial sites.

[0025] 2. The power supply filtering module in this application adopts a multi-stage capacitor filtering architecture. Different capacitance values ​​are connected in parallel at the 3.3V power supply terminal to filter out low-frequency ripple and high-frequency noise respectively. Multiple high-frequency decoupling capacitors are connected in parallel at the 1.8V power supply terminal to ensure stable power supply to the chip core. This can effectively cope with the power current fluctuations caused by the start-up and shutdown of the batching system equipment and avoid power noise coupling to the communication link.

[0026] 3. The EMI protection module in this application is configured with an RC network consisting of a high-voltage capacitor and a high-resistance resistor. This network can filter out high-frequency electromagnetic interference in industrial environments and quickly release static charge to prevent damage to core components. It also significantly reduces the packet loss rate and ensures high-speed and stable transmission of ingredient formula data, silo weight data, and equipment start-up and shutdown signals in complex industrial electromagnetic environments.

[0027] 4. This application includes a link connection indicator and a port speed indicator. By using different colored LEDs to indicate the link connection status and communication speed of the dual network ports, the link connection status and communication speed are visually indicated. This allows for easy and intuitive judgment of the network status, quick location of communication faults, and improvement of the efficiency and stability of the batching system. Attached Figure Description

[0028] Figure 1 This is a simplified circuit diagram of the core control module U1 according to one embodiment of this application;

[0029] Figure 2 This is a simplified circuit diagram of the first RJ45 network port J1A according to an embodiment of this application;

[0030] Figure 3 This is a simplified circuit diagram of the second RJ45 network port J1B according to an embodiment of this application;

[0031] Figure 4 This is a simplified circuit diagram of a 3.3V power supply filter module according to one embodiment of this application;

[0032] Figure 5 This is a simplified circuit diagram of another 3.3V power supply filtering module according to one embodiment of this application;

[0033] Figure 6 This is a simplified circuit diagram of a 1.87V power supply filter module according to one embodiment of this application;

[0034] Figure 7 This is a simplified circuit diagram of an EMI protection module according to an embodiment of this application; Detailed Implementation

[0035] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly set on the other component; when a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to the other component.

[0037] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "vertical", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0038] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" or "several" means two or more, unless otherwise explicitly specified.

[0039] It should be noted that the structures, proportions, sizes, etc., shown in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0040] Figure 1 - Figure 7 An embodiment of the dispensing circuit based on the PN bus of this application is shown, including a core control module, a dual-port module, a power filtering module, an EMI protection module, and a clock module.

[0041] The core control module is connected to the dual-port module, the power filtering module, and the clock module, respectively. The dual-port module is equipped with a link connection indicator interface and a port rate indicator interface.

[0042] The dual-port module is used to connect multiple device network ports to the PN bus batching system simultaneously.

[0043] Furthermore, the dual-port module includes a first RJ45 network port J1A and a second RJ45 network port J1B. The first RJ45 network port J1A and the second RJ45 network port J1B are respectively connected to the corresponding differential signal pins (TXP2 / TXM2, RXP2 / RXM2 pins) on the core control module through their corresponding differential signal interfaces (TD+, TD-, RD+, RD-). A terminal matching network composed of resistors and capacitors (R6 / R7 / C1, R8 / R9 / C2, R15 / R16 / C7, R17 / R18 / C8) is set on the signal lines to reduce signal reflection and ensure the quality of long-distance transmission.

[0044] The center tap on the first RJ45 network port J1A and the center tap on the second RJ45 network port J1B are both connected to a 3.3V power supply; the S1, S2 and S3 interfaces on the second RJ45 network port J1B are all connected to the PE end.

[0045] Specifically, the core control module uses the KSZ8863RLL chip U1. The first RJ45 network port J1A is connected to the differential signal pins TXP2 and TXM2 on the KSZ8863RLL chip U1 through its differential signal interfaces TD+ and TD- respectively. A resistor R6 is connected in series on one of the connection lines, and a resistor R7 is connected in series on the other connection line. The other ends of resistors R6 and R7 are connected together and then connected in series with capacitor C1 before being grounded.

[0046] The first RJ45 network port J1A is connected to the differential signal pins RXP2 and RXM2 on the KSZ8863RLL chip U1 via its differential signal interfaces RD+ and RD- respectively. A resistor R8 is connected in series on one of the connection lines, and a resistor R9 is connected in series on the other connection line. The other ends of resistors R8 and R9 are connected together and then connected in series with capacitor C2 before being grounded.

[0047] The second RJ45 network port J1B is connected to the differential signal pins TXP1 and TXM1 on the KSZ8863RLL chip U1 via its differential signal interfaces TD+ and TD- respectively. A resistor R15 is connected in series on one of the connection lines, and a resistor R16 is connected in series on the other connection line. The other ends of resistors R15 and R16 are connected together and then connected in series with a capacitor C7 before being grounded.

[0048] The second RJ45 network port J1B is connected to the differential signal pins RXP1 and RXM1 on the KSZ8863RLL chip U1 via its differential signal interfaces RD+ and RD- respectively. A resistor R17 is connected in series on one of the connection lines, and a resistor R18 is connected in series on the other connection line. The other ends of resistors R17 and R18 are connected together and then connected in series with a capacitor C8 before being grounded.

[0049] The resistors R6, R7, R8, R9, R15, R16, R17, and R18 all have a resistance of 49.9Ω, and the capacitors C1, C2, C7, and C8 all have a capacitance of 0.1uF / 16V. The resulting termination matching network can achieve 100Ω differential impedance matching and reduce signal reflection.

[0050] The center tap CT on the first RJ45 network port J1A and the second RJ45 network port J1B are each connected to a 3.3V power supply to provide DC bias for the differential signal, optimize the differential signal quality, and ensure signal transmission stability.

[0051] The S1, S2, and S3 interfaces on the second RJ45 network port J1B are all connected to the PE end.

[0052] Both the first RJ45 network port J1A and the second RJ45 network port J1B are equipped with corresponding link connection indicator interfaces and port speed indicator interfaces.

[0053] The positive terminals of the link connection indicator interfaces on the first RJ45 network port J1A and the second RJ45 network port J1B are both connected to a 3.3V power supply, and the negative terminals are connected in series with the corresponding current-limiting resistors and then connected to the corresponding link connection pins on the core control module.

[0054] The positive terminals of the corresponding port rate indicator interfaces on the first RJ45 network port J1A and the second RJ45 network port J1B are both connected to a 3.3V power supply, and the negative terminals are connected in series with the corresponding current-limiting resistors and then connected to the corresponding port rate pins on the core control module.

[0055] Specifically: the positive terminal LED_G+ of the link connection indicator on the first RJ45 network port J1A is connected to a 3.3V power supply, and the negative terminal LED_G- is connected to the link connection pin P2 LED LNK on the core control module after being connected in series with the current limiting resistor R1.

[0056] The positive terminal of the port rate indicator LED_Y+ on the first RJ45 network port J1A is connected to a 3.3V power supply, and the negative terminal is connected to the port rate pin P2 LED SPD on the core control module via a series current-limiting resistor R10.

[0057] The positive terminal of the link connection indicator LED_G+ on the second RJ45 network port J1B is connected to a 3.3V power supply, and the negative terminal LED_G- is connected to the link connection pin P1 LED LNK on the core control module after being connected in series with the current limiting resistor R14.

[0058] The positive terminal of the port rate indicator LED_Y+ on the second RJ45 network port J1B is connected to a 3.3V power supply, and the negative terminal LED_Y- is connected to the corresponding port rate pin P1 LED SPD on the core control module after being connected in series with the current limiting resistor R21.

[0059] The link connection indicator is a green LED. When the green LED is lit, it means that the corresponding first RJ45 network port J1A or second RJ45 network port J1B has established a link with the PN bus device. When it flashes, it means that there is batching data being sent and received.

[0060] The port speed indicator is a yellow LED. When the yellow LED is lit, it means that the corresponding first RJ45 network port J1A or second RJ45 network port J1B is working at a speed of 100Mbps. When it is off, it means that it is working at a speed of 10Mbps.

[0061] The EMI protection module is positioned between the PE terminal and the GND terminal to suppress electromagnetic interference in the industrial environment.

[0062] Furthermore, an EMI protection module is provided between the PE terminal and the grounding terminal GND. The EMI protection module includes parallel resistors and capacitors, forming an RC low-pass filter circuit.

[0063] Specifically, a resistor and capacitor are connected in parallel between the PE terminal and the grounding terminal GND. The resistor is 1MΩ (R29) and the capacitor is 1nF / 2kV (C32). The resistor and capacitor form a low-pass filter circuit to filter out high-frequency electromagnetic interference in the industrial environment. At the same time, the 2kV capacitor can release static charge to prevent electrostatic damage to U1 and RJ45 network ports, making it suitable for the complex electromagnetic environment of the batching workshop.

[0064] The power supply filtering module uses dual power supply and multi-stage capacitor filtering to purify power supply noise.

[0065] Furthermore, the dual power supplies on the power filtering module include a 3.3V power supply and a 1.8V power supply; a parallel capacitor is connected between the 3.3V power supply and GND to filter out high, medium and low frequency ripple in the power supply; a parallel capacitor is also connected between the 1.8V power supply and GND to perform high-frequency decoupling of the low voltage domain of the chip core.

[0066] Specifically, a set of parallel capacitors C3 and C4 are connected between the 3.3V power supply and GND. The capacitance parameters of capacitors C3 and C4 are both 1uF / 16V, which can filter out the low-to-medium frequency ripple (a few kHz to tens of MHz) of the 3.3V power supply and provide energy storage buffer to cope with the power current fluctuations when the batching system equipment starts and stops.

[0067] A set of capacitors C9 and C10 are connected in parallel between the 3.3V power supply and GND. The capacitance parameters of capacitors C9 and C10 are both 0.1uF / 16V to filter out high-frequency noise (tens of MHz to hundreds of MHz) and prevent noise from coupling to the power supply pin of U1.

[0068] A set of three capacitors C11, C12 and C13 are connected in parallel between the 1.8V power supply and GND. The parameters of capacitors C11, C12 and C13 are all 0.1uF / 16V. This provides high-frequency decoupling for the low voltage domain of the chip core, ensuring the stability of digital logic and analog signal processing.

[0069] The clock module provides a stable system clock for the core control module.

[0070] Furthermore, the clock module includes a crystal oscillator Y1 and external capacitors. The crystal oscillator Y1 and external capacitors form a resonant circuit, which is connected to the input and output pins of the external oscillator on the core control module to provide a stable clock signal for the core control module U1.

[0071] Specifically: the crystal oscillator Y1 has a parameter of 25MHz, and the capacitors include capacitors C5 and C6, which are 22pF / 16V. Capacitors C5 and C6 are connected in parallel and then grounded. Y1, C5 and C6 form a resonant circuit, which is connected to the X1 and X2 pins on the core control module.

[0072] A 1M resistor R20 is also connected between pins X1 and X2, in parallel with crystal oscillator Y1.

[0073] The core control module is grounded by connecting an external pull-down resistor R19 to its reference clock input / output interface. The reference clock output interface is fed back to the MII interface to achieve clock synchronization with the PN bus master controller.

[0074] Specifically, after connecting the REFCLKI_3 pin and REFCLKO_3 on the core control module U1, an external pull-down resistor R19 is connected. REFCLKO_3 outputs a reference clock, which is fed back to the ETH REF CLK pin of the MII interface to achieve clock synchronization with the PN bus master controller.

[0075] The reset pin on the core control module U1 forms a power-on reset circuit through pull-up resistors, pull-down resistors, and energy storage capacitors to ensure that the chip completes initialization after power-on.

[0076] Specifically, the FXSD1 and RSTN pins on the core control module U1 form a power-on reset circuit through pull-up resistor R4, pull-down resistor R5, and energy storage capacitor C33 to ensure that the chip completes initialization after power-on.

[0077] The core control module interconnects with the main controller of the PN bus batching system through its MII interface (ETH CRS DV / ETH REF CLK / ETH RXD0 / ETHRXD1 pins) to achieve bidirectional transmission of batching formula data, silo weight data, and equipment start / stop signals; it configures the PHY layer and adapts to the PN bus communication protocol requirements by connecting external pull-up resistors through its SMI interface (MDIO / MDC pins); it uses the SPI interface (SPISN / SPIQ pins) for reading and writing chip registers to configure and flexibly adjust communication parameters; and it reports chip status events to the processor by pulling up resistor R11 to 3.3V through the interrupt interface.

[0078] Therefore, this application discloses a batching circuit based on a PN bus. When the circuit of this invention operates in a PN bus batching system, it meets the communication needs of collaborative batching of multiple devices in an industrial setting through a dual-port module; the multi-level capacitor filtering architecture can effectively cope with the power current fluctuations caused by the start-up and shutdown of the batching system equipment, and avoid power noise coupling to the communication link; the EMI protection module prevents electrostatic damage to core components, significantly reduces the communication packet loss rate, and ensures high-speed and stable signal transmission in complex industrial electromagnetic environments; the on, off, and flashing states of different colored LEDs provide visual indications of the link connection status and communication rate of the dual network ports, making it convenient to intuitively judge the network status, quickly locate communication faults, and improve the working efficiency and stability of the batching system.

[0079] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A dispensing circuit based on a PN bus, characterized in that, It includes a core control module, a dual-port module, a power filtering module, an EMI protection module, and a clock module; The core control module is connected to the dual-port module, the power filtering module and the clock module respectively. The dual-port module is provided with a link connection indicator interface and a port rate indicator interface. The dual-port module is used to enable multiple device network ports to be connected to the PN bus dispensing system simultaneously; The power filtering module uses dual power supply and multi-stage capacitor filtering to purify power supply noise. The EMI protection module is positioned between the PE terminal and the GND terminal to suppress electromagnetic interference in the industrial environment. The clock module provides a stable system clock for the core control module.

2. The dispensing circuit based on a PN bus according to claim 1, characterized in that, The dual-port module includes a first RJ45 network port J1A and a second RJ45 network port J1B. The first RJ45 network port J1A and the second RJ45 network port J1B are respectively connected to the corresponding differential signal pins on the core control module through their corresponding differential signal interfaces. A terminal matching network composed of resistors and capacitors is provided on the signal lines they are connected to reduce signal reflection and ensure the quality of long-distance transmission. The center tap on the first RJ45 network port J1A and the center tap on the second RJ45 network port J1B are both connected to a 3.3V power supply. The S1, S2 and S3 interfaces on the second RJ45 network port J1B are all connected to the PE terminal.

3. The dispensing circuit based on a PN bus according to claim 2, characterized in that, Both the first RJ45 network port J1A and the second RJ45 network port J1B are equipped with a corresponding link connection indicator light interface and a port speed indicator light interface. The positive terminals of the link connection indicator interfaces on the first RJ45 network port J1A and the second RJ45 network port J1B are both connected to a 3.3V power supply, and the negative terminals are connected in series with the corresponding current-limiting resistors and then connected to the corresponding link connection pins on the core control module. The positive terminals of the corresponding port rate indicator interfaces on the first RJ45 network port J1A and the second RJ45 network port J1B are both connected to a 3.3V power supply, and the negative terminals are connected in series with the corresponding current-limiting resistors and then connected to the corresponding port rate pins on the core control module.

4. The dispensing circuit based on a PN bus according to claim 3, characterized in that, The link connection indicator light is a green LED. When the green LED is lit, it indicates that the corresponding first RJ45 network port J1A or second RJ45 network port J1B has established a link with the PN bus device. When it flashes, it indicates that there is material data being sent and received. The port speed indicator is a yellow LED. When the yellow LED is lit, it indicates that the corresponding first RJ45 network port J1A or second RJ45 network port J1B is working at a speed of 100Mbps. When it is off, it indicates that it is working at a speed of 10Mbps.

5. A dispensing circuit based on a PN bus according to claim 1, characterized in that, The EMI protection module includes resistors and capacitors connected in parallel, forming an RC low-pass filter circuit.

6. The dispensing circuit based on a PN bus according to claim 1, characterized in that, The power supply filtering module has two power supplies: a 3.3V power supply and a 1.8V power supply. A parallel capacitor is connected between the 3.3V power supply and GND to filter out high, medium and low frequency ripple in the power supply. A parallel capacitor is also connected between the 1.8V power supply and GND to decouple the low voltage domain of the chip core at high frequency.

7. The dispensing circuit based on a PN bus according to claim 1, characterized in that, The clock module includes a crystal oscillator Y1 and an external capacitor. The crystal oscillator Y1 and the external capacitor form a resonant circuit, which is connected to the input and output pins of the external oscillator on the core control module to provide a stable clock signal for the core control module U1.

8. The dispensing circuit based on a PN bus according to claim 1, characterized in that, The core control module uses the KSZ8863RLL chip U1. The core control module is grounded after being connected to an external pull-down resistor R19 through its reference clock input / output interface. The reference clock output interface is fed back to the MII interface to achieve clock synchronization with the PN bus master controller.

9. A dispensing circuit based on a PN bus according to claim 8, characterized in that, The reset pin on the core control module forms a power-on reset circuit through pull-up resistors, pull-down resistors, and energy storage capacitors.

10. A dispensing circuit based on a PN bus according to claim 9, characterized in that, The core control module is interconnected with the main controller of the PN bus batching system through its MII interface, external pull-up resistors through its SMI interface, read and write configuration of chip registers through its SPI interface, and pull-up resistors to the 3.3V power supply through its interrupt interface.

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