A high-precision low-temperature drift bandgap reference circuit

Abstract

The utility model relates to a kind of high-precision low temperature drift band gap reference circuit, including band gap reference core circuit, starting circuit, bias circuit, first operational amplifier circuit, PSRR promotion circuit and high-order curvature compensation circuit.Wherein, the starting circuit ensures that the circuit is out of degenerate state;The bias circuit provides stable current;The first operational amplifier circuit clamps core circuit potential;The PSRR promotion circuit enhances power supply rejection ratio by feedback structure;The high-order curvature compensation circuit carries out nonlinear temperature compensation to core circuit, further reduces temperature coefficient;In addition, the band gap reference core circuit generates zero temperature coefficient reference voltage using double triode and resistance network.It needs to be explained that, in the utility model embodiment, each module works cooperatively, optimizes temperature drift by high-order compensation, significantly suppresses power noise interference by combining PSRR promotion technology, realizes high-precision, low temperature drift reference voltage output.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, specifically to a high-precision low-temperature drift bandgap reference circuit. Background Technology

[0002] With the increasing demands of modern electronic systems on power management and the performance of precision analog circuits, bandgap reference circuits, as a reference voltage source capable of providing extremely low temperature coefficients independent of the supply voltage, have been widely used in various analog integrated circuits and precision measuring instruments. A typical bandgap reference voltage is approximately 1.2V, achieved by weighting and superimposing the positive temperature coefficient voltage (VBE) of the semiconductor PN junction with the thermoelectric potential generated by the current with the opposite temperature coefficient, resulting in an overall near-zero temperature coefficient. However, traditional first-order bandgap circuits exhibit significant temperature drift, making them unsuitable for high-precision applications.

[0003] In existing technologies, to reduce the temperature coefficient, most solutions employ second- or third-order temperature compensation networks. These networks compensate for second- or even higher-order curvature errors in the bandgap core module by adjusting the resistance ratio, adding diode series units, or using temperature-sensitive element networks. However, these solutions typically introduce additional process sensitivity, causing significant deviations in the circuit across different process corners and wafer locations. Furthermore, noise and mismatch within the compensation network itself can negatively impact the stability of the reference voltage. In addition, bandgap reference circuits face degenerate lock-up issues during startup, meaning that the bandgap core module may fail to enter its operating state properly when power is first switched on or when the power supply voltage fluctuates, leading to hysteresis or instability in the reference voltage. On the other hand, traditional bandgap circuits have low power supply rejection ratios (PSRR), making the reference voltage susceptible to interference from power supply noise, surges, or ripple, which can severely affect the measurement accuracy and control stability of the entire system. Utility Model Content

[0004] The purpose of this invention is to provide a high-precision, low-temperature drift bandgap reference circuit that integrates a startup circuit, a bias circuit, a bandgap reference core, a first-stage operational amplifier, a PSRR boost circuit, and a high-order curvature compensation circuit. This circuit can achieve high precision, low temperature drift, a wide operating voltage range, and strong anti-interference capability.

[0005] To achieve the above objectives, this utility model provides the following technical solution:

[0006] A high-precision, low-temperature drift bandgap reference circuit includes a bandgap reference core circuit, a startup circuit, a bias circuit, a first operational amplifier circuit, a PSRR boost circuit, and a high-order curvature compensation circuit. The startup circuit is used to free the circuit from a degenerate state. The bandgap reference core circuit generates a reference voltage with zero temperature coefficient. The bias circuit provides bias current to the circuit. The first operational amplifier circuit clamps the potential of the bandgap core module. The PSRR boost circuit improves the power supply rejection ratio of the overall circuit. The high-order curvature compensation circuit reduces the temperature coefficient of the bandgap reference core circuit.

[0007] The first operational amplifier circuit and the PSRR boost circuit are both connected to the bandgap reference core circuit. The bias circuit is connected to the first operational amplifier circuit and the bandgap reference core circuit. The startup circuit is connected to the bias circuit and the bandgap reference core circuit. The higher-order curvature compensation circuit is connected to the bandgap reference core circuit.

[0008] Furthermore, in a preferred embodiment of the present invention, the bandgap reference core circuit includes a first PMOS transistor, a first resistor R1, a second resistor R9, a third resistor R6, a fourth resistor R7, a fifth resistor R8, a first transistor Q1, and a second transistor Q2.

[0009] The source of the first PMOS transistor is connected to the power supply voltage. The drain of the first PMOS transistor is connected to the first resistor R1. The first resistor R1 is connected to the second resistor R9. The third resistor R6 and the fourth resistor R7 are both connected to the second resistor R9. The third resistor R6 is connected to the fifth resistor R8. The fifth resistor R8 is connected to the emitter of the second transistor Q2. The base and collector of the second transistor Q2 are both connected to ground. The fourth resistor R7 is connected to the emitter of the first transistor Q1. The base and collector of the first transistor Q1 are both connected to ground.

[0010] Furthermore, in a preferred embodiment of the present invention, the startup circuit includes a second PMOS transistor M12, a third PMOS transistor M13, a fourth PMOS transistor M14, a fifth PMOS transistor M15, a sixth PMOS transistor M21, a first NMOS transistor M16, a second NMOS transistor M17, a third NMOS transistor M18, a fourth NMOS transistor M19, a fifth NMOS transistor M20, and a first inverter;

[0011] The second PMOS transistor M12, the third PMOS transistor M13, the fourth PMOS transistor M14, and the fifth PMOS transistor M15 are connected in parallel. The source of the second PMOS transistor M12 is connected to the power supply voltage, and the drain of the fifth PMOS transistor M15 is connected to the drain of the second NMOS transistor M17. The source of the second NMOS transistor M17 is grounded. The source of the sixth PMOS transistor M21 is connected to the power supply voltage, and the drain of the sixth PMOS transistor M21 is connected to the drain of the first NMOS transistor M16. The gate of the first NMOS transistor M16 is connected to its drain, and the gate of the first NMOS transistor M16 is connected to the drain of the second NMOS transistor M17. The gate of the first NMOS transistor M17 is connected to the second NMOS transistor M18, the drain of the third NMOS transistor M18 is connected to the drain of the second NMOS transistor M17, and the source of the third NMOS transistor M18 is grounded; the drain of the fourth NMOS transistor M19 is connected to the drain of the second NMOS transistor M17, and the source of the fourth NMOS transistor M19 is grounded; the gate of the fifth NMOS transistor M20 is connected to the drain of the second NMOS transistor M17, the source of the fifth NMOS transistor M20 is grounded, the drain of the fifth NMOS transistor M20 is connected to the gate of the sixth PMOS transistor M21, and the output of the first inverter is connected to the gate of the fourth NMOS transistor M19.

[0012] Further, in a preferred embodiment of the present invention, the bias circuit includes a seventh PMOS transistor M8, an eighth PMOS transistor M9, a ninth PMOS transistor M25, a sixth NMOS transistor M10, a seventh NMOS transistor M11, an eighth NMOS transistor M26, a ninth NMOS transistor M27, a sixth resistor R0, a seventh resistor R14, an eighth resistor R15, a ninth resistor R16, and a third transistor Q0;

[0013] The gate of the seventh PMOS transistor M8 is connected to the gate of the eighth PMOS transistor M9. The source of the seventh PMOS transistor M8 is connected to the source of the eighth PMOS transistor M9, and the gate and drain of the seventh PMOS transistor M8 are shorted. The gate of the ninth PMOS transistor M25 is connected to the gates of the seventh PMOS transistor M8 and the eighth PMOS transistor M9. The drain and source of the ninth PMOS transistor M25 are connected to the power supply voltage. The gate of the sixth NMOS transistor M10 is connected to the gate of the seventh NMOS transistor M11. The drain of the sixth NMOS transistor M10 is connected to the drain of the seventh PMOS transistor M8. The source of the sixth NMOS transistor M10 is connected to the sixth resistor. The resistors R0, R14, R15, and R16 are connected in series. The ninth resistor R16 is grounded. The emitter of the third transistor Q0 is connected to the source of the seventh NMOS transistor M11. The base and collector of the third transistor Q0 are both grounded. The drain of the ninth NMOS transistor M27 is connected to the gate of the seventh NMOS transistor M11. The source of the ninth NMOS transistor M27 is grounded. The gate of the ninth NMOS transistor M27 is connected to the output of the first inverter. The gate of the eighth NMOS transistor M26 is connected to the gate of the seventh NMOS transistor M11. The source and drain of the eighth NMOS transistor M26 are grounded.

[0014] Furthermore, in a preferred embodiment of the present invention, the first operational amplifier circuit includes a tenth PMOS transistor M28, an eleventh PMOS transistor M4, a twelfth PMOS transistor M6, a thirteenth PMOS transistor M0, a fourteenth PMOS transistor M1, a tenth NMOS transistor M3, an eleventh NMOS transistor M2, a twelfth NMOS transistor M30, a thirteenth NMOS transistor M5, a tenth resistor R4, and a first capacitor C0;

[0015] The source of the tenth PMOS transistor M28 is connected to the power supply voltage. The drain of the tenth PMOS transistor M28 is connected to the drain of the seventh PMOS transistor M8. The source of the eleventh PMOS transistor M4 is connected to the power supply voltage. The drain of the eleventh PMOS transistor M4 is connected to the sources of the thirteenth PMOS transistor M0 and the fourteenth PMOS transistor M1. The drain of the thirteenth PMOS transistor M0 is connected to the drain of the tenth NMOS transistor M3. The source of the tenth NMOS transistor M3 is grounded. The gate and drain of the tenth NMOS transistor M3 are shorted. The drain of the fourteenth PMOS transistor M1 is connected to the drain of the eleventh NMOS transistor M2. The source of NMOS transistor M2 is grounded. The gates of the tenth NMOS transistor M3 and the eleventh NMOS transistor M2 are connected. The source of the twelfth PMOS transistor M6 is connected to the power supply voltage. The gate of the twelfth PMOS transistor M6 is connected to the gate of the eleventh PMOS transistor M4. The drain of the twelfth PMOS transistor M6 is connected to the drain of the thirteenth NMOS transistor M5. The source of the thirteenth NMOS transistor M5 is grounded. The drain of the twelfth NMOS transistor M30 is connected to the gate of the thirteenth NMOS transistor M5. The source of the twelfth NMOS transistor M30 is grounded. The gate of the twelfth NMOS transistor M30 is connected to the output terminal of the first inverter.

[0016] The tenth resistor R4 is connected in series with the first capacitor C0 and is connected across the eleventh NMOS transistor M2 and the thirteenth NMOS transistor M5. The thirteenth PMOS transistor M0 and the fourteenth PMOS transistor M1 are respectively connected to the third resistor R6 and the fourth resistor R7.

[0017] Furthermore, in a preferred embodiment of the present invention, the PSRR boosting circuit includes a fifteenth PMOS transistor M29 and a sixteenth PMOS transistor M22;

[0018] The source of the fifteenth PMOS transistor M29 is connected to the power supply voltage, the drain of the fifteenth PMOS transistor M29 is connected to the gate of the sixteenth PMOS transistor M22, the source of the sixteenth PMOS transistor M22 is connected to the first resistor R1, the drain of the sixteenth PMOS transistor M22 is grounded, and the gate of the sixteenth PMOS transistor M22 is connected to the first capacitor C0.

[0019] Furthermore, in a preferred embodiment of the present invention, the high-order curvature compensation circuit includes a second operational amplifier circuit, a seventeenth PMOS transistor M23, an eighteenth PMOS transistor M24, an eleventh resistor R10, a twelfth resistor R11, a thirteenth resistor R12, a fourteenth resistor R13, and a fourth transistor Q3.

[0020] The inverting input of the second operational amplifier circuit is connected to the first resistor R1. The non-inverting input of the second operational amplifier circuit is connected to the drain of the seventeenth PMOS transistor M23. The output of the second operational amplifier circuit is connected to the gates of the seventeenth PMOS transistor M23 and the eighteenth PMOS transistor M24. The sources of the seventeenth PMOS transistor M23 and the eighteenth PMOS transistor M24 are connected to the power supply voltage. The drain of the seventeenth PMOS transistor M23 is connected to the thirteenth resistor R12. The thirteenth resistor R12 is connected in series with the fourteenth resistor R13. The fourteenth resistor R13 is grounded. The emitter of the fourth transistor Q3 is connected to the drain of the eighteenth PMOS transistor M24. The base and collector of the fourth transistor Q3 are grounded. The eleventh resistor R10 is connected between the third resistor R6 and the emitter of the fourth transistor Q3. The twelfth resistor R11 is connected between the fourth resistor R7 and the emitter of the fourth transistor Q3.

[0021] The beneficial effects of the high-precision low-temperature drift bandgap reference circuit provided by this utility model are:

[0022] The high-precision, low-temperature drift bandgap reference circuit provided in this invention fully considers the tendency of traditional bandgap references to fall into degeneracy upon power-up and the impact of power supply ripple on output accuracy. Through a startup circuit composed of parallel multi-stage PMOS / NMOS devices and a feedback inverter, the core module can be quickly started under weak current conditions, ensuring the bandgap circuit reliably enters the operating region. Furthermore, the specially designed bias network provides a stable and controllable bias current for the bandgap core and operational amplifier, meeting current requirements across a wide temperature and process angle range while effectively reducing the impact of process mismatch of each stage of the device on the reference voltage. Therefore, this application further improves the circuit's startup reliability and power supply rejection performance while ensuring an extremely low temperature coefficient. Moreover, by introducing high-order curvature compensation, a powerful startup circuit, a stable bias network, and a dedicated PSRR boost structure, it achieves a high-precision, low-temperature drift, wide operating voltage range, and strong anti-interference capability bandgap reference circuit. Attached Figure Description

[0023] Figure 1 A schematic diagram of a high-precision low-temperature drift bandgap reference circuit provided for an embodiment of this utility model;

[0024] Figure 2 Overall circuit diagram of the high-precision low-temperature drift bandgap reference circuit provided for embodiments of this utility model;

[0025] Figure 3 The core circuit diagram of the bandgap reference in the high-precision low-temperature drift bandgap reference circuit provided in this embodiment of the utility model;

[0026] Figure 4 This is a diagram of the startup circuit in the high-precision low-temperature drift bandgap reference circuit in this embodiment of the invention.

[0027] Figure 5 This is a diagram of the bias circuit in the high-precision low-temperature drift bandgap reference circuit in this embodiment of the present invention.

[0028] Figure 6 This is a circuit diagram of the first operational amplifier in the high-precision low-temperature drift bandgap reference circuit of this utility model embodiment;

[0029] Figure 7 This is a diagram of the PSRR boosting circuit in the high-precision low-temperature drift bandgap reference circuit of this utility model embodiment;

[0030] Figure 8 This is a high-order curvature compensation circuit diagram in the high-precision low-temperature drift bandgap reference circuit of this utility model embodiment. Detailed Implementation

[0031] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments.

[0032] Furthermore, to make the objectives, technical solutions, and advantages of the specific embodiments of this application clearer, the technical solutions in the specific embodiments of this application will be described more clearly and completely below. Where specific conditions are not specified in the specific embodiments, they shall be performed under conventional conditions or conditions recommended by the manufacturer. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the specification herein is for the purpose of describing particular embodiments only and is not intended to limit the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0033] This application provides a high-precision low-temperature drift bandgap reference circuit, which relates to a bandgap reference architecture that integrates high-order curvature compensation, PSRR enhancement module and multi-circuit collaborative optimization. It is suitable for integrated circuit systems with stringent requirements for temperature stability and power supply noise suppression, such as high-precision ADCs / DACs, medical electronics, and precision sensors.

[0034] Specifically, this application provides a high-precision, low-temperature drift bandgap reference circuit including a bandgap reference core circuit, a startup circuit, a bias circuit, a first operational amplifier circuit, a PSRR boost circuit, and a high-order curvature compensation circuit. The startup circuit is used to free the circuit from degeneracy; the bandgap reference core circuit generates a reference voltage with zero temperature coefficient; the bias circuit provides bias current to the circuit; the first operational amplifier circuit clamps the potential of the bandgap core module; the PSRR boost circuit improves the power supply rejection ratio of the overall circuit; and the high-order curvature compensation circuit reduces the temperature coefficient of the bandgap reference core circuit. It should be noted that in this application embodiment, the first operational amplifier circuit and the PSRR boost circuit are both connected to the bandgap reference core circuit; the bias circuit is connected to both the first operational amplifier circuit and the bandgap reference core circuit; the startup circuit is connected to both the bias circuit and the bandgap reference core circuit; and the high-order curvature compensation circuit is connected to the bandgap reference core circuit.

[0035] Further, in some embodiments of this application, the bandgap reference core circuit includes a first PMOS transistor, a first resistor R1, a second resistor R9, a third resistor R6, a fourth resistor R7, a fifth resistor R8, a first transistor Q1, and a second transistor Q2; wherein, the source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the first resistor R1, the first resistor R1 is connected to the second resistor R9, the third resistor R6 and the fourth resistor R7 are both connected to the second resistor R9, the third resistor R6 is connected to the fifth resistor R8, the fifth resistor R8 is connected to the emitter of the second transistor Q2, the base and collector of the second transistor Q2 are both connected to ground, the fourth resistor R7 is connected to the emitter of the first transistor Q1, and the base and collector of the first transistor Q1 are both connected to ground. In other words, the bandgap reference core circuit has one source connected to the power supply voltage V. DD The system consists of a PMOS transistor, a series and branched precision resistor network (R1→R9→R6 / R7), and two bipolar transistors Q1 and Q2 with their bases and collectors grounded. The drain of the PMOS transistor is connected to resistors R6 and R7 via resistors R1 and R9. Resistor R6 is then connected to the emitter of Q2 via R8, while resistor R7 is directly connected to the emitter of Q1. The bases and collectors of both Q1 and Q2 are grounded, connected via V... BE With ΔV BE The proportional weighting achieves temperature compensation for the output reference voltage.

[0036] Further, in some embodiments of this application, the startup circuit includes a second PMOS transistor M12, a third PMOS transistor M13, a fourth PMOS transistor M14, a fifth PMOS transistor M15, a sixth PMOS transistor M21, a first NMOS transistor M16, a second NMOS transistor M17, a third NMOS transistor M18, a fourth NMOS transistor M19, a fifth NMOS transistor M20, and a first inverter; wherein, the second PMOS transistor M12, the third PMOS transistor M13, the fourth PMOS transistor M14, and the fifth PMOS transistor M15 are connected in parallel; the source of the second PMOS transistor M12 is connected to the power supply voltage; the drain of the fifth PMOS transistor M15 is connected to the drain of the second NMOS transistor M17; and the source of the second NMOS transistor M17 is grounded; the source of the sixth PMOS transistor M21 is connected to the power supply voltage; and the sixth PMOS transistor M20... The drain of transistor M21 is connected to the drain of the first NMOS transistor M16. The gate of the first NMOS transistor M16 is connected to its drain. The gate of the first NMOS transistor M16 is connected to the gate of the second NMOS transistor M17. The drain of the third NMOS transistor M18 is connected to the drain of the second NMOS transistor M17. The source of the third NMOS transistor M18 is grounded. The drain of the fourth NMOS transistor M19 is connected to the drain of the second NMOS transistor M17. The source of the fourth NMOS transistor M19 is grounded. The gate of the fifth NMOS transistor M20 is connected to the drain of the second NMOS transistor M17. The source of the fifth NMOS transistor M20 is grounded. The drain of the fifth NMOS transistor M20 is connected to the gate of the sixth PMOS transistor M21. The output of the first inverter is connected to the gate of the fourth NMOS transistor M19.

[0037] In other words, in this embodiment, the startup circuit consists of a parallel PMOS transistor group (M12-M15), NMOS transistors (M16-M20), and a single-stage inverter. Specifically, the sources of M12-M15 are all connected to VDD, and the drain of M15 is connected in series with the NMOS transistor M17. M16 and M17 form a current mirror to provide bias current for the inverter. The output of the inverter controls the on / off state of the startup signal through the NMOS switch M20. At the same time, the critical node voltage at the drain of M20 is fed back to the gate of the PMOS transistor M21. After power-on startup is completed, M21 completely turns off the parallel PMOS group to achieve efficient and rapid wake-up and complete suppression of static power consumption.

[0038] Further, in some embodiments of this application, the bias circuit includes a seventh PMOS transistor M8, an eighth PMOS transistor M9, a ninth PMOS transistor M25, a sixth NMOS transistor M10, a seventh NMOS transistor M11, an eighth NMOS transistor M26, a ninth NMOS transistor M27, a sixth resistor R0, a seventh resistor R14, an eighth resistor R15, a ninth resistor R16, and a third transistor Q0; wherein, the gate of the seventh PMOS transistor M8 is connected to the gate of the eighth PMOS transistor M9, the source of the seventh PMOS transistor M8 is connected to the source of the eighth PMOS transistor M9 and is connected to the power supply voltage, the gate of the seventh PMOS transistor M8 is shorted to the drain, the gate of the ninth PMOS transistor M25 is connected to the gates of the seventh PMOS transistor M8 and the eighth PMOS transistor M9, the drain and source of the ninth PMOS transistor M25 are connected to the power supply voltage, and the gate of the sixth NMOS transistor M10 is shorted to the gate of the seventh PMOS transistor M9. The gate of the NMOS transistor M11 is connected to the gate of the PMOS transistor M10. The drain of the sixth NMOS transistor M10 is connected to the drain of the seventh PMOS transistor M8. The source of the sixth NMOS transistor M10 is connected to the sixth resistor R0. The sixth resistor R0, the seventh resistor R14, the eighth resistor R15, and the ninth resistor R16 are connected in series. The ninth resistor R16 is grounded. The emitter of the third transistor Q0 is connected to the source of the seventh NMOS transistor M11. The base and collector of the third transistor Q0 are both grounded. The drain of the ninth NMOS transistor M27 is connected to the gate of the seventh NMOS transistor M11. The source of the ninth NMOS transistor M27 is grounded. The gate of the ninth NMOS transistor M27 is connected to the output terminal of the first inverter. The gate of the eighth NMOS transistor M26 is connected to the gate of the seventh NMOS transistor M11. The source and drain of the eighth NMOS transistor M26 are grounded.

[0039] In other words, in this embodiment, the bias circuit is composed of a bidirectional current mirror, a resistor voltage divider chain, and a transistor Q0: PMOS transistors M8 (gate and drain shorted), M9, and M25 cooperate with NMOS transistors M10 and M11 to form a self-biased main current mirror, providing a stable bias current for subsequent circuits; the resistor chain R0, R14, R15, and R16 are connected to ground to generate multi-level reference voltages; the emitter of transistor Q0 is connected to the source of the NMOS transistor to perform level correction and current extraction for the voltage divider node; at the same time, the controlled NMOS switches M26 and M27 respond to the inverter output signal to turn the bias path on or off, thereby realizing dynamic switching of the bias state.

[0040] Furthermore, in some embodiments of this application, the first operational amplifier circuit includes a tenth PMOS transistor M28, an eleventh PMOS transistor M4, a twelfth PMOS transistor M6, a thirteenth PMOS transistor M0, a fourteenth PMOS transistor M1, a tenth NMOS transistor M3, an eleventh NMOS transistor M2, a twelfth NMOS transistor M30, a thirteenth NMOS transistor M5, a tenth resistor R4, and a first capacitor C0;

[0041] In this configuration, the source of the tenth PMOS transistor M28 is connected to the power supply voltage, and the drain of the tenth PMOS transistor M28 is connected to the drain of the seventh PMOS transistor M8. The source of the eleventh PMOS transistor M4 is connected to the power supply voltage, and the drain of the eleventh PMOS transistor M4 is connected to the sources of the thirteenth PMOS transistor M0 and the fourteenth PMOS transistor M1. The drain of the thirteenth PMOS transistor M0 is connected to the drain of the tenth NMOS transistor M3. The source of the tenth NMOS transistor M3 is grounded, and the gate and drain of the tenth NMOS transistor M3 are shorted. The drain of the fourteenth PMOS transistor M1 is connected to the drain of the eleventh NMOS transistor M2. The source of the eleventh NMOS transistor M2 is grounded. The gates of the tenth NMOS transistor M3 and the eleventh NMOS transistor M2 are connected. The source of the twelfth PMOS transistor M6 is connected to the power supply voltage. The gate of the twelfth PMOS transistor M6 is connected to the gate of the eleventh PMOS transistor M4. The drain of the twelfth PMOS transistor M6 is connected to the drain of the thirteenth NMOS transistor M5. The source of the thirteenth NMOS transistor M5 is grounded. The drain of the twelfth NMOS transistor M30 is connected to the gate of the thirteenth NMOS transistor M5. The source of the twelfth NMOS transistor M30 is grounded. The gate of the twelfth NMOS transistor M30 is connected to the output terminal of the first inverter.

[0042] In addition, the tenth resistor R4 is connected in series with the first capacitor C0 and is connected across the eleventh NMOS transistor M2 and the thirteenth NMOS transistor M5. The thirteenth PMOS transistor M0 and the fourteenth PMOS transistor M1 are respectively connected to the third resistor R6 and the fourth resistor R7.

[0043] In other words, in this embodiment, the first operational amplifier adopts a differential input-single-ended output architecture, wherein M28 and M4 form an input stage differential pair, and M0 and M1 work together as load transistors of the differential pair; M3 and M2 form a current mirror load, and a compensation network consisting of R4 in series with C0 is connected across the output stage to ensure loop stability; the drain of the output transistor M5 is directly connected to the bandgap core resistor network R6 / R7 to achieve reliable clamping of the output potential.

[0044] Furthermore, in some embodiments of this application, the PSRR boost circuit includes a fifteenth PMOS transistor M29 and a sixteenth PMOS transistor M22; wherein, the source of the fifteenth PMOS transistor M29 is connected to the power supply voltage, the drain of the fifteenth PMOS transistor M29 is connected to the gate of the sixteenth PMOS transistor M22, the source of the sixteenth PMOS transistor M22 is connected to the first resistor R1, the drain of the sixteenth PMOS transistor M22 is grounded, and the gate of the sixteenth PMOS transistor M22 is connected to the first capacitor C0.

[0045] In other words, the PSRR boosting unit consists of two series-connected PMOS transistors M29 and M22: First, the source of M29 is directly connected to the power supply to initially isolate power supply noise; its drain output signal drives the gate of the next stage M22; the source of M22 is coupled to the reference network through the bandgap reference core resistor R1, and the drain is grounded, closing a local negative feedback loop, thereby further suppressing power supply ripple and improving the overall power supply rejection ratio.

[0046] Furthermore, in some embodiments of this application, the high-order curvature compensation circuit includes a second operational amplifier circuit, a seventeenth PMOS transistor M23, an eighteenth PMOS transistor M24, an eleventh resistor R10, a twelfth resistor R11, a thirteenth resistor R12, a fourteenth resistor R13, and a fourth transistor Q3.

[0047] In this configuration, the inverting input of the second operational amplifier circuit is connected to the first resistor R1, the non-inverting input of the second operational amplifier circuit is connected to the drain of the seventeenth PMOS transistor M23, the output of the second operational amplifier circuit is connected to the gates of the seventeenth PMOS transistor M23 and the eighteenth PMOS transistor M24, the sources of the seventeenth PMOS transistor M23 and the eighteenth PMOS transistor M24 are connected to the power supply voltage, the drain of the seventeenth PMOS transistor M23 is connected to the thirteenth resistor R12, the thirteenth resistor R12 is connected in series with the fourteenth resistor R13, the fourteenth resistor R13 is grounded, the emitter of the fourth transistor Q3 is connected to the drain of the eighteenth PMOS transistor M24, the base and collector of the fourth transistor Q3 are grounded, the eleventh resistor R10 is connected between the third resistor R6 and the emitter of the fourth transistor Q3, and the twelfth resistor R11 is connected between the fourth resistor R7 and the emitter of the fourth transistor Q3.

[0048] In other words, in this embodiment, the high-order curvature compensation unit is composed of a second operational amplifier, a PMOS current mirror (M23 / M24), a resistor network (R10~R13), and a temperature-sensitive branch (Q3 and R13 / R14). The second operational amplifier continuously compares the potential difference between the bandgap core voltage Vin and the compensation node, and drives its output to the PMOS mirror pair M23 / M24, thereby accurately injecting compensation current into the core resistor R11 / R12. At the same time, the temperature-dependent network composed of transistor Q3 and R13 and R14 will generate nonlinear voltage components with temperature changes, further correcting the curvature and improving the temperature linearity of the reference voltage.

[0049] It should be emphasized that, in order to make the present utility model solution, its principle and function clearer and more specific, the applicant, in conjunction with... Figures 1 to 8 The present invention will be further described in detail below:

[0050] The high-precision cryogenic drift bandgap reference circuit described in this embodiment includes a bandgap reference core circuit, a startup circuit, a bias circuit, a first operational amplifier circuit, a PSRR boost circuit, and a high-order curvature compensation circuit. The first operational amplifier circuit and the PSRR boost circuit directly act on the bandgap reference core circuit; the bias circuit connects both the first operational amplifier circuit and the bandgap reference core circuit; the startup circuit connects the bias circuit and the bandgap reference core circuit; and the high-order curvature compensation circuit is connected to the bandgap reference core circuit.

[0051] also, Figure 3 The demonstrated bandgap reference core circuit has the advantage over traditional voltage-mode bandgap reference circuits in that it eliminates the branch formed by a PMOS transistor current mirror. On one hand, this reduces power consumption; on the other hand, due to the channel length modulation effect of the MOS transistor, the temperature drift and error caused by MOS transistor mismatch are much greater than the impact of resistor mismatch. Figure 3 The structural mismatch shown is smaller.

[0052] The applicant will now analyze in detail the process of generating the reference voltage in this circuit.

[0053] The high-gain operational amplifier forms a feedback loop in the core circuit, clamping the input voltages at both ends to be equal. The ratio of the emitter junction area of ​​PNP transistors Q2 to Q1 is N:1, therefore:

[0054]

[0055] in,

[0056] Figure 3 In the middle, the resistance R6 = R7, I PTATCurrent flows through resistors R1, R6, and R7, generating a positive temperature coefficient voltage. This voltage is generated because the currents in branches R6 and R7 are equal. Therefore, the current flowing through R1 is 2I. PTAT Therefore, the voltage across R1 is The voltage across R7 is Therefore, the voltage with a positive temperature coefficient is the sum of the voltages across R1 and R7, which is...

[0057] Due to V BE It is a negative temperature coefficient voltage; therefore, a positive temperature coefficient voltage... When superimposed with the negative temperature coefficient voltage and after first-order temperature compensation, the output reference voltage is obtained as follows:

[0058]

[0059] When T = 300K To ensure symmetry in the layout design, N is generally set to 8. Simultaneously, to guarantee zero temperature, it is necessary to:

[0060]

[0061] and Therefore It is a constant that is independent of temperature;

[0062] At 300K,

[0063] By properly allocating the resistance values, a reference voltage V with zero temperature coefficient can be obtained. REF We set R1 = 78.85K, R7 = 30.90K, and R8 = 19.66K. It should be noted that the resistance values ​​here are slightly different from the design values. These resistance values ​​are obtained by fine-tuning after simulating the temperature curve. This also reflects the slight difference between the simulated design value and the design value. Through simulation, we strive to minimize the temperature coefficient.

[0064] Furthermore, Figure 4 The startup circuit shown is designed to prevent zero current transfer and the transistors from turning on properly when the power supply is applied, i.e., to avoid a metastable operating point. Adding the startup circuit ensures that the circuit operates normally after the power supply stabilizes. It should be noted that when the circuit is first powered on, V... BP It may be in a high-level state, in which case the circuit cannot start normally, V RE It is at a low level, so M is at this time 20 Cutoff, making M 18 The gate is high, so M 18 When the circuit is turned on, current flows through M.18 At this time, V BP When the voltage drops to low, the circuit is turned on and operates normally. After this, starting the circuit only consumes M... 12 The current in the nA range on the branch circuit is the working principle of the starting circuit.

[0065] Furthermore, Figure 5 The bias circuit shown is Type structure, M8~M 11 The symmetrical structure formed will M 11 M 11 The source voltage is clamped, so the sum of the voltage drops across the sixth resistor R0, the seventh resistor R14, the eighth resistor R15, and the ninth resistor R16 equals the voltage drop V across the third transistor Q0. BE Therefore, bias current

[0066] Furthermore, Figure 6 The first operational amplifier circuit shown is a crucial module in the bandgap reference circuit, decisively influencing the accuracy of the reference voltage output. When designing an amplifier, factors such as open-loop gain, input-output common-mode level, unity-gain bandwidth, and phase margin are typically considered. In the bandgap circuit, the op-amp primarily clamps the voltages of the two branches. Assuming the op-amp's open-loop gain is infinite, based on the virtual short and virtual open characteristics, we have V... IN =V IP Thus, ΔV with a positive temperature coefficient is obtained. BE However, in actual design, it is impossible to achieve an operational amplifier with infinite gain; the gain of a typical operational amplifier is generally less than 120dB. Besides its clamping function, which affects the accuracy of the reference output, the operational amplifier also has a significant impact on the power supply rejection ratio (PSRR).

[0067] Furthermore, it should be emphasized that this application uses a two-stage operational amplifier, which has a simple circuit structure but provides sufficient gain. Its principle is as follows:

[0068] The input stage amplifier circuit consists of M11, M12, M13, M16, and M7. M11 and M12 form a PMOS differential input pair, which can effectively suppress common-mode signal interference compared to single-ended input. M13 and M16 are current mirrors and active loads. M7 provides a constant bias current for the first stage. The output stage amplifier circuit consists of M8 and M14. M14 is a common-source amplifier, and M8 provides a constant bias current for it, while also serving as the output load for the second stage. The phase compensation circuit consists of R1 and C1. R1 and capacitor C1 are connected across the input and output of the second stage to form RC Miller compensation. M27, M28, and M30 are enable transistors used for simulation testing during transient startup of the overall circuit. When the circuit is operating normally, ENB is low and EN is high.

[0069] The total DC open-loop gain of the above op-amp is:

[0070] A0 = -g m11 g m14 (r o11 |r o13 )(r o14 |r o8 )

[0071] Frequency compensation is crucial when designing a two-stage operational amplifier. It is necessary to increase the gain of the operational amplifier while ensuring stability.

[0072]

[0073] To ensure stability, the secondary pole P2 must be located outside GBW. L These are parasitic capacitances related to the bandgap core circuit, typically in the fF range. Stability requirements can be met by properly distributing the bias currents between the two stages of the operational amplifier.

[0074] It is important to note that the bias voltage VBP of the aforementioned op-amp is provided by a bias current source, as shown in the diagram above. The bias circuit employs a self-biased current source structure to provide a constant current to the op-amp and the bandgap core circuitry. Its basic principle is as follows:

[0075] The symmetrical current mirror structure of M8 to M11 makes the drain points of M10 and M11 equal, which acts as a clamp at the input of the op-amp; let: R0 + R14 + R15 + R16 = Rs; therefore, the voltage VBE on the BJT is the voltage across Rs, hence: The required bias current can be obtained by adjusting the value of Rs.

[0076] The core of the above structure lies in the "active voltage regulation of the current mirror drain." Traditional solutions indirectly adjust the current by controlling the gate, but here a source follower is used to directly stabilize the drain voltage, which is equivalent to establishing a "voltage anchor point" at the critical node of noise coupling. Specifically, there are three mechanisms: First, the low output impedance characteristic of the source follower is like a small resistor connected in parallel between the current mirror drain and the power supply. The source of the PMOS source follower presents a low output impedance to ground. Typical values ​​range from 1 to 10 kΩ. Regardless of VDD fluctuations, the drain voltage V of the current mirror in the bandgap core circuit remains constant. d Forced to stabilize at V G,pmos -V THP Since it is independent of VDD, this significantly reduces power supply noise; secondly, there is a local negative feedback loop, which quickly compensates for drain voltage fluctuations; finally, there is active shunting of power supply noise, with high-frequency noise being bypassed to ground. This structure requires optimization of the PMOS size during design to ensure its transconductance gmp This maximizes the PSRR of the circuit. In summary, the core innovation of the above structure lies in dynamically transforming the high-impedance drain node of the current mirror into a low-impedance node. From a physical perspective, this means changing the output impedance R of the source follower... out In V d A parallel low-impedance path is established between VDD and the circuit to shunt power supply noise to ground. From a system perspective, this structure creates a local negative feedback loop that adaptively clamps the voltage, ensuring that VDD... d It is unrelated to VDD and becomes a "silent island" of power supply noise.

[0077] Furthermore, Figure 7 The PSRR boosting circuit shown uses a simple PMOS source follower structure, which is placed between the op-amp output and the bandgap core circuit, effectively improving the power supply rejection ratio (PSRR) of the circuit.

[0078] also, Figure 8 The main design concept of the high-order curvature compensation circuit shown is as follows:

[0079] Traditional first-order temperature compensation cannot eliminate V BE The high-order nonlinear term in V BE The relationship between temperature and temperature is as follows:

[0080]

[0081] Among them, V BG0 and V BE0 These are the PN junction voltage at 0K and the base-emitter voltage at T0, respectively. This is a temperature-independent process constant, typically taken as 4–5. α depends on the temperature characteristics of the current flowing through the BJT collector junction; when I… C When the current is PTAT, α = 1; I C When I is a zero temperature coefficient current, α = 0; when I C When the current is CTAT, α = -1. According to the above formula, the last term... It is the main source of nonlinearity. Its Taylor expansion is shown below:

[0082]

[0083] Observing the nonlinear terms after the above decomposition, we can see that they contain second-order and higher-order terms related to temperature. Therefore, it can be seen that V BE Linearization method, design of high-order curvature compensation circuit, directly cancels Obtain the linear temperature coefficient V BE .

[0084] It should be further noted that the operational amplifier used in the high-order curvature compensation circuit is the same two-stage operational amplifier as that used in the bandgap core circuit. REF The op-amp's inverting input is connected to the op-amp's output, which is connected to the gates of M23 and M24. The op-amp's non-inverting input is connected to the drain of M23, forming a negative feedback loop to ensure loop stability. Through the op-amp's clamping action, the drain voltage of M23 is kept equal to V. REF By adjusting resistors R12 and R13, a temperature-independent current I can be obtained. Furthermore, R12 and R13 are different types of resistors with opposite temperature coefficients, in order to obtain an even lower temperature coefficient current. This zero-temperature-coefficient current I is injected into Q3 via the PMOS current mirror, therefore:

[0085]

[0086] The current I injected into Q1 and Q2 PTAT It is directly proportional to temperature, therefore:

[0087]

[0088] Therefore, the voltage difference across the compensation resistors R10 / R11 is:

[0089]

[0090] The nonlinear compensation current flowing through R10 / R11 at this time is:

[0091]

[0092] After the nonlinear compensation current from R10 / R11 is injected into the core bandgap reference circuit, V REF The output voltage value is:

[0093]

[0094] To eliminate the nonlinear term, the resistance relationship needs to be set as follows:

[0095]

[0096] in, These are circuit parameters.

[0097] Theoretically, by setting the current flowing through M23 and M24 and the aforementioned resistor ratios, the nonlinear term can be perfectly eliminated, resulting in a reference voltage with zero temperature coefficient. However, due to the mismatch of the current mirror, the temperature coefficients of resistors R10, R11, R12, and R13, and various process errors (easily detected during simulation at process corners), the final voltage can only be reduced. REF The temperature coefficient is present, but it cannot be completely eliminated.

[0098] In summary, the high-precision, low-temperature drift bandgap reference circuit provided in this invention, through a startup circuit composed of parallel multi-stage PMOS / NMOS devices and a feedback inverter, can quickly start the core module under weak current conditions, ensuring the reliable entry of the bandgap circuit into the operating region. Furthermore, a specially designed bias network provides a stable and controllable bias current for the bandgap core and operational amplifier, meeting current requirements across a wide temperature and process angle range while effectively reducing the impact of process mismatch of each stage of the device on the reference voltage. Therefore, the high-precision, low-temperature drift bandgap reference circuit provided in this embodiment of the invention further improves the circuit's startup reliability and power supply rejection performance while ensuring an extremely low temperature coefficient. Moreover, by introducing high-order curvature compensation, a powerful startup circuit, a stable bias network, and a dedicated PSRR boost structure, it achieves a high-precision, low-temperature drift, wide operating voltage range, and strong anti-interference capability bandgap reference circuit.

Claims

1. A high-precision cryogenic drift bandgap reference circuit, characterized in that, It includes a bandgap reference core circuit, a startup circuit, a bias circuit, a first operational amplifier circuit, a PSRR boost circuit, and a high-order curvature compensation circuit; wherein, the startup circuit is used to get the circuit out of degeneracy; the bandgap reference core circuit is used to generate a reference voltage with zero temperature coefficient; the bias circuit is used to provide bias current to the circuit; the first operational amplifier circuit is used to clamp the potential of the bandgap core module; the PSRR boost circuit is used to improve the power supply rejection ratio of the overall circuit; and the high-order curvature compensation circuit is used to reduce the temperature coefficient of the bandgap reference core circuit. The first operational amplifier circuit and the PSRR boost circuit are both connected to the bandgap reference core circuit. The bias circuit is connected to the first operational amplifier circuit and the bandgap reference core circuit. The startup circuit is connected to the bias circuit and the bandgap reference core circuit. The higher-order curvature compensation circuit is connected to the bandgap reference core circuit.

2. The high-precision low-temperature drift bandgap reference circuit according to claim 1, characterized in that, The core circuit of the bandgap reference includes a first PMOS transistor, a first resistor R1, a second resistor R9, a third resistor R6, a fourth resistor R7, a fifth resistor R8, a first transistor Q1, and a second transistor Q2. The source of the first PMOS transistor is connected to the power supply voltage. The drain of the first PMOS transistor is connected to the first resistor R1. The first resistor R1 is connected to the second resistor R9. The third resistor R6 and the fourth resistor R7 are both connected to the second resistor R9. The third resistor R6 is connected to the fifth resistor R8. The fifth resistor R8 is connected to the emitter of the second transistor Q2. The base and collector of the second transistor Q2 are both connected to ground. The fourth resistor R7 is connected to the emitter of the first transistor Q1. The base and collector of the first transistor Q1 are both connected to ground.

3. The high-precision low-temperature drift bandgap reference circuit according to claim 2, characterized in that, The startup circuit includes a second PMOS transistor M12, a third PMOS transistor M13, a fourth PMOS transistor M14, a fifth PMOS transistor M15, a sixth PMOS transistor M21, a first NMOS transistor M16, a second NMOS transistor M17, a third NMOS transistor M18, a fourth NMOS transistor M19, a fifth NMOS transistor M20, and a first inverter; The second PMOS transistor M12, the third PMOS transistor M13, the fourth PMOS transistor M14, and the fifth PMOS transistor M15 are connected in parallel. The source of the second PMOS transistor M12 is connected to the power supply voltage, and the drain of the fifth PMOS transistor M15 is connected to the drain of the second NMOS transistor M17. The source of the second NMOS transistor M17 is grounded. The source of the sixth PMOS transistor M21 is connected to the power supply voltage, and the drain of the sixth PMOS transistor M21 is connected to the drain of the first NMOS transistor M16. The gate of the first NMOS transistor M16 is connected to its drain, and the gate of the first NMOS transistor M16 is connected to the drain of the second NMOS transistor M17. The gate of the first NMOS transistor M17 is connected to the second NMOS transistor M18, the drain of the third NMOS transistor M18 is connected to the drain of the second NMOS transistor M17, and the source of the third NMOS transistor M18 is grounded; the drain of the fourth NMOS transistor M19 is connected to the drain of the second NMOS transistor M17, and the source of the fourth NMOS transistor M19 is grounded; the gate of the fifth NMOS transistor M20 is connected to the drain of the second NMOS transistor M17, the source of the fifth NMOS transistor M20 is grounded, the drain of the fifth NMOS transistor M20 is connected to the gate of the sixth PMOS transistor M21, and the output of the first inverter is connected to the gate of the fourth NMOS transistor M19.

4. The high-precision low-temperature drift bandgap reference circuit according to claim 3, characterized in that, The bias circuit includes a seventh PMOS transistor M8, an eighth PMOS transistor M9, a ninth PMOS transistor M25, a sixth NMOS transistor M10, a seventh NMOS transistor M11, an eighth NMOS transistor M26, a ninth NMOS transistor M27, a sixth resistor R0, a seventh resistor R14, an eighth resistor R15, a ninth resistor R16, and a third transistor Q0. The gate of the seventh PMOS transistor M8 is connected to the gate of the eighth PMOS transistor M9. The source of the seventh PMOS transistor M8 is connected to the source of the eighth PMOS transistor M9, and the gate and drain of the seventh PMOS transistor M8 are shorted. The gate of the ninth PMOS transistor M25 is connected to the gates of the seventh PMOS transistor M8 and the eighth PMOS transistor M9. The drain and source of the ninth PMOS transistor M25 are connected to the power supply voltage. The gate of the sixth NMOS transistor M10 is connected to the gate of the seventh NMOS transistor M11. The drain of the sixth NMOS transistor M10 is connected to the drain of the seventh PMOS transistor M8. The source of the sixth NMOS transistor M10 is connected to the sixth resistor. The resistors R0, R14, R15, and R16 are connected in series. The ninth resistor R16 is grounded. The emitter of the third transistor Q0 is connected to the source of the seventh NMOS transistor M11. The base and collector of the third transistor Q0 are both grounded. The drain of the ninth NMOS transistor M27 is connected to the gate of the seventh NMOS transistor M11. The source of the ninth NMOS transistor M27 is grounded. The gate of the ninth NMOS transistor M27 is connected to the output of the first inverter. The gate of the eighth NMOS transistor M26 is connected to the gate of the seventh NMOS transistor M11. The source and drain of the eighth NMOS transistor M26 are grounded.

5. The high-precision low-temperature drift bandgap reference circuit according to claim 4, characterized in that, The first operational amplifier circuit includes the tenth PMOS transistor M28, the eleventh PMOS transistor M4, the twelfth PMOS transistor M6, the thirteenth PMOS transistor M0, the fourteenth PMOS transistor M1, the tenth NMOS transistor M3, the eleventh NMOS transistor M2, the twelfth NMOS transistor M30, the thirteenth NMOS transistor M5, the tenth resistor R4, and the first capacitor C0. The source of the tenth PMOS transistor M28 is connected to the power supply voltage. The drain of the tenth PMOS transistor M28 is connected to the drain of the seventh PMOS transistor M8. The source of the eleventh PMOS transistor M4 is connected to the power supply voltage. The drain of the eleventh PMOS transistor M4 is connected to the sources of the thirteenth PMOS transistor M0 and the fourteenth PMOS transistor M1. The drain of the thirteenth PMOS transistor M0 is connected to the drain of the tenth NMOS transistor M3. The source of the tenth NMOS transistor M3 is grounded. The gate and drain of the tenth NMOS transistor M3 are shorted. The drain of the fourteenth PMOS transistor M1 is connected to the drain of the eleventh NMOS transistor M2. The source of NMOS transistor M2 is grounded. The gates of the tenth NMOS transistor M3 and the eleventh NMOS transistor M2 are connected. The source of the twelfth PMOS transistor M6 is connected to the power supply voltage. The gate of the twelfth PMOS transistor M6 is connected to the gate of the eleventh PMOS transistor M4. The drain of the twelfth PMOS transistor M6 is connected to the drain of the thirteenth NMOS transistor M5. The source of the thirteenth NMOS transistor M5 is grounded. The drain of the twelfth NMOS transistor M30 is connected to the gate of the thirteenth NMOS transistor M5. The source of the twelfth NMOS transistor M30 is grounded. The gate of the twelfth NMOS transistor M30 is connected to the output terminal of the first inverter. The tenth resistor R4 is connected in series with the first capacitor C0 and is connected across the eleventh NMOS transistor M2 and the thirteenth NMOS transistor M5. The thirteenth PMOS transistor M0 and the fourteenth PMOS transistor M1 are respectively connected to the third resistor R6 and the fourth resistor R7.

6. The high-precision low-temperature drift bandgap reference circuit according to claim 5, characterized in that, The PSRR boost circuit includes a fifteenth PMOS transistor M29 and a sixteenth PMOS transistor M22; The source of the fifteenth PMOS transistor M29 is connected to the power supply voltage, the drain of the fifteenth PMOS transistor M29 is connected to the gate of the sixteenth PMOS transistor M22, the source of the sixteenth PMOS transistor M22 is connected to the first resistor R1, the drain of the sixteenth PMOS transistor M22 is grounded, and the gate of the sixteenth PMOS transistor M22 is connected to the first capacitor C0.

7. The high-precision low-temperature drift bandgap reference circuit according to claim 6, characterized in that, The high-order curvature compensation circuit includes a second operational amplifier circuit, a seventeenth PMOS transistor M23, an eighteenth PMOS transistor M24, an eleventh resistor R10, a twelfth resistor R11, a thirteenth resistor R12, a fourteenth resistor R13, and a fourth transistor Q3. The inverting input of the second operational amplifier circuit is connected to the first resistor R1. The non-inverting input of the second operational amplifier circuit is connected to the drain of the seventeenth PMOS transistor M23. The output of the second operational amplifier circuit is connected to the gates of the seventeenth PMOS transistor M23 and the eighteenth PMOS transistor M24. The sources of the seventeenth PMOS transistor M23 and the eighteenth PMOS transistor M24 are connected to the power supply voltage. The drain of the seventeenth PMOS transistor M23 is connected to the thirteenth resistor R12. The thirteenth resistor R12 is connected in series with the fourteenth resistor R13. The fourteenth resistor R13 is grounded. The emitter of the fourth transistor Q3 is connected to the drain of the eighteenth PMOS transistor M24. The base and collector of the fourth transistor Q3 are grounded. The eleventh resistor R10 is connected between the third resistor R6 and the emitter of the fourth transistor Q3. The twelfth resistor R11 is connected between the fourth resistor R7 and the emitter of the fourth transistor Q3.

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