Regulator circuit for eliminating power-on oscillation and vehicle

Abstract

The application discloses a voltage stabilizing circuit and a vehicle for eliminating power-on oscillation. The voltage stabilizing circuit comprises a soft start circuit, an error amplifier, a power field effect transistor, a power-on oscillation eliminating circuit and a power-on output port. In the embodiment of the application, the transient enhancement circuit is disabled at the initial stage of starting, and is activated when the output voltage approaches the target value, which can reduce the risk of oscillation in the power-on process of the voltage stabilizing circuit, while the optimization capability of load transient is retained, and the loop is not greatly affected, so that the oscillation in the power-on process disappears, thereby avoiding the uncertainty influence of the power-on oscillation on the circuit system.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a voltage regulator circuit and a vehicle for eliminating power-on oscillations. Background Technology

[0002] In new energy vehicles, the main components consist of an electric drive system, a power supply system, and an electronic auxiliary system, with the power supply system being the most crucial. With the development of vehicle electrification and intelligence, voltage regulator circuits are becoming increasingly important in on-board power supply design, especially in low-voltage applications such as on-board power supplies, in-vehicle infotainment systems, body control, and autonomous driving. A low dropout regulator (LDO) is a low-dropout linear regulator primarily used to control the output voltage of a circuit, maintaining it at a constant value. Its core working principle is to adjust the output voltage through a feedback loop, ensuring that the output voltage remains at the set value even when the load changes. With continuous research on LDO voltage regulator circuits, various circuits to improve LDO performance have emerged. For example, compensation circuits have been developed to improve the loop stability of LDO circuits; protection circuits have been invented to protect LDOs from damage; and transient enhancement circuits have been designed to improve the transient response of LDOs. LDOs with transient enhancement circuits significantly reduce overshoot spikes and response time when the load changes. While introducing transient boost circuits into traditional LDOs can optimize the transient response speed of the load, it has some drawbacks. For example, during power-up, a rapid voltage rise may be mistakenly identified by the transient boost circuit as a sudden load change, causing it to activate. This results in the circuit's output switching on and off repeatedly, ultimately leading to output voltage oscillations and affecting system reliability. To address this issue, the sensitivity of the transient boost circuit is typically adjusted to weaken its role in the loop. This significantly improves the oscillation problem, but it also degrades the transient characteristics. Changing the output capacitor and adjusting the main loop can also provide improvement, but the loop stability of the main loop remains to be discussed. Utility Model Content

[0003] This application provides a voltage regulator circuit and vehicle for eliminating power-on oscillations, solving the technical problem that current voltage regulator circuits are unable to eliminate the impact of oscillations during power-on on system reliability.

[0004] This application provides a voltage regulator circuit for eliminating power-on oscillations, including a soft-start circuit, an error amplifier, a power MOSFET M1, a power-on oscillation elimination circuit, and a power-on output port;

[0005] The error amplifier has a negative input terminal, a positive input terminal, and an output terminal. The output terminal of the soft-start circuit outputs a supply voltage Vref. The soft-start circuit is connected to the negative input terminal of the amplifier. The output terminal of the amplifier is connected to the gate of the power MOSFET M1. The source of the power MOSFET M1 is connected to the input voltage VIN. The drain of the power MOSFET M1 is connected to the positive input terminal of the amplifier and the power-on output port. The power-on output port outputs a power-on voltage VOUT.

[0006] The power-on oscillation elimination circuit takes the supply voltage Vref and the reference signal voltage as inputs, and its output is connected to the gate of the power MOSFET M1. When the supply voltage Vref is less than the reference signal voltage, the power-on oscillation elimination circuit outputs a high voltage to control the power MOSFET M1 to turn off, and the power-on voltage VOUT output by the power-on output port is 0V. When the supply voltage Vref is greater than or equal to the reference signal voltage, the power-on oscillation elimination circuit turns off, the power MOSFET M1 turns on, and the power-on voltage VOUT output by the power-on output port is equal to the input voltage VIN.

[0007] Furthermore, the input voltage VIN is equal to the supply voltage Vref, and the source of the power MOSFET M1 is connected to the output of the soft-start circuit.

[0008] Furthermore, the voltage regulator circuit for eliminating power-on oscillation also includes an internal grounding circuit, the first end of which is connected to the drain of the power MOSFET M1, and the second end of which is grounded.

[0009] Furthermore, the internal grounding circuit includes a first voltage divider resistor R1 and a second voltage divider resistor R2 connected in series, and the connection point of the first voltage divider resistor R1 and the second voltage divider resistor R2 is the internal grounding terminal ADJ.

[0010] Furthermore, the voltage regulator circuit for eliminating power-on oscillations also includes a bandgap reference circuit. The soft-start circuit is connected to the negative input terminal of the amplifier through the bandgap reference circuit, and the soft-start circuit is connected to the internal ground terminal ADJ.

[0011] Furthermore, the reference signal voltage includes a first reference signal Vref1 and a second reference signal Vref2. The circuit for eliminating power-on oscillation includes a switch control module and a voltage regulation output module. The switch control module generates a first switch signal ENH and a second switch signal ENL based on the first reference signal Vref1 and the supply voltage Vref. The voltage regulation output module is connected to the switch control module. The voltage regulation output module controls the voltage regulation output module to turn on and off based on the first switch signal ENH and the second switch signal ENL. When the voltage regulation output module is on, it outputs the input voltage VIN based on the second reference signal Vref2 and the supply voltage Vref.

[0012] Furthermore, the switch control module includes a first comparator COMP1, a first inverter NOT1, and a second inverter NOT2. The positive input terminal of the first comparator COMP1 receives the supply voltage Vref, and the negative input terminal of the first comparator COMP1 receives the first reference signal Vref1. The output terminal of the first comparator COMP1 is connected in series with the first inverter NOT1 and the second inverter NOT2. The first inverter NOT1 outputs the first switch signal ENH, and the second inverter NOT2 outputs the second switch signal ENL.

[0013] Furthermore, the voltage regulation output module includes a second comparator COMP2, a first P-channel MOSFET MP1, a second P-channel MOSFET MP2, a third P-channel MOSFET MP3, a first N-channel MOSFET NM1, and a second N-channel MOSFET NM2. The positive input terminal of the second comparator COMP2 receives the supply voltage Vref, and the negative input terminal receives the second reference signal Vref2. The enable terminal of the second comparator COMP2 is connected to the first switch signal ENH and the second switch signal ENL. The second comparator COMP2 operates when the first switch signal ENH is high and the second switch signal ENL is low, and is turned off when the first switch signal ENH is low and the second switch signal ENL is high. The output terminal of the second comparator COMP2 is connected to the gate of the first P-channel MOSFET MP1. The source of MP1 is connected to the power supply VDD. The drain of the first P-channel MOSFET MP1 is connected to the drain of the first N-channel MOSFET NM1. The gate and drain of the first N-channel MOSFET NM1 are interconnected to form a current mirror. The gate of the first N-channel MOSFET NM1 is connected to the gate of the second N-channel MOSFET NM2. The source of the first N-channel MOSFET NM1 is connected to the source of the second N-channel MOSFET NM2. The drain of the second N-channel MOSFET NM2 is connected to the drain of the second P-channel MOSFET MP2. The gate and drain of the second P-channel MOSFET MP2 are interconnected. The gate of the second P-channel MOSFET MP2 is connected to the gate of the third P-channel MOSFET MP3. The sources of the second P-channel MOSFET MP2 and the third P-channel MOSFET MP3 are both connected to the input voltage VIN. The drain of the third P-channel MOSFET MP3 is connected to the gate of the power MOSFET M1.

[0014] Furthermore, the voltage regulator circuit for eliminating power-on oscillations also includes a transient enhancement circuit and / or an overcurrent protection circuit, wherein the transient enhancement circuit and / or the overcurrent protection circuit are connected to the gate of the power MOSFET M1.

[0015] This application also provides a vehicle that includes a power supply system, the power supply system including a voltage regulator circuit for eliminating power-on oscillations as described in any of the preceding claims.

[0016] The voltage regulator circuit and vehicle provided in this application embodiment for eliminating power-on oscillation disable the transient enhancement circuit during the initial startup phase and activate it again when the output voltage approaches the target value. This reduces the risk of oscillation during the power-on process of the voltage regulator circuit, while also retaining the optimization capability of load transients. It does not have a significant impact on the loop, thus eliminating the oscillation during the power-on process and avoiding the uncertainty brought to the circuit system by power-on oscillation. Attached Figure Description

[0017] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0018] Figure 1 This is a schematic diagram of the voltage regulator circuit for eliminating power-on oscillations provided in an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of the structure of the circuit for eliminating power-on oscillation provided in an embodiment of this application.

[0020] Figure 3 A comparison diagram of power-on waveforms provided for embodiments of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0022] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0023] For details, please refer to Figure 1 This application provides a voltage regulator circuit for eliminating power-on oscillations. The voltage regulator circuit for eliminating power-on oscillations includes a soft-start circuit, an error amplifier, a power MOSFET M1, a power-on oscillation elimination circuit, and a power-on output port.

[0024] The error amplifier has a negative input terminal, a positive input terminal, and an output terminal. The output terminal of the soft-start circuit outputs a supply voltage Vref. The soft-start circuit is connected to the negative input terminal of the amplifier. The output terminal of the amplifier is connected to the gate of the power MOSFET M1. The source of the power MOSFET M1 is connected to the input voltage VIN. The drain of the power MOSFET M1 is connected to the positive input terminal of the amplifier and the power-on output port. The power-on output port outputs a power-on voltage VOUT.

[0025] The power-on oscillation elimination circuit takes the supply voltage Vref and the reference signal voltage as inputs, and its output is connected to the gate of the power MOSFET M1. When the supply voltage Vref is less than the reference signal voltage, the power-on oscillation elimination circuit outputs a high voltage to control the power MOSFET M1 to turn off, and the power-on voltage VOUT output by the power-on output port is 0V. When the supply voltage Vref is equal to the reference signal voltage, the power-on oscillation elimination circuit turns off, causing the gate voltage of the power MOSFET M1 to decrease and turn on the power MOSFET M1. When the supply voltage Vref is greater than or equal to the reference signal voltage, the power-on oscillation elimination circuit turns off, the power MOSFET M1 turns on, and the power-on voltage VOUT output by the power-on output port is equal to the input voltage VIN.

[0026] Furthermore, the input voltage VIN is equal to the supply voltage Vref, and the source of the power MOSFET M1 is connected to the output of the soft-start circuit.

[0027] Please see Figure 1 The voltage regulator circuit for eliminating power-on oscillations also includes an internal grounding circuit. The first terminal of the internal grounding circuit is connected to the drain of the power field-effect transistor M1, and the second terminal of the internal grounding circuit is grounded.

[0028] Please see Figure 1 The internal grounding circuit includes a first voltage divider resistor R1 and a second voltage divider resistor R2 connected in series. The connection point of the first voltage divider resistor R1 and the second voltage divider resistor R2 is the internal grounding terminal ADJ.

[0029] Please see Figure 1 The voltage regulator circuit for eliminating power-on oscillations also includes a bandgap reference circuit. The soft-start circuit is connected to the negative input terminal of the amplifier through the bandgap reference circuit, and the soft-start circuit is connected to the internal ground terminal ADJ.

[0030] Please see Figure 2The reference signal voltage includes a first reference signal Vref1 and a second reference signal Vref2. The power-on oscillation elimination circuit includes a switch control module and a voltage regulation output module. The switch control module generates a first switch signal ENH and a second switch signal ENL based on the first reference signal Vref1 and the supply voltage Vref. The voltage regulation output module is connected to the switch control module. The voltage regulation output module controls the voltage regulation output module to turn on and off based on the first switch signal ENH and the second switch signal ENL. When the voltage regulation output module is on, it outputs the input voltage VIN based on the second reference signal Vref2 and the supply voltage Vref.

[0031] Please see Figure 2 The switch control module includes a first comparator COMP1, a first inverter NOT1, and a second inverter NOT2. The positive input terminal of the first comparator COMP1 receives the supply voltage Vref, and the negative input terminal of the first comparator COMP1 receives the first reference signal Vref1. The output terminal of the first comparator COMP1 is connected in series with the first inverter NOT1 and the second inverter NOT2. The first inverter NOT1 outputs the first switch signal ENH, and the second inverter NOT2 outputs the second switch signal ENL.

[0032] Please see Figure 2The voltage regulation output module includes a second comparator COMP2, a first P-channel MOSFET MP1, a second P-channel MOSFET MP2, a third P-channel MOSFET MP3, a first N-channel MOSFET NM1, and a second N-channel MOSFET NM2. The positive input terminal of the second comparator COMP2 receives the supply voltage Vref, and the negative input terminal receives the second reference signal Vref2. The enable terminal of the second comparator COMP2 is connected to the first switch signal ENH and the second switch signal ENL. When the first switch signal ENH is high and... The second comparator COMP2 operates when the second switch signal ENL is low, and shuts down when the first switch signal ENH is low and the second switch signal ENL is high. The output of the second comparator COMP2 is connected to the gate of the first P-channel MOSFET MP1. The source of the first P-channel MOSFET MP1 is connected to the power supply VDD. The drain of the first P-channel MOSFET MP1 is connected to the drain of the first N-channel MOSFET NM1. The gate and drain of the first N-channel MOSFET NM1 are interconnected to form a current mirror. The gate of the first N-channel MOSFET NM1 is connected to the gate of the second N-channel MOSFET NM2, and the source of the first N-channel MOSFET NM1 is connected to the source of the second N-channel MOSFET NM2. Both the sources of the first N-channel MOSFET NM1 and the second N-channel MOSFET NM2 are connected to the internal ground terminal ADJ, replicating the current to the second N-channel MOSFET NM2. The width-to-length ratio of the first N-channel MOSFET NM1 to the second N-channel MOSFET NM2 is 1:2. The drain of the second N-channel MOSFET NM2 is connected to the second P-channel MOSFET MP2. The drain of the second P-channel MOSFET MP2 is interconnected with the gate of the third P-channel MOSFET MP3. The gate of the second P-channel MOSFET MP2 is connected to the gate of the third P-channel MOSFET MP3, and the current is replicated to the third P-channel MOSFET MP3. The width-to-length ratio of the second P-channel MOSFET MP2 to the third P-channel MOSFET MP3 is 1:2. The source of the second P-channel MOSFET MP2 and the source of the third P-channel MOSFET MP3 are both connected to the input voltage VIN. The drain of the third P-channel MOSFET MP3 is connected to the gate of the power MOSFET M1.

[0033] Please see Figure 1 The voltage regulator circuit for eliminating power-on oscillations further includes a transient enhancement circuit and / or an overcurrent protection circuit, wherein the transient enhancement circuit and / or the overcurrent protection circuit are connected to the gate of the power MOSFET M1.

[0034] Understandably, the transient enhancement circuitry can cause this voltage to oscillate. For example... Figure 3 As shown in signal A, oscillations occur below 4V during the Vref voltage rise process. Preferably, both the first reference signal Vref1 and the second reference signal Vref2 are 4V. The basic idea of ​​this application is to eliminate the power-on oscillation circuit when Vref is less than 4V. Figure 1 When the gate voltage of M1 is VIN, M1 is off, and VOUT is 0V. When Vref is greater than 4V, the power-on oscillation elimination circuit is no longer working, and VOUT will follow Vref to establish a voltage, thus avoiding oscillation below 4V.

[0035] The specific steps are as follows: Figure 2 As shown, when Vref is less than 4V, the output of the first comparator COMP1 is low. After passing through the first inverter NOT1, ENH becomes high, and after passing through the second inverter NOT2, ENL becomes low. ENH being high and ENL being low indicates that the second comparator COMP2 is working; otherwise, it is not working. At this time, the second comparator COMP2 is working. Since Vref is less than 4V, the output point A of the second comparator COMP2 is low, so point B is high. At this time, point C is low, eliminating the conduction of MP3 in the power MOSFET M1, which outputs a high level VIN to the gate. The Gate signal is high. When the Gate signal is high (VIN), Figure 1 When the gate voltage of M1 is VIN, and M1 (PMOS) is turned off, VOUT is 0V, which shuts down the output of the power-on oscillation elimination circuit and shields the oscillation signal.

[0036] When Vref rises above 4V, COMP1 outputs a high level, ENH is low, and ENL is high. At this time, COMP2 is turned off, and its output is high (internal enable control; COMP2 is high when not in operation). Therefore, point A is high, point B is low, and point C is high. The MP3 circuit, which eliminates power-on oscillation, is turned off and no longer outputs VIN to the gate of power MOSFET M1. The gate signal is no longer affected by the power-on oscillation elimination circuit and will instead follow the... Figure 1 The output of the error amplifier changes accordingly. As Vref rises, the Gate signal goes low at the moment MP3 of the power-on oscillation elimination circuit turns off, causing M1 (PMOS) to turn on, making VOUT = VIN. This preserves the optimization capability for load transients and does not have a significant impact on the loop. When the circuit is working normally, VOUT = Vref, and the error amplifier output Vref - VIN = 0, keeping M1 on. VOUT will establish a voltage with a Vref greater than 4V, thus eliminating the oscillation phenomenon.

[0037] like Figure 3 As shown, signal A is the abnormal oscillation waveform that occurs during power-on, and signal B is the power-on waveform after applying this application. It can be seen that the abnormal waveform has disappeared.

[0038] This application also provides a vehicle that includes a power supply system, the power supply system including a voltage regulator circuit for eliminating power-on oscillations as described in any of the preceding claims.

[0039] The voltage regulator circuit and vehicle provided in this application embodiment for eliminating power-on oscillation disable the transient enhancement circuit during the initial startup phase and activate it again when the output voltage approaches the target value. This reduces the risk of oscillation during the power-on process of the voltage regulator circuit, while also retaining the optimization capability of load transients. It does not have a significant impact on the loop, thus eliminating the oscillation during the power-on process and avoiding the uncertainty brought to the circuit system by power-on oscillation.

[0040] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0041] The above provides a detailed description of a voltage regulator circuit and vehicle for eliminating power-on oscillations provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A voltage regulator circuit for eliminating power-on oscillation, characterized in that, include: Soft-start circuit, error amplifier, power MOSFET (M1), power-on oscillation suppression circuit and power-on output port; The error amplifier has a negative input terminal, a positive input terminal, and an output terminal. The output terminal of the soft-start circuit outputs the supply voltage (Vref) and is connected to the negative input terminal of the amplifier. The output terminal of the amplifier is connected to the gate of the power MOSFET (M1). The source input voltage (VIN) of the power MOSFET (M1) is connected to the source input terminal. The drain of the power MOSFET (M1) is connected to the positive input terminal of the amplifier and the power-on output port. The power-on output port outputs the power-on voltage (VOUT). The power-on oscillation elimination circuit receives the supply voltage (Vref) and the reference signal voltage as inputs, and its output is connected to the gate of the power MOSFET (M1). When the supply voltage (Vref) is less than the reference signal voltage, the power-on oscillation elimination circuit outputs a high voltage to control the power MOSFET (M1) to turn off, and the power-on voltage (VOUT) output from the power-on output port is 0V. When the supply voltage (Vref) is greater than or equal to the reference signal voltage, the power-on oscillation elimination circuit turns off, the power MOSFET (M1) turns on, and the power-on voltage (VOUT) output from the power-on output port is equal to the input voltage (VIN).

2. The voltage regulator circuit for eliminating power-on oscillation as described in claim 1, characterized in that, The input voltage (VIN) is equal to the supply voltage (Vref), and the source of the power MOSFET (M1) is connected to the output of the soft-start circuit.

3. The voltage regulator circuit for eliminating power-on oscillation as described in claim 1, characterized in that, The voltage regulator circuit for eliminating power-on oscillations also includes an internal grounding circuit. The first terminal of the internal grounding circuit is connected to the drain of the power MOSFET (M1), and the second terminal of the internal grounding circuit is grounded.

4. The voltage regulator circuit for eliminating power-on oscillation as described in claim 3, characterized in that, The internal grounding circuit includes a first voltage divider resistor (R1) and a second voltage divider resistor (R2) connected in series. The connection point of the first voltage divider resistor (R1) and the second voltage divider resistor (R2) is the internal grounding terminal (ADJ).

5. The voltage regulator circuit for eliminating power-on oscillation as described in claim 1, characterized in that, The voltage regulator circuit for eliminating power-on oscillations also includes a bandgap reference circuit. The soft-start circuit is connected to the negative input terminal of the amplifier through the bandgap reference circuit, and the soft-start circuit is connected to the internal ground terminal (ADJ).

6. The voltage regulator circuit for eliminating power-on oscillation as described in claim 1, characterized in that, The reference signal voltage includes a first reference signal (Vref1) and a second reference signal (Vref2). The power-on oscillation elimination circuit includes a switch control module and a voltage regulation output module. The switch control module generates a first switch signal (ENH) and a second switch signal (ENL) based on the first reference signal (Vref1) and the supply voltage (Vref). The voltage regulation output module is connected to the switch control module. The voltage regulation output module controls the voltage regulation output module to turn on and off based on the first switch signal (ENH) and the second switch signal (ENL). When the voltage regulation output module is on, it outputs the input voltage (VIN) based on the second reference signal (Vref2) and the supply voltage (Vref).

7. The voltage regulator circuit for eliminating power-on oscillation as described in claim 6, characterized in that, The switch control module includes a first comparator (COMP1), a first inverter (NOT1), and a second inverter (NOT2). The positive input terminal of the first comparator (COMP1) receives the supply voltage (Vref), and the negative input terminal of the first comparator (COMP1) receives the first reference signal (Vref1). The output terminal of the first comparator (COMP1) is connected in series with the first inverter (NOT1) and the second inverter (NOT2). The first inverter (NOT1) outputs the first switch signal (ENH), and the second inverter (NOT2) outputs the second switch signal (ENL).

8. The voltage regulator circuit for eliminating power-on oscillation as described in claim 7, characterized in that, The voltage regulation output module includes a second comparator (COMP2), a first P-channel MOSFET (MP1), a second P-channel MOSFET (MP2), a third P-channel MOSFET (MP3), a first N-channel MOSFET (NM1), and a second N-channel MOSFET (NM2). The positive input terminal of the second comparator (COMP2) receives the supply voltage (Vref), and the negative input terminal receives the second reference signal (Vref2). The enable terminal of the second comparator (COMP2) is connected to the first switch signal (ENH) and the second switch signal (ENL). The second comparator (COMP2) operates when the first switch signal (ENH) is high and the second switch signal (ENL) is low, and is turned off when the first switch signal (ENH) is low and the second switch signal (ENL) is high. The output terminal of the second comparator (COMP2) is connected to the gate of the first P-channel MOSFET (MP1). The source of the first P-channel MOSFET (MP1) is connected to the power supply VDD. The drain of the first P-channel MOSFET (MP1) is connected to the drain of the first N-channel MOSFET (NM1). The gate and drain of the first N-channel MOSFET (NM1) are interconnected to form a current mirror. The gate of the first N-channel MOSFET (NM1) is connected to the gate of the second N-channel MOSFET (NM2). The source of the first N-channel MOSFET (NM1) is connected to the source of the second N-channel MOSFET (NM2). The drain of the second N-channel MOSFET (NM2) is connected to the source of the second N-channel MOSFET (NM2). The gate of the second P-channel MOSFET (MP2) is connected to the drain of the second P-channel MOSFET (MP2), the gate and drain of the second P-channel MOSFET (MP2) are interconnected, the gate of the second P-channel MOSFET (MP2) is connected to the gate of the third P-channel MOSFET (MP3), the source of the second P-channel MOSFET (MP2) and the source of the third P-channel MOSFET (MP3) are both connected to the input voltage (VIN), and the drain of the third P-channel MOSFET (MP3) is connected to the gate of the power MOSFET (M1).

9. The voltage regulator circuit for eliminating power-on oscillation as described in claim 1, characterized in that, The voltage regulator circuit for eliminating power-on oscillations also includes a transient enhancement circuit and / or an overcurrent protection circuit, wherein the transient enhancement circuit and / or the overcurrent protection circuit are connected to the gate of the power MOSFET (M1).

10. A vehicle, characterized in that, The vehicle includes a power system, which includes a voltage regulator circuit for eliminating power-on oscillations as described in any one of claims 1 to 9.

Images