A circuit for preventing output voltage jitter

Abstract

The application discloses an output voltage jitter prevention circuit, and relates to the technical field of electronic circuits. The circuit comprises a comparison module, a swing rate enhancement module and an output module. The comparison module is connected with the swing rate enhancement module and the output module, and the swing rate enhancement module is connected with the output module. The comparison module is used for starting the swing rate enhancement module. The swing rate enhancement module is used for adjusting the transient response of the output module. The output module is used for providing an output voltage to a load. By implementing the start control circuit described in the application, the jitter of the power supply voltage during system starting and the jitter of the output voltage during normal operation are balanced, so that the power supply voltage V CC jitter during system power-on is avoided, and the output voltage V out can quickly respond to fluctuations during normal operation, so that the output voltage is stable.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to an output voltage jitter prevention circuit. Background Technology

[0002] In the design of low dropout linear regulators (LDOs), a slew rate enhancement module is typically incorporated into the system to accelerate the transient response of the LDO output. However, it is difficult to achieve a good balance between the power supply voltage jitter during system startup and the output voltage jitter during normal operation when setting the slew rate enhancement module's turn-on threshold. Therefore, an anti-output voltage jitter circuit is urgently needed. Utility Model Content

[0003] To address the problem in existing low-dropout linear regulators where the slew rate enhancement module struggles to achieve a good balance between power supply voltage fluctuations during system startup and output voltage fluctuations during normal operation, this application provides the following technical solution:

[0004] A circuit for preventing output voltage jitter is provided, comprising: a comparator module, a slew rate enhancement module, and an output module.

[0005] The comparison module is connected to the slew rate enhancement module and the output module, and the slew rate enhancement module is connected to the output module.

[0006] The comparison module is used to start the slew rate enhancement module.

[0007] The slew rate enhancement module is used to adjust the transient response of the output module.

[0008] The output module is used to provide output voltage to the load.

[0009] Furthermore, the comparison module has: a first comparison module port, a second comparison module port, a third comparison module port, a fourth comparison module port, a fifth comparison module port, a sixth comparison module port, and a seventh comparison module port.

[0010] The oscillation enhancement module has: oscillation enhancement first port, oscillation enhancement second port, oscillation enhancement third port, oscillation enhancement fourth port and oscillation enhancement fifth port.

[0011] The output module has: a first port, a second port, and a third port.

[0012] The fourth port of the comparator module is connected to the third port of the slew rate enhancement module, the seventh port of the comparator module is connected to the second port of the slew rate enhancement module, the second port of the comparator module is connected to the second port of the output module, and the fourth port of the slew rate enhancement module is connected to the third port of the output module.

[0013] The first port of the module, the first port of the slew rate enhancement module, and the first port of the output module are used to obtain the power supply voltage. The fifth port of the comparison module is used to obtain the first bias voltage. The sixth port of the comparison module is used to obtain the reference voltage and to start the slew rate enhancement module when the reference voltage is greater than the output voltage. The fifth port of the slew rate enhancement module is used to obtain the second bias voltage. The second port of the output module is used to provide the output voltage.

[0014] Furthermore, the comparison module includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and an inverter.

[0015] The first transistor has: a first transistor first terminal, a first transistor second terminal, and a first transistor third terminal; the second transistor has: a second transistor first terminal, a second transistor second terminal, and a second transistor third terminal; the third transistor has: a third transistor first terminal, a third transistor second terminal, and a third transistor third terminal; the fourth transistor has: a fourth transistor first terminal, a fourth transistor second terminal, and a fourth transistor third terminal; the fifth transistor has: a fifth transistor first terminal, a fifth transistor second terminal, and a fifth transistor third terminal; the sixth transistor has: a sixth transistor first terminal, a sixth transistor second terminal, and a sixth transistor third terminal; the seventh transistor has: a seventh transistor first terminal, a seventh transistor second terminal, and a seventh transistor third terminal; the eighth transistor has: an eighth transistor first terminal, an eighth transistor second terminal, and an eighth transistor third terminal; the inverter has: an inverter input terminal and an inverter output terminal.

[0016] The first terminal of the second transistor is connected to the first terminal of the third transistor and the second terminal of the second transistor. The second terminal of the second transistor is also connected to the second terminal of the fourth transistor. The first terminal of the fourth transistor serves as the second port of the comparator module. The second terminal of the third transistor is connected to the second terminals of the fifth transistor and the second terminals of the eighth transistor, and then serves as the seventh port of the comparator module. The third terminal of the second transistor is connected to the third terminal of the third transistor and the third terminal of the eighth transistor, and then serves as the first port of the comparator module. The first terminal of the fifth transistor is connected to the first terminal of the first transistor, and then serves as the sixth port of the comparator module. The third terminal of the fifth transistor is connected to the second terminal of the first transistor. The third terminal of the first transistor is connected to the third terminal of the fourth transistor and the second terminal of the sixth transistor, and then serves as the fifth port of the comparator module. The third terminal of the sixth transistor is connected to the second terminal of the seventh transistor. The first terminal of the seventh transistor is connected to the first terminal of the eighth transistor and the inverter input terminal, and then serves as the third port of the comparator module. The inverter output terminal serves as the fourth port of the comparator module. The third terminal of the seventh transistor is used to connect to the reference potential.

[0017] Furthermore, the first transistor is an N-channel MOSFET.

[0018] Furthermore, the slew rate enhancement module includes: the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, and the thirteenth transistor.

[0019] The ninth transistor has: a first terminal, a second terminal, and a third terminal.

[0020] The tenth transistor has: a first terminal, a second terminal, and a third terminal.

[0021] The eleventh transistor has: the first terminal of the eleventh transistor, the second terminal of the eleventh transistor, and the third terminal of the eleventh transistor.

[0022] The twelfth transistor has: a first terminal, a second terminal, and a third terminal.

[0023] The thirteenth transistor has: a first terminal, a second terminal, and a third terminal.

[0024] The first terminal of the tenth transistor serves as the second port for slew rate enhancement, the first terminal of the eleventh transistor serves as the fifth port for slew rate enhancement, the third terminal of the tenth transistor is connected to the third terminal of the eleventh transistor and serves as the first port for slew rate enhancement, the second terminal of the tenth transistor is connected to the second terminal of the twelfth transistor and the first terminal of the twelfth transistor, the first terminal of the twelfth transistor is also connected to the first terminal of the thirteenth transistor and the second terminal of the ninth transistor, the second terminal of the thirteenth transistor is connected to the second terminal of the eleventh transistor and serves as the fourth port for slew rate enhancement, the first terminal of the ninth transistor serves as the third port for slew rate enhancement, and the third terminals of the twelfth transistor, the third terminals of the thirteenth transistor and the third terminal of the ninth transistor are connected to the reference potential.

[0025] Furthermore, the output module includes: the fourteenth transistor.

[0026] The fourteenth transistor has: a first terminal, a second terminal, and a third terminal.

[0027] The first terminal of the fourteenth transistor serves as the third port of the output module, the second terminal of the fourteenth transistor serves as the second port of the output module, and the third terminal of the fourteenth transistor serves as the first port of the output module.

[0028] Furthermore, the fourteenth transistor is a P-channel power MOSFET.

[0029] Furthermore, the anti-output voltage jitter circuit also includes a delay module.

[0030] The delay module is connected to the comparator module to slowly raise the reference voltage and suppress output voltage jitter.

[0031] Furthermore, the delay module has: a first port, a second port, a third port, and a fourth port.

[0032] The fourth port of the delay module is connected to the third port of the comparison module; the third port of the comparison module is used to acquire the delay signal, and the reference voltage is slowly raised when acquiring the delay signal.

[0033] The first port of the delay module is used to obtain the power supply voltage, the second port of the delay module is used to obtain the delay module enable signal to enable the delay module, and the third port of the delay module is used to obtain the reference voltage.

[0034] Furthermore, the delay module includes: a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, a buffer, a capacitor, and a first circuit.

[0035] The fifteenth transistor has: a first terminal, a second terminal, and a third terminal; the sixteenth transistor has: a first terminal, a second terminal, and a third terminal; the seventeenth transistor has: a first terminal, a second terminal, and a third terminal.

[0036] The buffer has: a first port and a second port.

[0037] The first terminal of the fifteenth transistor is connected to the first terminal of the sixteenth transistor and serves as the second port of the delay module. The third terminal of the fifteenth transistor serves as the first port of the delay module. The second terminal of the fifteenth transistor is connected to the second terminal of the sixteenth transistor and the first port of the buffer. The second port of the buffer serves as the fourth port of the delay module. The third terminal of the sixteenth transistor is connected to the second terminal of the seventeenth transistor. The first terminal of the seventeenth transistor serves as the third port of the delay module. The third terminal of the seventeenth transistor is connected to one end of the first resistor. The first port of the buffer is also connected to one end of the capacitor. The other end of the first resistor and the other end of the capacitor are connected to the reference potential.

[0038] By implementing the startup control circuit described in the embodiments of this application, the problems of power supply voltage fluctuation during system startup and output voltage fluctuation during normal operation are balanced, thereby preventing power supply voltage V fluctuations when the system is powered on. CC Jitter; during normal operation, it can quickly respond to the output voltage V. out The fluctuations in voltage stabilize the output voltage. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of an anti-output voltage jitter circuit module provided in an embodiment of this application;

[0041] Figure 2 This is a schematic diagram of the comparison module circuit provided in an embodiment of this application;

[0042] Figure 3 This is a schematic diagram of the slew rate enhancement module circuit provided in an embodiment of this application;

[0043] Figure 4 This is a schematic diagram of the output module circuit provided in an embodiment of this application;

[0044] Figure 5 This is a schematic diagram of another comparator module circuit;

[0045] Figure 6 This is a schematic diagram of another anti-output voltage jitter circuit module provided in an embodiment of this application;

[0046] Figure 7 This is a schematic diagram of the delay module circuit provided in the embodiment of this application. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0048] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The numbers in the accompanying drawings are only used to distinguish individual functional parts or modules and do not indicate logical relationships between parts or modules. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the term encompasses the element or object listed following the term and its equivalents, without excluding other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. “Above,” “below,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0049] The various embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same reference numerals are assigned to components having substantially the same or similar structure and function, and repeated descriptions of them will be omitted.

[0050] To address the problem that the slew rate enhancement module in a low-dropout linear regulator struggles to achieve a good balance between power supply voltage fluctuations during system startup and output voltage fluctuations during normal operation, this application provides the following technical solution:

[0051] In some embodiments, such as Figure 1 As shown, an anti-output voltage jitter circuit includes: a comparator module 100, a slew rate enhancement module 200, and an output module 300.

[0052] The comparison module 100 is connected to the oscillation enhancement module 200 and the output module 300, wherein the oscillation enhancement module 200 is connected to the output module 300.

[0053] Comparison module 100 is used to start slew rate enhancement module 200.

[0054] The slew rate enhancement module 200 is used to adjust the transient response of the output module 300.

[0055] Output module 300 is used to output to load R L Provide output voltage V out .

[0056] Specifically, the comparison module 100 has: a first comparison module port 101, a second comparison module port 102, a third comparison module port 103, a fourth comparison module port 104, a fifth comparison module port 105, a sixth comparison module port 106, and a seventh comparison module port 107.

[0057] The oscillation enhancement module 200 has: a first oscillation enhancement port 201, a second oscillation enhancement port 202, a third oscillation enhancement port 203, a fourth oscillation enhancement port 204, and a fifth oscillation enhancement port 205.

[0058] The output module 300 has: a first port 301, a second port 302, and a third port 303.

[0059] The fourth port 104 of the comparator module is connected to the third port 203 of the slew rate enhancement, the seventh port 107 of the comparator module is connected to the second port 202 of the slew rate enhancement, the second port 102 of the comparator module is connected to the second port 302 of the output module, and the fourth port 204 of the slew rate enhancement is connected to the third port 303 of the output module.

[0060] The first port 101 of the module, the first port 201 of the slew rate enhancement module, and the first port 301 of the output module are used to obtain the power supply voltage V. CC The fifth port 105 of the comparator module is used to obtain the first bias voltage V. bias1 The sixth port 106 of the comparator module is used to obtain the reference voltage V. ref and at the reference voltage V ref Greater than the output voltage V out The slew rate enhancement module 200 is activated, and the fifth port 205 of the slew rate enhancement module is used to obtain the second bias voltage V. bias2 The second port 302 of the output module is used to provide the output voltage V. out .

[0061] like Figure 2 As shown, the comparison module 100 includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and an inverter 110.

[0062] The first transistor T1 has: the first transistor's first electrode T 101 The second electrode of the first transistor T 102 and the third electrode T of the first transistor 103 The second transistor T2 has: the first electrode T of the second transistor 201 The second transistor's second electrode T 202 and the third electrode T of the second transistor 203The third transistor T3 has: the first terminal T of the third transistor 301 The second electrode of the third transistor T 302 and the third transistor's third electrode T 303 The fourth transistor T4 has: the first electrode T of the fourth transistor 401 The second electrode of the fourth transistor, T 402 and the third electrode T of the fourth transistor 403 The fifth transistor T5 has: the first electrode T of the fifth transistor 501 The second electrode of the fifth transistor, T 502 and the third electrode T of the fifth transistor 503 The sixth transistor T6 has: the first electrode T of the sixth transistor 601 The second electrode of the sixth transistor, T 602 and the third electrode T of the sixth transistor 603 The seventh transistor T7 has: the first terminal T of the seventh transistor 701 The second electrode of the seventh transistor, T 702 and the third electrode T of the seventh transistor 703 The eighth transistor T8 has: the first terminal T of the eighth transistor 801 The second electrode of the eighth transistor, T 802 and the third electrode T of the eighth transistor 803 The inverter 110 has an inverter input terminal 111 and an inverter output terminal 112.

[0063] Among them, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are N-channel MOSFETs; the second transistor T2, the third transistor T3 and the eighth transistor T8 are P-channel MOSFETs.

[0064] The first transistor's first electrode T 101 Gate, second electrode T of the first transistor 102 The drain and the third terminal of the first transistor, T. 103 The source; the first terminal of the second transistor, T. 201 Gate, second transistor, second electrode T 202 The drain, the third electrode of the second transistor, T 203 The source; the first terminal of the third transistor, T. 301 Gate, second electrode T of the third transistor 302 The drain, the third electrode of the third transistor T 303 Source; first terminal of the fourth transistor T 401 Gate, second electrode T of the fourth transistor 402 The drain, the third terminal of the fourth transistor, T 403 The source; the first terminal of the fifth transistor, T. 501 Gate, the second electrode of the fifth transistor T502 The drain, the third terminal of the fifth transistor, T 503 Source; the first terminal of the sixth transistor, T. 601 Gate, the second terminal of the sixth transistor T 602 The drain, the third terminal of the sixth transistor, T 603 Source; the first terminal of the seventh transistor, T. 701 Gate, the second terminal of the seventh transistor T 702 The drain, the third terminal of the seventh transistor, T 703 Source; the first terminal of the eighth transistor, T. 801 Gate, the second terminal of the eighth transistor T 802 The drain, the third terminal of the eighth transistor, T 803 For the source pole.

[0065] The first electrode of the second transistor T 201 With the first electrode T of the third transistor 301 and the second transistor's second electrode T 202 Connection, second transistor second electrode T 202 Also with the second electrode T of the fourth transistor 402 Connection, fourth transistor first electrode T 401 As the second port 102 of the comparison module, the second electrode of the third transistor T 302 With the second electrode T of the fifth transistor 502 and the second electrode T of the eighth transistor 802 After connection, it serves as the seventh port 107 of the comparator module, and the third electrode of the second transistor is T. 203 With the third transistor's third electrode T 303 and the third electrode T of the eighth transistor 803 After connection, it serves as the first port 101 of the comparator module, and the first electrode T of the fifth transistor. 501 With the first transistor first electrode T 101 After connection, it serves as the sixth port 106 of the comparator module, with the third electrode T of the fifth transistor. 503 With the second electrode T of the first transistor 102 Connection, first transistor third pole T 103 With the third electrode T of the fourth transistor 403 and the second electrode T of the sixth transistor 602 Connection, sixth transistor first terminal T 601 As the fifth port 105 of the comparator module, the third electrode of the sixth transistor T 603 With the second electrode T of the seventh transistor 702 Connection, seventh transistor first terminal T 701 With the first electrode T of the eighth transistor 801 And the inverter input terminal 111 is connected as the third port 103 of the comparator module, the inverter output terminal 112 is connected as the fourth port 104 of the comparator module, and the third electrode of the seventh transistor T703 Used to connect to a reference potential.

[0066] like Figure 3 As shown, the slew rate enhancement module 200 includes: a ninth transistor T9, a tenth transistor T... 10 11th transistor T 11 Twelfth transistor T 12 And the thirteenth transistor T 13 .

[0067] The ninth transistor T9 has: the first electrode T of the ninth transistor 901 The second electrode of the ninth transistor, T 902 and the third electrode T of the ninth transistor 903 .

[0068] The tenth transistor T 10 It has: the first electrode T of the tenth transistor 1001 The tenth transistor, second electrode T 1002 and the third electrode T of the tenth transistor 1003 .

[0069] 11th transistor T 11 It has: the first electrode T of the eleventh transistor 1101 11th transistor second electrode T 1102 And the third electrode T of the eleventh transistor 1103 .

[0070] Twelfth transistor T 12 It has: the first terminal T of the twelfth transistor 1201 The second electrode of the twelfth transistor T 1202 and the third electrode T of the twelfth transistor 1203 .

[0071] Thirteenth transistor T 13 It has: the first electrode T of the thirteenth transistor 1301 The second electrode of the thirteenth transistor, T 1302 And the third electrode T of the thirteenth transistor 1303 .

[0072] Among them, the ninth transistor T9 and the twelfth transistor T 12 And the thirteenth transistor T 13 It is an N-channel MOSFET; the tenth transistor T 10 11th transistor T 11 It is a P-channel MOSFET.

[0073] The first electrode of the ninth transistor, T 901 Gate, the second electrode of the ninth transistor T 902 The drain, the third terminal of the ninth transistor, T 903Source; the first terminal of the tenth transistor, T. 1001 Gate, the second terminal of the tenth transistor T 1002 The drain, the third terminal of the tenth transistor, T 1003 The source; the first terminal of the eleventh transistor, T. 1101 The gate, the second electrode of the eleventh transistor T 1102 The drain and the third terminal of the eleventh transistor, T. 1103 Source; the first terminal of the twelfth transistor, T. 1201 Gate, the second terminal of the twelfth transistor T 1202 The drain, the third terminal of the twelfth transistor, T 1203 Source; the first terminal of the thirteenth transistor, T. 1301 Gate, second terminal T of the thirteenth transistor 1302 The drain, the third terminal of the thirteenth transistor, T 1303 For the source pole.

[0074] The first electrode of the tenth transistor T 1001 As the second port 202 for slew rate enhancement, the first terminal T of the eleventh transistor... 1101 As the fifth port 205 for slew rate enhancement, the third electrode of the tenth transistor T 1003 With the third electrode T of the eleventh transistor 1103 After connection, it serves as the first port 201 for slew rate enhancement, and the second terminal T of the tenth transistor. 1002 With the second electrode T of the twelfth transistor 1202 and the first electrode T of the twelfth transistor 1201 Connection, the first terminal of the twelfth transistor T 1201 Also related to the first electrode T of the thirteenth transistor 1301 and the second electrode T of the ninth transistor 902 Connection, the second terminal of the thirteenth transistor T 1302 With the second electrode T of the eleventh transistor 1102 After connection, it serves as the fourth port 204 for slew rate enhancement, and the first electrode T of the ninth transistor. 901 As the third port 203 for slew rate enhancement, the third electrode of the twelfth transistor T 1203 The third electrode of the thirteenth transistor T 1303 and the third electrode T of the ninth transistor 903 Connect to the reference potential.

[0075] like Figure 4 As shown, the output module 300 includes: a fourteenth transistor T 14 .

[0076] Fourteenth transistor T 14 It has: the first terminal T of the fourteenth transistor 1401 The fourteenth transistor, second electrode T 1402 and the third electrode T of the fourteenth transistor1403 .

[0077] The fourteenth transistor's first electrode T 1401 Gate, the second terminal of the fourteenth transistor T 1402 The drain, the third terminal of the fourteenth transistor, T 1403 For the source pole.

[0078] The fourteenth transistor's first electrode T 1401 As the third port 303 of the output module, the second terminal of the fourteenth transistor T 1402 As the second port 302 of the output module, the third electrode of the fourteenth transistor T 1403 Port 301 serves as the first output port of the module.

[0079] Among them, the fourteenth transistor T 14 It is a P-channel power MOSFET.

[0080] In the design of low dropout linear regulators (LDOs), a slew rate enhancement module is typically incorporated into the system to accelerate the transient response of the LDO output. At the reference voltage V... ref When the value is low, the gate-source voltage of the sixth transistor T6 becomes low, and the sixth transistor T6 is in a subthreshold state, with its equivalent impedance R... T6 Increase the activation threshold I of the slew rate enhancement module. ref ·R T6 The slew rate enhancement module will not activate under low voltage conditions, preventing jitter during power-on. Under normal operating conditions, the reference voltage V... ref With a higher value, the gate-source voltage of the sixth transistor T6 increases, causing it to exit the subthreshold region and enhancing its conduction capability. The equivalent impedance R... T6 Reduce the activation threshold I of the slew rate enhancement module. ref ·R T6 Reduce it to the normal value. At this time, if the load current suddenly changes, V ref -Vout once higher than I ref ·R T6 The slew rate enhancement module is immediately activated to suppress V. out Continue to decrease, causing V out Rapid recovery reduces the amplitude of its jitter. Among them, I ref This is the reference current.

[0081] Compared to the second resistor R2 connected in series with the third terminal T of the fifth transistor 503 With the second electrode T of the sixth transistor 602 Regarding the proposed solution, such as Figure 5 As shown. The second resistor R2 is to turn off the comparator under normal operating conditions. The principle is: when V ref >Vout +I ref The slew rate enhancement module will only operate when R2 is reached, and Iref·R2 constitutes the activation threshold for the slew rate enhancement module. Where V ref V is the reference voltage. out For the output voltage, I ref The reference current is given by R2, and R2 is the resistance of the second resistor. However, during LDO startup, the reference voltage V... ref and output voltage V out Both are at low values; the sixth transistor T6 enters the linear region; the current flowing through the second resistor R2 is very small; and the reference voltage V... ref Slightly higher than the output voltage V out When this happens, the slew rate enhancement module will activate, introducing a large current that increases the output current V. out Jitter. If the resistance of the second resistor R2 is increased to such that I... ref • R2 remains large at low voltage, ensuring V during startup. ref -V out ref • R2 (slew rate enhancement module activation threshold) prevents jitter; however, as the resistance of the second resistor R2 increases, the activation threshold I of the slew rate enhancement module during normal operation also increases. ref R2 will also increase, and the output voltage V out It will be lower than V ref More frequent loads will activate the slew rate enhancement module, causing the system to respond more slowly to sudden increases in load current during normal operation, thus increasing the output voltage V. out The shaking.

[0082] In some other preferred embodiments, such as Figure 6 As shown, the anti-output voltage jitter circuit also includes a delay module 400.

[0083] The delay module 400 is connected to the comparator module 100 and is used to slowly raise the reference voltage V. ref This suppresses output voltage jitter.

[0084] Specifically, the delay module 400 has: a first port 401, a second port 402, a third port 403, and a fourth port 404.

[0085] The fourth port 404 of the delay module is connected to the third port 103 of the comparison module 100; the third port 103 of the comparison module is used to acquire the delay signal EN_d, and when acquiring the delay signal, the reference voltage V is slowly raised. ref .

[0086] The first port 401 of the delay module is used to obtain the power supply voltage V. CC ​The second port 402 of the delay module is used to acquire the delay module enable signal EN to enable the delay module 400. The third port 403 of the delay module is used to acquire the reference voltage V. ref .

[0087] like Figure 7 As shown, the delay module 400 includes: a fifteenth transistor T 15 The sixteenth transistor T 16 The seventeenth transistor T 17 The components include buffer 120, capacitor C, and the first circuit R1.

[0088] The fifteenth transistor T 15 It has: the first electrode T of the fifteenth transistor 1501 The second electrode of the fifteenth transistor, T 1502 and the third electrode T of the fifteenth transistor 1503 .

[0089] Sixteenth transistor T 16 It has: the first electrode T of the sixteenth transistor 1601 The second electrode of the sixteenth transistor, T 1602 and the third electrode T of the sixteenth transistor 1603 .

[0090] The seventeenth transistor T 17 It has: the first terminal T of the seventeenth transistor 1701 The seventeenth transistor, second electrode T 1702 and the third electrode T of the seventeenth transistor 1703 .

[0091] The buffer 120 has: a first buffer port 121 and a second buffer port 122.

[0092] The fifteenth transistor T 15 It is a P-channel MOSFET, the sixteenth transistor T 16 and the seventeenth transistor T 17 It is an N-channel MOSFET.

[0093] The first electrode of the fifteenth transistor, T 1501 Gate, the second electrode of the fifteenth transistor T 1502 The drain, the third terminal of the fifteenth transistor, T 1503 Source; the first terminal of the sixteenth transistor, T. 1601 Gate, the second terminal of the sixteenth transistor T 1602 The drain, the third terminal of the sixteenth transistor, T 1603 Source; the first terminal of the seventeenth transistor, T. 1701 Gate, the second terminal of the seventeenth transistor T 1702 The drain, the third terminal of the seventeenth transistor, T1703 For the source pole.

[0094] The first electrode of the fifteenth transistor, T 1501 With the first electrode T of the sixteenth transistor 1601 After connection, it serves as the second port 402 of the delay module, and the third electrode T of the fifteenth transistor. 1503 As the first port 401 of the delay module, the second terminal T of the fifteenth transistor 1502 With the second electrode T of the sixteenth transistor 1602 And the buffer's first port 121 is connected, the buffer's second port 122 serves as the fourth port 404 of the delay module; the sixteenth transistor's third electrode T 1603 With the second electrode T of the seventeenth transistor 1702 Connection, the first terminal T of the seventeenth transistor 1701 As the third port 403 of the delay module, the third electrode of the seventeenth transistor T 1703 One end of the first resistor R1 is connected to the first port 121 of the buffer, and the other end of the first resistor R1 and the other end of the capacitor C are connected to the reference potential.

[0095] After introducing the delay module 400, when the system is first powered on, the delay module enable signal EN is low, and the potential of capacitor C is V. CC As the power supply voltage V... CC Stable, the delay module enable signal EN transitions from low level to the power supply voltage V. CC At this time, the reference voltage V ref The change is slow, from low to high; the seventeenth transistor T 17 As the capacitor gradually transitions from the cutoff region to the saturation region, the conduction current gradually saturates. The charge on capacitor C (C·V) CC Only in V ref At a relatively high level (the seventeenth transistor T) 17 Rapid discharge only occurs when the delay module enable signal EN changes from low to high (in the saturation region). CC The delay signal EN_d changes from low level to V. CC The delay t is determined by the reference voltage V. ref The value is determined by the slew rate. When the slew rate enhancement module is turned on, the reference voltage V... ref The voltage has reached a relatively high level, I ref No longer subject to reference voltage V ref The effect is not caused by the seventeenth transistor T. 17 The tail current source determines this. Therefore, this further ensures the output voltage V. out There will be no jitter during setup.

[0096] By implementing the startup control circuit described in the embodiments of this application, the problems of power supply voltage fluctuation during system startup and output voltage fluctuation during normal operation are balanced, thereby preventing power supply voltage V fluctuations when the system is powered on. CC Jitter; during normal operation, it can quickly respond to the output voltage V. out The fluctuations in voltage make the output voltage stable; the addition of the delay module further ensures that the output voltage will not fluctuate.

[0097] All of the above-mentioned optional technical solutions can be combined in any way to form the optional embodiments of this application, and will not be described in detail here.

[0098] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A circuit for preventing output voltage jitter, characterized in that, include: The module includes a comparison module, a slew rate enhancement module, and an output module. The comparison module is connected to the slew rate enhancement module and the output module, and the slew rate enhancement module is connected to the output module. The comparison module is used to activate the slew rate enhancement module; The slew rate enhancement module is used to adjust the transient response of the output module; The output module is used to provide output voltage to the load.

2. The anti-output voltage jitter circuit according to claim 1, characterized in that, The comparison module has: a first comparison module port, a second comparison module port, a third comparison module port, a fourth comparison module port, a fifth comparison module port, a sixth comparison module port, and a seventh comparison module port; The oscillation rate enhancement module has: a first oscillation rate enhancement port, a second oscillation rate enhancement port, a third oscillation rate enhancement port, a fourth oscillation rate enhancement port, and a fifth oscillation rate enhancement port; The output module has: a first output module port, a second output module port, and a third output module port; The fourth port of the comparison module is connected to the third port of the slew rate enhancement, the seventh port of the comparison module is connected to the second port of the slew rate enhancement, the second port of the comparison module is connected to the second port of the output module, and the fourth port of the slew rate enhancement is connected to the third port of the output module. The first port of the module, the first port of the slew rate enhancement, and the first port of the output module are used to obtain the power supply voltage. The fifth port of the comparison module is used to obtain the first bias voltage. The sixth port of the comparison module is used to obtain the reference voltage and to activate the slew rate enhancement module when the reference voltage is greater than the output voltage. The fifth port of the slew rate enhancement is used to obtain the second bias voltage. The second port of the output module is used to provide the output voltage.

3. The anti-output voltage jitter circuit according to claim 2, characterized in that, The comparison module includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and an inverter; The first transistor has: a first transistor first terminal, a first transistor second terminal, and a first transistor third terminal; the second transistor has: a second transistor first terminal, a second transistor second terminal, and a second transistor third terminal; the third transistor has: a third transistor first terminal, a third transistor second terminal, and a third transistor third terminal; the fourth transistor has: a fourth transistor first terminal, a fourth transistor second terminal, and a fourth transistor third terminal; the fifth transistor has: a fifth transistor first terminal, a fifth transistor second terminal, and a fifth transistor third terminal; the sixth transistor has: a sixth transistor first terminal, a sixth transistor second terminal, and a sixth transistor third terminal; the seventh transistor has: a seventh transistor first terminal, a seventh transistor second terminal, and a seventh transistor third terminal; the eighth transistor has: an eighth transistor first terminal, an eighth transistor second terminal, and an eighth transistor third terminal; the inverter has: an inverter input terminal and an inverter output terminal; The first terminal of the second transistor is connected to the first terminal of the third transistor and the second terminal of the second transistor. The second terminal of the second transistor is also connected to the second terminal of the fourth transistor. The first terminal of the fourth transistor serves as the second port of the comparator module. The second terminal of the third transistor is connected to the second terminals of the fifth transistor and the second terminals of the eighth transistor, and then serves as the seventh port of the comparator module. The third terminal of the second transistor is connected to the third terminal of the third transistor and the third terminal of the eighth transistor, and then serves as the first port of the comparator module. The first terminal of the fifth transistor is connected to the first terminal of the first transistor, and then serves as the sixth port of the comparator module. The third terminal of the fifth transistor is connected to the second terminal of the first transistor. The third terminal of the first transistor is connected to the third terminal of the fourth transistor and the second terminal of the sixth transistor, and then serves as the fifth port of the comparator module. The third terminal of the sixth transistor is connected to the second terminal of the seventh transistor. The first terminal of the seventh transistor is connected to the first terminal of the eighth transistor and the first terminal of the inverter, and then serves as the third port of the comparator module. The output terminal of the inverter serves as the fourth port of the comparator module. The third terminal of the seventh transistor is used to connect to the reference potential.

4. The anti-output voltage jitter circuit according to claim 3, characterized in that, The first transistor is an N-channel MOSFET.

5. The anti-output voltage jitter circuit according to claim 2, characterized in that, The slew rate enhancement module includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; The ninth transistor has: a first terminal of the ninth transistor, a second terminal of the ninth transistor, and a third terminal of the ninth transistor; The tenth transistor has: a first terminal of the tenth transistor, a second terminal of the tenth transistor, and a third terminal of the tenth transistor; The eleventh transistor has: an eleventh transistor first terminal, an eleventh transistor second terminal, and an eleventh transistor third terminal; The twelfth transistor has: a first terminal, a second terminal, and a third terminal; The thirteenth transistor has: a first terminal of the thirteenth transistor, a second terminal of the thirteenth transistor, and a third terminal of the thirteenth transistor; The first terminal of the tenth transistor serves as the second port for slew rate enhancement, the first terminal of the eleventh transistor serves as the fifth port for slew rate enhancement, the third terminal of the tenth transistor is connected to the third terminal of the eleventh transistor and serves as the first port for slew rate enhancement, the second terminal of the tenth transistor is connected to the second terminal of the twelfth transistor and the first terminal of the twelfth transistor, the first terminal of the twelfth transistor is also connected to the first terminal of the thirteenth transistor and the second terminal of the ninth transistor, the second terminal of the thirteenth transistor is connected to the second terminal of the eleventh transistor and serves as the fourth port for slew rate enhancement, the first terminal of the ninth transistor serves as the third port for slew rate enhancement, and the third terminals of the twelfth transistor, the third terminals of the thirteenth transistor, and the third terminals of the ninth transistor are connected to a reference potential.

6. The anti-output voltage jitter circuit according to claim 2, characterized in that, The output module includes: a fourteenth transistor; The fourteenth transistor has: a first terminal, a second terminal, and a third terminal; The first terminal of the fourteenth transistor serves as the third port of the output module, the second terminal of the fourteenth transistor serves as the second port of the output module, and the third terminal of the fourteenth transistor serves as the first port of the output module.

7. The anti-output voltage jitter circuit according to claim 6, characterized in that, The fourteenth transistor is a P-channel power MOSFET.

8. The anti-output voltage jitter circuit according to any one of claims 1-7, characterized in that, The anti-output voltage jitter circuit also includes a delay module; The delay module is connected to the comparison module and is used to slowly raise the reference voltage and suppress output voltage jitter.

9. The anti-output voltage jitter circuit according to claim 8, characterized in that, The delay module has: a first port, a second port, a third port, and a fourth port. The fourth port of the delay module is connected to the third port of the comparison module; the third port of the comparison module is used to acquire the delay signal, and when acquiring the delay signal, the reference voltage is slowly raised; The first port of the delay module is used to obtain the power supply voltage, the second port of the delay module is used to obtain the delay module enable signal to enable the delay module, and the third port of the delay module is used to obtain the reference voltage.

10. The anti-output voltage jitter circuit according to claim 9, characterized in that, The delay module includes: a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, a buffer, a capacitor, and a first circuit; The fifteenth transistor has: a first terminal, a second terminal, and a third terminal; The sixteenth transistor has: a first terminal, a second terminal, and a third terminal; The seventeenth transistor has: a first terminal, a second terminal, and a third terminal; The buffer has: a first buffer port and a second buffer port; The first terminal of the fifteenth transistor is connected to the first terminal of the sixteenth transistor and serves as the second port of the delay module. The third terminal of the fifteenth transistor serves as the first port of the delay module. The second terminal of the fifteenth transistor is connected to the second terminal of the sixteenth transistor and the first port of the buffer. The second port of the buffer serves as the fourth port of the delay module. The third terminal of the sixteenth transistor is connected to the second terminal of the seventeenth transistor. The first terminal of the seventeenth transistor serves as the third port of the delay module. The third terminal of the seventeenth transistor is connected to one end of the first resistor. The first port of the buffer is also connected to one end of the capacitor. The other end of the first resistor and the other end of the capacitor are connected to a reference potential.

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