Test device and test system for GPU plug-in frame

Abstract

The present disclosure relates to a GPU test device and a test system, the GPU test device comprising a test slot assembly and a logic chip assembly, the test slot assembly comprising a first circuit board, a PCIe conversion chip and a communication protocol conversion chip, the first circuit board being provided with a connector for signal connection with a GPU slot, the first circuit board being signal connected with the logic chip assembly through a PCIe cable, and the PCIe conversion chip and the communication protocol conversion chip being arranged on the first circuit board. In this way, when the test device is connected with the corresponding GPU slot and the logic chip assembly through the connector respectively, the GPU slot can be tested at a lower cost and a faster response speed through the PCIe conversion chip and the communication protocol conversion chip arranged in the test slot assembly.

Description

Technical Field

[0001] This disclosure relates to the field of GPU interpolation testing equipment technology, and more specifically, to a GPU interpolation testing equipment and system. Background Technology

[0002] In related technologies, GPU (Graphics Processing Unit) frame testing usually requires a dedicated test head. The test head has a complex structure, numerous peripherals, a long delivery cycle for a single test head, and is expensive. In addition, the startup time of the entire test head is long. As a result, GPU frame testing in related technologies is costly and inefficient. Utility Model Content

[0003] The purpose of this disclosure is to provide a GPU interpolation testing device and system that is low in cost and highly efficient, thereby at least partially solving the problems in the related art.

[0004] To achieve the above objectives, this disclosure provides a GPU interpolation testing device, comprising: Test the in-frame components and logic chip components. The test frame assembly includes a first circuit board, a PCIe conversion chip, and a communication protocol conversion chip. The first circuit board has a connector for signal connection with the GPU frame. The first circuit board is signal connected to the logic chip assembly via a PCIe cable. Both the PCIe conversion chip and the communication protocol conversion chip are located on the first circuit board.

[0005] Optionally, there may be multiple PCIe conversion chips, which are arranged at intervals on the first circuit board.

[0006] Optionally, the PCIe conversion chip includes an uplink interface and multiple downlink interfaces. The uplink interface is used to signal connect to the logic chip assembly via the PCIe cable, and the multiple downlink interfaces are signal connected to the GPU frame via the connector.

[0007] Optionally, the connector is an inter-board connector.

[0008] Optionally, the testing equipment further includes a heat sink for dissipating heat from the GPU socket.

[0009] Optionally, the logic chip assembly and the test frame assembly are spaced apart, and the logic chip assembly is provided with an interface for electrical connection with the PCIe cable.

[0010] Optionally, the logic chip assembly includes a second circuit board and a CPU chip and a memory chip disposed on the second circuit board, and the interface is disposed on the second circuit board.

[0011] Optionally, the logic chip assembly is a mobile workstation.

[0012] A second aspect of this disclosure provides a testing system, including a GPU interposer and the aforementioned GPU interposer testing device, wherein the GPU interposer and the GPU interposer testing device are electrically connected.

[0013] Optionally, the GPU bay includes a UBB board and multiple OAM modules disposed on the UBB board.

[0014] The above technical solution utilizes a GPU interposer testing device comprising a test interposer assembly and a logic chip assembly. The test interposer assembly includes a first circuit board and a PCIe conversion chip and a communication protocol conversion chip mounted on the first circuit board. The first circuit board is equipped with connectors for signal connection with the GPU interposer assembly, and the first circuit board is connected to the logic chip assembly via a PCIe cable. Thus, the PCIe conversion chip enables signal connection between the GPU interposer assembly and the logic chip assembly, allowing for testing of the UBB board within the GPU interposer assembly and the OAM module mounted on the UBB board. Specifically, the PCIe chip in the GPU interposer assembly enables high-speed data path testing and OAM function module verification. The communication protocol conversion chip enables signal connection between the GPU interposer assembly and the logic chip assembly, thereby enabling low-speed management and monitoring of the UBB board within the GPU interposer assembly and the OAM module mounted on the UBB board, including temperature sensor network connectivity, OAM module identification and configuration, power supply and heat dissipation system monitoring, and inter-board connector status detection. Compared to related technologies that use a head-on GPU interlocking test, this solution requires less equipment, has lower costs, and runs faster. The startup time for head-on testing is reduced from approximately 3 minutes to 60 seconds, thus improving testing efficiency.

[0015] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the accompanying drawings...

[0017] Figure 1 This is a schematic diagram of the structure of a test device for a GPU interposer provided in an exemplary embodiment of this disclosure.

[0018] Figure 2This is a schematic diagram of the structure of the test system provided in an exemplary embodiment of this disclosure.

[0019] Figure 3 This is a schematic diagram of the structure of a GPU interpolation test device provided in related technologies.

[0020] Explanation of reference numerals in the attached figures 1-Test bay assembly; 11-First circuit board; 12-PCIe conversion chip; 13-First connector; 14-Communication protocol conversion chip; 15-Heat sink; 2-GPU bay; 21-UBB board; 22-OAM module; 3-Logic chip assembly; 31-Second circuit board; 32-CPU chip; 33-Storage chip; 4-Head unit; 41-Memory module; 42-Hard disk; 43-Adapter card; 5-Management chip. Detailed Implementation

[0021] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0022] In this disclosure, unless otherwise stated, directional terms such as “inner” and “outer” refer to the inner and outer parts of a specific structural outline; terms such as “first” and “second” are used only to distinguish one element from another and do not have any sequential or important meaning.

[0023] Furthermore, "comprising" and its variations are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment". Definitions of other terms will be given in the following description.

[0024] The terms “a” and “a plurality” used in this disclosure are illustrative and not restrictive, and those skilled in the art should understand that they should be understood as “one or more” unless otherwise expressly indicated in the context.

[0025] In this disclosure, directional terms are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or a specific orientation structure and operation, and therefore should not be construed as a limitation of this disclosure, which is not limited in this respect.

[0026] In the description of this disclosure, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "connect," "link," and "install" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0027] In related technologies, GPU (Graphics Processing Unit) frame fitting tests typically require dedicated testing equipment. This equipment is complex, has numerous peripherals, a long delivery cycle, and is expensive, with a single equipment unit costing over 200,000 yuan. Furthermore, the entire system takes a long time to boot due to the numerous peripherals, approximately 3 minutes. Therefore, GPU frame fitting testing in these technologies is both costly and inefficient. The testing equipment used in these technologies includes... Figure 3 As shown, the chassis 4 is connected to the GPU bay 2 via a connector. The chassis 4 includes four PCIe conversion chips, two CPU chips, a memory module 41, a hard drive 42, an adapter card 43, a management chip 5, a heatsink, and a network card. During testing, the GPU bay 2 and chassis 4 are connected via the first connector 13, and the four PCIe conversion chips and the management chip 5 are used for comprehensive testing of the UBB board and OAM module.

[0028] To solve the above problems, such as Figure 1 and Figure 2 As shown, this disclosure provides a test device for a GPU socket, including: a test socket assembly 1 and a logic chip assembly 3. The test socket assembly 1 includes a first circuit board 11 and a PCIe conversion chip 12 and a communication protocol conversion chip 14 disposed on the first circuit board 11. A connector 13 for connecting to the GPU socket 2 is disposed on the first circuit board 11. The first circuit board 11 is connected to the logic chip assembly 3 through a PCIe cable.

[0029] Through the above technical solution, the GPU frame testing equipment includes a test frame assembly 1 and a logic chip assembly 3. The test frame assembly 1 includes a first circuit board 11 and a PCIe conversion chip 12 and a communication protocol conversion chip 14 disposed on the first circuit board 11. The first circuit board 11 has a connector 13 for connecting to the GPU frame. The first circuit board 11 is connected to the logic chip assembly 3 via a PCIe cable. The PCIe (Peripheral Component Interconnect Express) conversion chip 12 and the communication protocol conversion chip 14 are respectively disposed on the first circuit board 11. Thus, the GPU frame 2 and the logic chip assembly 3 can be signal-connected through the PCIe conversion chip 12, thereby enabling testing of the UBB (Universal Baseboard, OAM module carrier board) 21 in the GPU frame 2 and the OAM (OCP Accelerator) board mounted on the UBB board 21. The testing of module 22 (a GPU acceleration module conforming to the OCP specification) involves using the PCIe chip 12 in the GPU enclosure testing equipment to perform high-speed data path testing and OAM function module verification. The communication protocol conversion chip 14 enables signal connection between the GPU enclosure 2 and the logic chip assembly 3, thereby completing low-speed management and monitoring of the UBB board 21 in the GPU enclosure 2 and the OAM module 22 installed on the UBB board 21. This includes temperature sensor network connectivity, OAM module 22 identification and configuration, power and heat dissipation system monitoring, and inter-board connector status detection. Compared to related technologies, this solution requires less equipment, has lower cost, and runs faster, reducing the startup time of the head unit test from approximately 3 minutes to 60 seconds, thus improving testing efficiency.

[0030] It should be noted that the test equipment for the GPU slot 2 provided in this disclosure uses a communication protocol conversion chip 14, which can be an I2C protocol conversion chip or an I3C protocol conversion chip, to scan all OAM modules 22 on the UBB board 21, obtain the device list and ID, and use the PCIe chip 12 to detect the function of each OAM module 22, establish a device topology diagram, and set test parameters such as PCIe link bandwidth, I2C or I3C timeout, and temperature threshold according to the test plan. The PCIe cable can be an MCIO (Mini Cool Edge IO) cable. The logic chip component 3 sends PCIe configuration commands to verify whether the link can be successfully trained and reach the expected bandwidth. Test data packets are sent to different OAM modules 22 on the UBB board 21 through the PCIe chip 12 to verify the accuracy of data routing. The PCIe chip 12 is used to monitor signal quality and check for problems such as impedance mismatch and crosstalk. In addition, the logic chip component 3 sends computation instructions to the GPU of the OAM module 22 to verify its basic functions such as floating-point operations and memory access, performs memory read / write tests, checks the integrity of the HBM / GDDR memory on the OAM module 22, and verifies the communication performance between OAM modules 22 through the high-speed interconnect channel of the UBB board 21. The logic chip component 3 reads the temperature sensor data on the OAM module 22 through the communication protocol conversion chip 14 to verify its accuracy and alarm threshold settings, tests the power timing, power consumption monitoring, and abnormal power failure protection mechanism of the OAM module 22, verifies the control capability of the UBB board 21 over the heat sink rotation speed to ensure normal response of the cooling system, and runs GPU computing load and temperature / power monitoring to verify the stability of the system under high load, as well as simulate PCIe link errors, temperature anomalies, and other faults to test the system's fault tolerance and recovery mechanism.

[0031] It should be noted that the GPU bay 2 mentioned above includes a UBB board 21 and eight OAM modules 22 installed on the UBB board 21. The communication protocol conversion chip 14 can be a USB to I2C protocol conversion chip.

[0032] In some possible implementations, there are multiple PCIe conversion chips 12 arranged at intervals on the first circuit board 11. For example, there can be two PCIe chips 12, each providing 16 channels. By setting up two PCIe chips 12, 32 channels can be provided. The number of OAM modules 22 is 8. Increasing the number of PCIe chips 12 can construct a multi-level switching topology, enabling multiple OAM modules 22 to be tested simultaneously, thereby shortening the test time and improving the test efficiency.

[0033] Of course, it is understood that the number of two PCIe conversion chips 12 mentioned above is illustrative. In other embodiments, the number of PCIe conversion chips 12 can be specifically selected according to different operating conditions. For example, in other embodiments, the number of PCIe conversion chips 12 can also be three, four, or five. Furthermore, more PCIe conversion chips 12 are not necessarily better. The number of PCIe conversion chips 12 and the testing efficiency of the OAM module 22 have an inverted U-shaped relationship. Within a reasonable range, such as 3 to 6 chips, increasing the number of PCIe conversion chips 12 can significantly improve testing efficiency; beyond this threshold, the benefits diminish.

[0034] For example, when testing a UBB board based on 8 OAM modules, two PCIe 5.0 switch chips are configured on the first circuit board 11 of the test equipment. Each PCIe conversion chip 12 is configured with one uplink PCIe×16 interface connected to the logic chip assembly 3.

[0035] In some possible implementations, the PCIe conversion chip 12 includes an uplink interface and multiple downlink interfaces. The uplink interface is signal-connected to the logic chip assembly 3 via a PCIe cable, and the multiple downlink interfaces are signal-connected to the GPU frame 2 via a connector 13. For example, the PCIe conversion chip 12 includes one uplink interface and four downlink interfaces. The UBB board 21 in the GPU bay 2 is equipped with eight OAM modules, each of which is equipped with one GPU. The PCIe conversion chip 12 is a PCIe 5.0 Switch chip with one PCIe x16 uplink channel (bandwidth 32GB / s, PCIe 5.0) and four PCIe x4 downlink channels (each with a bandwidth of 8GB / s, totaling 32GB / s), making the total uplink bandwidth equal to the total downlink bandwidth. Each downlink device receives equal bandwidth. Each PCIe conversion chip 12 corresponds to four OAM modules 22, which in turn corresponds to four GPUs. This ensures that the downlink bandwidth meets the computing needs of a single GPU while preventing the uplink bandwidth from becoming a bottleneck. It also avoids bandwidth competition on the shared bus, prevents interference between downlink devices, and improves system stability.

[0036] In some possible implementations, connector 13 is an inter-board connector. For example, it could be a dedicated high-speed connector recommended by the OCP specification, which can adapt to advantages such as high speed, high density, high reliability, and ease of maintenance. In particular, it is suitable for multi-GPU interconnection, large data transmission, and long-term stable operation scenarios in the architecture of UBB board 21 and OAM module 22. The dedicated high-speed connector recommended by the OCP specification has high-speed transmission capabilities, matching the bandwidth requirements of AI computing, supporting high-speed protocols, and being compatible with key protocols such as PCIe Gen5 / 6, NVLink 4.0, and CXL 3.0. It features a bottleneck-free bandwidth design, providing hundreds of differential signal pairs per connector, with a total bandwidth of up to 10Tbps, avoiding wasted computing power due to data transmission bottlenecks. Furthermore, it has low latency characteristics, reducing signal reflection and transmission delay. In addition, the dedicated high-speed connector recommended by the OCP specification can also transmit multiple signals in a single package, eliminating the need for separate power and management interfaces, saving PCB routing space on UBB board 21 and the first circuit board 11 in the test frame assembly 1. In addition, when connector 13 is a dedicated high-speed connector recommended by the OCP specification, it can also serve as an open standard interface to ensure that UBB boards, OAM modules and logic chip components 3 from different manufacturers are interchangeable, making it convenient to verify compatibility with different brands of equipment during testing.

[0037] In some possible implementations, the test equipment also includes a heat sink 15 for cooling the GPU socket 2. For example, the heat sink 15 can be a fan. By installing a fan in the test equipment, air can be supplied to the GPU socket 2 to cool it, thereby quickly cooling the OAM module 22 in the GPU socket 2 during high-power testing, so that the OAM module 22 in the GPU socket 2 can maintain high-power test conditions for a long time to complete the test.

[0038] Of course, it is understandable that the heat sink 15 mentioned above can be placed between the two PCIe conversion chips 12, thereby making full use of the space of the test frame assembly 1.

[0039] In some possible implementations, the logic chip assembly 3 and the test frame assembly 1 are spaced apart, with the logic chip assembly 3 having an interface for electrical connection to the PCIe cable. The logic chip assembly 3 may include a second circuit board 31 and a CPU chip 32 and a storage chip 33 disposed on the second circuit board 31. The storage chip 33 may include a memory module and a hard drive. In this case, to be compatible with the CPU chip 32, the communication protocol conversion chip 14 can be a USB to I2C protocol conversion chip, thereby enabling the CPU chip 32 to monitor and debug I2C devices. That is, the CPU chip 32 can read the temperature sensor data on the OAM module 22, verify its accuracy and alarm threshold settings, test the power timing, power consumption monitoring and abnormal power failure protection mechanism of the OAM module 22, verify the control capability of the UBB board 21 on the heat sink rotation speed, ensure the normal response of the heat dissipation system, run GPU computing load and temperature / power monitoring, verify the stability of the system under high load, and simulate PCIe link errors, temperature anomalies and other faults to test the fault tolerance and recovery mechanism of the system. Of course, the storage chip 33 in the above-mentioned logic chip component 3 includes a memory module and a hard disk. The hard disk stores the operating system, drivers, test applications, large datasets and calculation results, while the memory module provides data supply and caching. Sufficiently large and fast memory is the key to ensuring the continuous operation of the GPU. The interface on the logic chip component 3 that is electrically connected to the PCIe cable can be set on the second circuit board 31, so as to facilitate the connection between the second circuit board 31 and the first circuit board 11 via the PCIe cable, so that the GPU frame 2 and the logic chip component 3 can be connected through the test equipment signal of the GPU frame.

[0040] In some possible implementations, the logic chip assembly 3 mentioned in the test equipment for the GPU bay 2 can be a mobile workstation. The mobile workstation can be an existing product and can be obtained through external purchase. The mobile workstation includes a second circuit board 31, which is a PCB board. The second circuit board 31 has multiple mounting positions, some of which are used to install the CPU chip 32 and the memory chip 33. The PCB board also has an interface for electrical connection with a PCIe cable.

[0041] A second aspect of this disclosure provides a testing system including a GPU bay 2, a logic chip assembly 3, and a testing device for the GPU bay, wherein the GPU bay 2 and the logic chip assembly 3 are connected via the GPU bay testing device. The testing system of this disclosure incorporates all the advantages of the aforementioned GPU bay testing device, which will not be elaborated further here.

[0042] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0043] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0044] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A testing device for GPU interposer frames, characterized in that, include: Test the in-frame components and logic chip components. The test frame assembly includes a first circuit board, a PCIe conversion chip, and a communication protocol conversion chip. The first circuit board has a connector for signal connection with the GPU frame. The first circuit board is signal connected to the logic chip assembly via a PCIe cable. Both the PCIe conversion chip and the communication protocol conversion chip are located on the first circuit board.

2. The GPU interposer test device according to claim 1, characterized in that, There are multiple PCIe conversion chips, which are arranged at intervals on the first circuit board.

3. The GPU interposer test device according to claim 1, characterized in that, The PCIe conversion chip includes an uplink interface and multiple downlink interfaces. The uplink interface is used to connect to the logic chip components via a PCIe cable, and the multiple downlink interfaces are connected to the GPU frame via the connector.

4. The GPU interposer test device according to claim 1, characterized in that, The connector is an inter-board connector.

5. The GPU interposer test device according to claim 1, characterized in that, The testing equipment also includes a heat sink for dissipating heat from the GPU socket.

6. The GPU interposer test device according to claim 1, characterized in that, The logic chip assembly and the test frame assembly are spaced apart, and the logic chip assembly has an interface for electrical connection with the PCIe cable.

7. The GPU interposer test device according to claim 6, characterized in that, The logic chip assembly includes a second circuit board and a CPU chip and a memory chip disposed on the second circuit board, and the interface is disposed on the second circuit board.

8. The GPU interposer test device according to claim 1, characterized in that, The logic chip assembly is a mobile workstation.

9. A testing system, characterized in that, The device includes a GPU interposer and a test device for the GPU interposer as described in any one of claims 1-8, wherein the GPU interposer and the test device for the GPU interposer are electrically connected.

10. The testing system according to claim 9, characterized in that, The GPU bay includes a UBB board and multiple OAM modules mounted on the UBB board.

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