Computer device

Abstract

The embodiment of the present application discloses a computer device. The computer device comprises a function chip, a fan module, a super input-output chip and a level conversion unit. The function chip is provided with a first serial interface, the super input-output chip is provided with a second serial interface, the level conversion unit comprises a first level conversion circuit and a second level conversion circuit, and the first level conversion circuit and the second level conversion circuit are electrically connected between the first serial interface and the second serial interface. The embodiment of the present application sets the serial interface capable of supporting temperature data transmission on the function chip and the super input-output chip, utilizes the ability of the function chip to sample the temperature data of itself, and transmits the temperature data by means of the serial interface, so that the thermistor does not need to be set in the surrounding environment of the function chip to sample the temperature data, and thus the accuracy and reliability of the temperature sampling of the function chip can be improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to a computer device. Background Technology

[0002] The Central Processing Unit (CPU) of a computer device generates a significant amount of heat during operation. If this heat is not dissipated promptly, it can cause the CPU to enter an abnormal operating state, thereby reducing its performance. Typically, in computers supporting Intel standards, the CPU transmits its temperature to the embedded controller (EC) via the PECI (Platform Environment Control Interface). The EC then controls the fan to perform cooling operations based on the CPU temperature. However, other chips lack a PECI interface and cannot transmit temperature data to the embedded controller. To detect the temperature of these chips, related technologies place thermistors around them. These thermistors sample temperature data and transmit it directly to the embedded controller for temperature regulation.

[0003] However, the thermistor is not placed close to the chip, and the temperature data sampled by the thermistor is easily interfered with by other heat sources, so it cannot accurately reflect the temperature of the chip itself. At the same time, the relevant technology requires the temperature data sampled by the thermistor to be indirectly determined to determine the chip temperature. When the thermistor is abnormal but the chip is normal, the chip temperature cannot be known. This approach has significant limitations. Utility Model Content

[0004] To address the aforementioned technical problems, this application provides a computer device that improves upon the limitations of temperature detection in related technologies.

[0005] In a first aspect, embodiments of this application provide a computer device including a functional chip, a fan module, a super input / output (SUP) chip, and a level conversion unit. The functional chip has a first serial interface configured to transmit temperature data sampled by the functional chip, and the first serial interface includes a first clock terminal and a first data terminal. The SIP chip has a second serial interface and is electrically connected to the fan module, and the second serial interface includes a second clock terminal and a second data terminal. The level conversion unit includes a first level conversion circuit and a second level conversion circuit. The first level conversion circuit is electrically connected to the second clock terminal and is also electrically connected to the first clock terminal via a preset serial clock line. The second level conversion circuit is electrically connected to the second data terminal and is also electrically connected to the first data terminal via a preset serial data line. Both the first and second level conversion circuits are configured to transmit level conversion data to the SIP chip based on the temperature data transmitted by the functional chip, so that the SIP chip controls the fan module to adjust the operating temperature of the functional chip.

[0006] This embodiment of the application provides serial interfaces capable of supporting temperature data transmission on both the functional chip and the super input / output chip. Utilizing the functional chip's ability to sample its own temperature data, the serial interface is used to transmit this data, eliminating the need for a thermistor in the surrounding environment. This improves the accuracy and reliability of the functional chip's temperature sampling. Furthermore, this embodiment does not rely on a specific interface for temperature data transmission; it transmits temperature data to the super input / output chip only through the first and second serial interfaces. This allows the super input / output chip to control the fan module to adjust the functional chip's operating temperature, thus enhancing the compatibility of temperature detection.

[0007] Optionally, the first level conversion circuit includes a first pull-up circuit, a first switching unit, and a second pull-up circuit. The first terminal of the first switching unit is electrically connected to the first pull-up circuit and the second clock terminal, respectively. The second terminal of the first switching unit is electrically connected to the second pull-up circuit and is also electrically connected to the first clock terminal through a serial clock line. The first switching unit is configured to transmit a first clock signal input via the first clock terminal to the first pull-up circuit so that the first pull-up circuit performs level conversion on the first clock signal, or to transmit a second clock signal input via the second clock terminal to the second pull-up circuit so that the second pull-up circuit performs level conversion on the second clock signal.

[0008] The embodiments of this application, through the coordinated operation of the first pull-up circuit, the first switching unit, and the second pull-up circuit, can convert the level of the clock signal into the level of the adaptive functional chip or the super input / output chip, thereby improving the compatibility of clock signal transmission between the functional chip and the super input / output chip.

[0009] Optionally, the first pull-up circuit includes a first resistor, a first voltage is applied to a first end of the first resistor, and a second end of the first resistor is electrically connected to a first end of the first switching unit; and / or, the second pull-up circuit includes a second resistor, a second voltage is applied to a first end of the second resistor, and a second end of the second resistor is electrically connected to a second end of the first switching unit.

[0010] Optionally, the first switching unit includes a first switch and a second switch connected in series. The first terminal of the first switch is electrically connected to a first pull-up circuit and a second clock terminal, respectively. The second terminal of the first switch is electrically connected to the first terminal of the second switch. The second terminal of the second switch is electrically connected to the second pull-up circuit and is also electrically connected to the first clock terminal through a serial clock line.

[0011] Both the first switch and the second switch are configured to transmit a second clock signal input via a second clock terminal to a second pull-up circuit, so that the second pull-up circuit performs level conversion on the second clock signal, and the second switch is also configured to block power backflow from the first clock terminal to the second clock terminal; or, both the first switch and the second switch are configured to transmit a first clock signal input via a first clock terminal to a first pull-up circuit, so that the first pull-up circuit performs level conversion on the first clock signal, and the first switch is also configured to block power backflow from the second clock terminal to the first clock terminal.

[0012] The embodiments of this application utilize a first switch and a second switch to transmit clock signals from a functional chip or a super input / output chip, and can also prevent power from flowing back from the functional chip or super input / output chip to the super input / output chip or functional chip, thereby improving the working stability of the computer equipment.

[0013] Optionally, the first switch is a first NMOS transistor, the second switch is a second NMOS transistor, and the first switching unit further includes a first Zener diode and a second Zener diode. A first voltage is applied to the gate of the first NMOS transistor. The drain of the first NMOS transistor is electrically connected to a first pull-up circuit and a second clock terminal, respectively. The anode of the body diode of the first NMOS transistor is electrically connected to the source of the first NMOS transistor, and the cathode of the body diode is electrically connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is also electrically connected to the source of the second NMOS transistor. A first voltage is applied to the gate of the second NMOS transistor. The drain of the second NMOS transistor is electrically connected to a second pull-up circuit and also electrically connected to the first clock terminal via a serial clock line. The anode of the body diode of the second NMOS transistor is electrically connected to the source of the second NMOS transistor, and the cathode of the body diode is electrically connected to the drain of the second NMOS transistor. The first Zener diode is electrically connected between the gate and source of the first NMOS transistor, and the second Zener diode is electrically connected between the gate and source of the second NMOS transistor.

[0014] This application embodiment employs a first NMOS transistor and a second NMOS transistor, which not only transmits clock signals from the functional chip or the super input / output chip, but also prevents power from flowing back into the super input / output chip or the functional chip, thereby improving the operational stability of the computer equipment. Simultaneously, this application embodiment, through the first and second Zener diodes, also protects the first and second NMOS transistors from high-voltage damage.

[0015] Optionally, the second level conversion circuit includes a third pull-up circuit, a second switching unit, and a fourth pull-up circuit; the first terminal of the second switching unit is electrically connected to the third pull-up circuit and the second data terminal respectively, and the second terminal of the second switching unit is electrically connected to the fourth pull-up circuit and is also electrically connected to the first data terminal through a serial data line; the second switching unit is configured to transmit first data input via the first data terminal to the third pull-up circuit so that the third pull-up circuit performs level conversion on the first data, or to transmit second data input via the second data terminal to the fourth pull-up circuit so that the fourth pull-up circuit performs level conversion on the second data.

[0016] The embodiments of this application, through the coordinated operation of the third pull-up circuit, the second switching unit, and the fourth pull-up circuit, can convert the data level into the level of the adaptive function chip or super input / output chip, thereby improving the compatibility of data transmission between the function chip and the super input / output chip.

[0017] Optionally, the third pull-up circuit includes a third resistor, a second voltage is applied to the first end of the third resistor, and the second end of the third resistor is electrically connected to the first end of the second switching unit; and / or, the fourth pull-up circuit includes a fourth resistor, a second voltage is applied to the first end of the fourth resistor, and the second end of the fourth resistor is electrically connected to the second end of the second switching unit.

[0018] Optionally, the second switching unit includes a third switch and a fourth switch connected in series. The first end of the third switch is electrically connected to the third pull-up circuit and the second data terminal, respectively. The second end of the third switch is electrically connected to the first end of the fourth switch. The second end of the fourth switch is electrically connected to the fourth pull-up circuit and is also electrically connected to the first data terminal through a serial data line.

[0019] Both the third and fourth switches are configured to transmit the first data input via the first data terminal to the third pull-up circuit, so that the third pull-up circuit performs level conversion on the first data, and the fourth switch is also configured to block power backflow from the first data terminal to the second data terminal; or, both the third and fourth switches are configured to transmit the second data input via the second data terminal to the fourth pull-up circuit, so that the fourth pull-up circuit performs level conversion on the second data, and the third switch is also configured to block power backflow from the second data terminal to the first data terminal.

[0020] This application embodiment utilizes a third switch and a fourth switch to transmit data from a functional chip or a super input / output chip, and can also prevent power from flowing back from the functional chip or super input / output chip to the super input / output chip or functional chip, thereby improving the working stability of the computer equipment.

[0021] Optionally, the third switch is a third NMOS transistor, the fourth switch is a fourth NMOS transistor, and the second switching unit further includes a third Zener diode and a fourth Zener diode; the gate of the third NMOS transistor is subjected to a first voltage, the drain of the third NMOS transistor is electrically connected to the third pull-up circuit and the second data terminal respectively, the anode of the body diode of the third NMOS transistor is electrically connected to the source of the third NMOS transistor, the cathode of the body diode of the third NMOS transistor is electrically connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is also electrically connected to the source of the fourth NMOS transistor, the gate of the fourth NMOS transistor is subjected to a first voltage, the drain of the fourth NMOS transistor is electrically connected to the fourth pull-up circuit and is also electrically connected to the first data terminal through a serial data line, the anode of the body diode of the fourth NMOS transistor is electrically connected to the source of the fourth NMOS transistor, the cathode of the body diode of the fourth NMOS transistor is electrically connected to the drain of the fourth NMOS transistor, the third Zener diode is electrically connected between the gate and the source of the third NMOS transistor, and the fourth Zener diode is electrically connected between the gate and the source of the fourth NMOS transistor.

[0022] This application embodiment employs a third NMOS transistor and a fourth NMOS transistor, which not only transmits data from the functional chip or the super input / output chip, but also prevents power from the functional chip or super input / output chip from flowing back to the super input / output chip or the functional chip, thereby improving the operational stability of the computer equipment. Simultaneously, this application embodiment also protects the third and fourth NMOS transistors from high-voltage damage through the third and fourth Zener diodes.

[0023] Optionally, the functional chip may include any one of a central processing unit, a power management chip, or a memory chip. Attached Figure Description

[0024] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0025] Figure 1 A schematic diagram of the circuit structure of a computer device provided in an embodiment of this application; Figure 2A schematic diagram of the circuit structure of a computer device using Intel standards provided in the embodiments of this application; Figure 3 A circuit structure diagram of a computer device provided for some embodiments of this application; Figure 4 This is a schematic diagram of the specific circuit structure of a level conversion unit provided in an embodiment of this application; Figure 5 A circuit structure diagram of a computer device provided for other embodiments of this application; Figure 6 A circuit structure diagram of a computer device provided for other embodiments of this application; Figure 7 This is a schematic diagram of the circuit structure of a computer device provided for other embodiments of this application. Detailed Implementation

[0026] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "electrically connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "bottom," etc., used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. Furthermore, technical features involved in the different embodiments of this application described below may be combined with each other as long as they do not conflict with each other.

[0028] Computer equipment consists of components such as CPU, power supply module, memory, hard drive, and graphics card. When working, the power consumption of a computer is relatively high, reaching over 100W. Therefore, computer equipment generates a lot of heat when working. If the heat is not dissipated in time, it can easily cause the CPU and other components to lag due to overheating, seriously affecting performance.

[0029] Typically, computer equipment requires real-time monitoring of the CPU temperature and the temperatures of other chips. Higher CPU and chip temperatures necessitate higher fan speeds to dissipate heat more effectively; however, high speeds can lead to increased fan noise. To achieve a balance between heat dissipation and fan noise, precise monitoring of the operating temperatures of various heat sources is necessary to flexibly adjust fan speeds accordingly.

[0030] There are currently two methods for reading CPU temperature, as follows: 1. Place a thermistor around the CPU and adjust the fan speed based on the temperature data sampled by the thermistor. 2. Obtain the temperature data transmitted by the CPU through the CPU's PECI interface and adjust the fan speed based on this temperature data.

[0031] The two methods for reading CPU temperature each have the following drawbacks: 1. In the first method, the thermistor is not placed close to the CPU, but at a certain distance. This makes it susceptible to interference from surrounding heat sources, or the heat detected by the thermistor may have already attenuated before reaching the CPU, resulting in a significant deviation between the temperature data sampled by the thermistor and the actual CPU temperature. 2. The second method is only suitable for computer equipment using Intel standards and is not suitable for computer equipment using other standards. Therefore, the application scope of the second method is relatively limited.

[0032] In Intel standard computer devices or other standard computer devices, the primary method for reading the temperature of other types of chips is currently the first approach, which also suffers from the same drawbacks. It's worth noting that although other types of chips (such as power management chips) have the ability to sample their own temperature, they lack corresponding output interfaces to transmit temperature data to upper-level chips or applications via their pins. Therefore, related technologies still use the first approach to detect the temperature of other types of chips in order to transmit the chip temperature data to the embedded controller. Furthermore, this approach requires indirectly determining the chip temperature through temperature data sampled by a thermistor. When the thermistor malfunctions but the chip is functioning normally, the chip temperature cannot be determined, which presents a significant limitation.

[0033] This embodiment of the application provides serial interfaces capable of supporting temperature data transmission on both the functional chip and the super input / output chip. Utilizing the functional chip's ability to sample its own temperature data, the serial interface is used to transmit this data, eliminating the need for a thermistor in the surrounding environment. This improves the accuracy and reliability of the functional chip's temperature sampling. Furthermore, this embodiment does not rely on a specific interface for temperature data transmission; it transmits temperature data to the super input / output chip only through the first and second serial interfaces. This allows the super input / output chip to control the fan module to adjust the functional chip's operating temperature, thus enhancing the compatibility of temperature detection.

[0034] The following embodiments of this application provide a computer device. Please refer to... Figure 1 The computer device 100 includes a functional chip 200, a fan module 300, a super input / output chip 400, and a level conversion unit 500.

[0035] The functional chip 200 is configured to sample its own temperature. For example, the functional chip 200 integrates a temperature sensor that can sample the temperature of the functional chip 200 during operation. The functional chip 200 includes a central processing unit, a power management chip, or a memory chip.

[0036] The functional chip 200 is provided with a first serial interface 21, which is used to transmit temperature data sampled by the functional chip 200. The first serial interface 21 includes a first clock terminal 211 and a first data terminal 212.

[0037] The fan module 300 is used to dissipate heat from the functional chip 200. The fan module 300 includes one or more fans.

[0038] The Super Input / Output (SIO) chip 400 is equipped with a second serial interface 41 and is electrically connected to the fan module 300. The second serial interface 41 includes a second clock terminal 411 and a second data terminal 412. Each functional chip transmits temperature data to the SIO chip 400 through the serial interface. Based on the temperature data and a preset fan speed curve, the SIO chip 400 determines the target fan speed and controls the fan module to rotate according to the target fan speed. In this way, the SIO chip 400 can match the optimal target fan speed for the current environment for heat dissipation, avoiding fan noise caused by matching too high a fan speed, and also avoiding the inability to dissipate heat to the external environment in time due to matching too low a fan speed.

[0039] When data is exchanged between the Super Input / Output Chip 400 and the Functional Chip 200, the voltage levels of the data responded to by the Super Input / Output Chip 400 and the Functional Chip 200 can be the same or different. For example, the voltage level of the data responded to by the Super Input / Output Chip 400 is 3.3V, and the voltage level of the data responded to by the Functional Chip 200 is 1.8V. Therefore, in this embodiment, the 3.3V of the data from the Super Input / Output Chip 400 needs to be converted to 1.8V so that the Functional Chip 200 can respond to the data normally; alternatively, the 1.8V of the data from the Functional Chip 200 needs to be converted to 3.3V so that the Super Input / Output Chip 400 can respond to the data normally.

[0040] The level conversion unit 500 includes a first level conversion circuit 600 and a second level conversion circuit 700. The first level conversion circuit 600 is electrically connected to the second clock terminal 411 and is also electrically connected to the first clock terminal 211 through a preset serial clock line 50a. The second level conversion circuit 700 is electrically connected to the second data terminal 412 and is also electrically connected to the first data terminal 212 through a preset serial data line 50b.

[0041] Both the first level conversion circuit 600 and the second level conversion circuit 700 can convert the temperature data transmitted by the functional chip 200 to obtain level-converted data adapted to the functional chip 200 or the super input / output chip 400. Specifically, both the first level conversion circuit 600 and the second level conversion circuit 700 can be used to transmit level-converted data to the super input / output chip 400 based on the temperature data transmitted by the functional chip 200, so that the super input / output chip 400 can control the fan module 300 to adjust the operating temperature of the functional chip 200.

[0042] The working principle of computer device 100 is as follows: Functional chip 200 samples temperature data and sends the temperature data to super input / output chip 400 through first serial interface 21 and second serial interface 41. Super input / output chip 400 determines the target fan speed based on the temperature data and fan speed curve, and controls fan module 300 to adjust the operating temperature of functional chip 200 based on the target fan speed.

[0043] This embodiment of the application eliminates the need for a thermistor to be placed in the surrounding environment of the functional chip 200 to sample temperature data. By utilizing the functional chip 200's ability to sample its own temperature data, the sampled temperature data is ensured to be relatively reliable and accurate. Furthermore, this embodiment of the application provides serial interfaces capable of supporting temperature data transmission on both the functional chip 200 and the super input / output chip 400, overcoming the problem in related technologies that temperature data cannot be transmitted to the super input / output chip 400.

[0044] Furthermore, when the functional chip 200 is a CPU, in computer devices using Intel standards, related technologies can only transmit temperature data via the PECI interface. In computer devices not using Intel standards, to obtain CPU temperature data, a thermistor must be placed around the CPU to sample the CPU temperature data for transmission to the embedded controller. However, this embodiment uses serial port transmission to transmit temperature data. Even if the CPU in a computer device not using Intel standards lacks a PECI interface, it can still transmit temperature data via serial port transmission. Therefore, the approach of this embodiment is compatible with computer devices not using Intel standards, without relying on a specific interface to transmit temperature data. It only transmits temperature data to the Super Input / Output chip via the first and second serial interfaces, so that the Super Input / Output chip can control the fan module to adjust the operating temperature of the functional chip. This improves the compatibility of temperature detection.

[0045] When the function chip 200 is a power management chip and the computer device uses Intel standards, please refer to [link to relevant documentation]. Figure 2 The CPU800 is electrically connected to the Super Input / Output Chip 400 via a PECI interface, and transmits temperature data about the CPU800 to the Super Input / Output Chip 400 via the PECI interface. The function chip 200 transmits temperature data of the function chip 200 to the Super Input / Output Chip 400 via a first serial interface 21, a second serial interface 41, and the Super Input / Output Chip 400, respectively.

[0046] Please see Figure 3 The first level conversion circuit 600 includes a first pull-up circuit 61, a first switching unit 62, and a second pull-up circuit 63. The first terminal of the first switching unit 62 is electrically connected to the first pull-up circuit 61 and the second clock terminal 411, respectively. The second terminal of the first switching unit 62 is electrically connected to the second pull-up circuit 63 and is also electrically connected to the first clock terminal 211 through a serial clock line 50a.

[0047] The first pull-up circuit 61 is used to pull up the level of the clock signal input to the second clock terminal 411 to the first level. For example, the functional chip 200 transmits the first clock signal to the super input / output chip 400, wherein the level of the first clock signal is 1.8V. When the first clock signal is transmitted to the super input / output chip 400 via the second clock terminal 411, the first pull-up circuit 61 converts the 1.8V first clock signal into a 3.3V first conversion signal (that is, the level of the first conversion signal is the first level, and the first level is 3.3V). The 3.3V first conversion signal is input to the second clock terminal 411 to be transmitted to the super input / output chip 400.

[0048] The first switching unit 62 is used to transmit a first clock signal input via the first clock terminal 211 to the first pull-up circuit 61 so that the first pull-up circuit 61 performs level conversion on the first clock signal, or to transmit a second clock signal input via the second clock terminal 411 to the second pull-up circuit 63 so that the second pull-up circuit 63 performs level conversion on the second clock signal.

[0049] The second pull-up circuit 63 is used to pull up the level of the clock signal input to the first clock terminal 211 to the second level. For example, the super input / output chip 400 transmits the second clock signal to the function chip 200. The level of the second clock signal is 3.3V. When the second clock signal is transmitted to the function chip 200 via the first clock terminal 211, the second pull-up circuit 63 converts the 3.3V second clock signal into a 1.8V second conversion signal (that is, the level of the second conversion signal is the second level, and the second level is 1.8V). The 1.8V second conversion signal is input to the first clock terminal 211 to be transmitted to the function chip 200.

[0050] This embodiment of the application, through the coordinated operation of the first pull-up circuit 61, the first switching unit 62 and the second pull-up circuit 63, can convert the level of the clock signal into the level of the adaptive function chip 200 or the super input / output chip 400, thereby improving the compatibility of clock signal transmission between the function chip 200 and the super input / output chip 400.

[0051] Please see Figure 4 The first pull-up circuit 61 includes a first resistor R1, a first voltage V1 is applied to the first end of the first resistor R1, and the second end of the first resistor R1 is electrically connected to the first end 621 of the first switching unit 62. For example, the first voltage V1 is 3.3V.

[0052] When the functional chip 200 transmits the first clock signal to the super input / output chip 400, the first switching unit 62 transmits the first clock signal to the second clock terminal 411. Under the action of the first voltage V1, the first resistor R1 performs level conversion on the first clock signal to obtain a 3.3V first conversion signal.

[0053] Please continue reading. Figure 4 The second pull-up circuit 63 includes a second resistor R2, a second voltage V2 is applied to the first end of the second resistor R2, and the second end of the second resistor R2 is electrically connected to the second end 622 of the first switching unit 62. For example, the second voltage V2 is 1.8V.

[0054] When the super input / output chip 400 transmits the third clock signal to the function chip 200, the first switching unit 62 transmits the third clock signal to the first clock terminal 211. Under the action of the second voltage V2, the second resistor R2 performs level conversion on the third clock signal to obtain a second converted signal of 1.8V.

[0055] Please see Figure 5 The first switch unit 62 includes a first switch 621 and a second switch 622 connected in series. The first end of the first switch 621 is electrically connected to the first pull-up circuit 61 and the second clock terminal 411, respectively. The second end of the first switch 621 is electrically connected to the first end of the second switch 622. The second end of the second switch 622 is electrically connected to the second pull-up circuit 63 and is also electrically connected to the first clock terminal 211 through the serial clock line 50a.

[0056] In some embodiments, both the first switch 621 and the second switch 622 are used to transmit the second clock signal input to the second clock terminal 411 so that the second pull-up circuit 63 performs level conversion on the second clock signal. The second switch 622 is also used to block the power supply from the first clock terminal 211 from flowing back to the second clock terminal 411, thereby preventing the power supply from the first clock terminal 211 from affecting the super input / output chip 400.

[0057] In some embodiments, both the first switch 621 and the second switch 622 are used to transmit the first clock signal input to the first clock terminal 211 so that the first pull-up circuit 61 performs level conversion on the first clock signal. The first switch 621 is also used to block the power from the second clock terminal 411 from flowing back to the first clock terminal 211, thereby preventing the power from the second clock terminal 411 from affecting the functional chip 200.

[0058] This application embodiment utilizes the first switch 621 and the second switch 622 to transmit clock signals from the function chip 200 or from the super input / output chip 400, and can also prevent power from the function chip 200 or the super input / output chip 400 from flowing back to the super input / output chip 400 or the function chip 200, thereby improving the working stability of the computer device 100.

[0059] Please continue reading. Figure 4 The first switch 621 is the first NMOS transistor Q1, the second switch 622 is the second NMOS transistor Q2, and the first switch unit 62 also includes a first Zener diode ZD1 and a second Zener diode ZD2.

[0060] A first voltage V1 is applied to the gate of the first NMOS transistor Q1. The drain of the first NMOS transistor Q1 is electrically connected to the first pull-up circuit 61 and the second clock terminal 411. The anode of the body diode of the first NMOS transistor Q1 is electrically connected to the source of the first NMOS transistor Q1, and the cathode of the body diode of the first NMOS transistor Q1 is electrically connected to the drain of the first NMOS transistor Q1. The source of the first NMOS transistor Q1 is also electrically connected to the source of the second NMOS transistor Q2. The gate of the second NMOS transistor Q2 is also applied with the first voltage V1. The drain of the second NMOS transistor Q2 is electrically connected to the second pull-up circuit 63 and also electrically connected to the first clock terminal 211 through the serial clock line 50a. The positive terminal of the body diode of the second NMOS transistor Q2 is electrically connected to the source of the second NMOS transistor Q2, and the negative terminal of the body diode of the second NMOS transistor Q2 is electrically connected to the drain of the second NMOS transistor Q2. The first Zener diode ZD1 is electrically connected between the gate and the source of the first NMOS transistor Q1, and the second Zener diode ZD2 is electrically connected between the gate and the source of the second NMOS transistor Q2.

[0061] The working principles of the first NMOS transistor Q1 and the second NMOS transistor Q2 are as follows: 1) When the functional chip 200 transmits a low-level clock signal to the super input / output chip 400, the first NMOS transistor Q1 and the second NMOS transistor Q2 enter the conduction state under the action of the first voltage. The low-level clock signal from the first clock terminal 211 is transmitted to the second clock terminal 411 in sequence through the second NMOS transistor Q2 and the first NMOS transistor Q1, and is received by the super input / output chip 400.

[0062] When the functional chip 200 transmits a high-level clock signal to the super input / output chip 400, the high level is 1.8V. The first NMOS transistor Q1 and the second NMOS transistor Q2 are both cut off. The first pull-up circuit 61 outputs a high level of 3.3V. The 3.3V high level is transmitted to the second clock terminal 411 and received by the super input / output chip 400.

[0063] 2) When the super input / output chip 400 transmits a low-level clock signal to the function chip 200, the first NMOS transistor Q1 and the second NMOS transistor Q2 enter the conduction state under the action of the first voltage. The low-level clock signal from the second clock terminal 411 is transmitted to the first clock terminal 211 in sequence through the first NMOS transistor Q1 and the second NMOS transistor Q2, and is received by the super input / output chip 400.

[0064] When the super input / output chip 400 transmits a high-level clock signal to the function chip 200, the high level is 1.8V. The first NMOS transistor Q1 and the second NMOS transistor Q2 are both cut off. The second pull-up circuit 63 outputs a high level of 1.8V, which is transmitted to the first clock terminal 211 and received by the function chip 200.

[0065] The body diode of the first NMOS transistor Q1 can prevent power from flowing back from the super input / output chip 400 to the functional chip 200. At the same time, the body diode of the second NMOS transistor Q2 can prevent power from flowing back from the functional chip 200 to the super input / output chip 400.

[0066] The first Zener diode ZD1 is used to regulate the gate-source voltage of the first NMOS transistor Q1, preventing the first NMOS transistor Q1 from being broken down by high voltage and protecting the first NMOS transistor Q1.

[0067] The second Zener diode ZD2 is used to regulate the gate-source voltage of the second NMOS transistor Q2, preventing the second NMOS transistor Q2 from being broken down by high voltage and protecting the second NMOS transistor Q2.

[0068] This embodiment employs a first NMOS transistor Q1 and a second NMOS transistor Q2, which not only transmits clock signals from the functional chip or the super input / output chip, but also prevents power from flowing back into the super input / output chip or the functional chip, thereby improving the operational stability of the computer equipment. Simultaneously, this embodiment also protects the first NMOS transistor Q1 and the second NMOS transistor Q2 from high-voltage damage through the first Zener diode ZD1 and the second Zener diode ZD2.

[0069] Please see Figure 6 The second level conversion circuit 700 includes a third pull-up circuit 71, a second switching unit 72, and a fourth pull-up circuit 73. The first terminal of the second switching unit 72 is electrically connected to the third pull-up circuit 71 and the second data terminal 412, respectively. The second terminal of the second switching unit 72 is electrically connected to the fourth pull-up circuit 73 and is also electrically connected to the first data terminal 212 through a serial data line 50b.

[0070] The third pull-up circuit 71 is used to pull up the level of the data input to the second data terminal 412 to the third level. For example, the functional chip 200 transmits first data to the super input / output chip 400, wherein the level of the first data is 1.8V. When the first data is transmitted to the super input / output chip 400 via the second data terminal 412, the third pull-up circuit 71 converts the 1.8V first data into 3.3V first converted data (that is, the level of the first converted data is the third level, and the third level is 3.3V). The 3.3V first converted data is input to the second data terminal 412 to be transmitted to the super input / output chip 400.

[0071] The second switching unit 72 is used to transmit first data input via the first data terminal 212 to the third pull-up circuit 71 so that the third pull-up circuit 71 performs level conversion on the first data, or to transmit second data input via the second data terminal to the fourth pull-up circuit 73 so that the fourth pull-up circuit 73 performs level conversion on the second data.

[0072] The fourth pull-up circuit 73 is used to pull up the level of the data input to the first data terminal 212 to the fourth level. For example, the super input / output chip 400 transmits third data to the function chip 200, wherein the level of the third data is 3.3V. When the third data is transmitted to the function chip 200 via the first data terminal 212, the fourth pull-up circuit 73 converts the 3.3V third data into 1.8V second converted data (that is, the level of the second converted data is the fourth level, and the fourth level is 1.8V). The 1.8V second converted data is input to the first data terminal 212 to be transmitted to the function chip 200.

[0073] This embodiment of the application, through the coordinated operation of the third pull-up circuit 71, the second switching unit 72 and the fourth pull-up circuit 73, can convert the data level into the level of the adaptive function chip 200 or the super input / output chip 400, thereby improving the compatibility of data transmission between the function chip 200 and the super input / output chip 400.

[0074] Please continue reading. Figure 4 The third pull-up circuit 71 includes a third resistor R3. A first voltage V1 is applied to the first end of the third resistor R3, and the second end of the third resistor R3 is electrically connected to the first end 721 of the second switching unit 72.

[0075] When the functional chip 200 transmits the first data to the super input / output chip 400, the second switching unit 72 transmits the first data to the second data terminal 412. Under the action of the first voltage V1, the third resistor R3 performs level conversion on the first data to obtain the first converted data of 3.3V.

[0076] Please continue reading. Figure 4The fourth pull-up circuit 73 includes a fourth resistor R4, the first end of which is subjected to a second voltage V2, and the second end of the fourth resistor R4 is electrically connected to the second end 722 of the second switching unit 72.

[0077] When the super input / output chip 400 transmits third data to the function chip 200, the second switching unit 72 transmits the third data to the first data terminal 212. Under the action of the second voltage V2, the fourth resistor R4 performs level conversion on the third data to obtain 1.8V second converted data.

[0078] Please see Figure 7 The second switch unit 72 includes a third switch 721 and a fourth switch 722 connected in series. The first end of the third switch 721 is electrically connected to the third pull-up circuit 71 and the second data terminal 412, respectively. The second end of the third switch 721 is electrically connected to the first end of the fourth switch 722. The second end of the fourth switch 722 is electrically connected to the fourth pull-up circuit 73 and is also electrically connected to the first data terminal 212 through the serial data line 50b.

[0079] In some embodiments, both the third switch 721 and the fourth switch 722 are used to transmit the first data input via the first data terminal 212 to the third pull-up circuit 71 so that the third pull-up circuit 71 performs level conversion on the first data. The fourth switch 722 is also used to block the power from the first data terminal 212 from flowing back to the second data terminal 412, thereby preventing the power from the first data terminal 212 from affecting the super input / output chip 400.

[0080] In some embodiments, both the third switch 721 and the fourth switch 722 are used to transmit the second data input via the second data terminal 412 to the fourth pull-up circuit 73, so that the fourth pull-up circuit 73 performs level conversion on the second data. The third switch 721 is also used to block the power from the second data terminal 412 from flowing back to the first data terminal 212, thereby preventing the power from the second data terminal 412 from affecting the functional chip 200.

[0081] This application embodiment utilizes the third switch 721 and the fourth switch 722 to transmit data from the function chip 200 or the super input / output chip 400, and can also prevent power from the function chip 200 or the super input / output chip 400 from flowing back to the super input / output chip 400 or the function chip 200, thereby improving the working stability of the computer device 100.

[0082] Please continue reading. Figure 4 The third switch 721 is the third NMOS transistor Q3, the fourth switch 722 is the fourth NMOS transistor Q4, and the second switch unit 72 also includes the third Zener diode ZD3 and the fourth Zener diode ZD4.

[0083] The gate of the third NMOS transistor Q3 is subjected to a first voltage V1. The drain of the third NMOS transistor Q3 is electrically connected to the third pull-up circuit 71 and the second data terminal 412. The anode of the body diode of the third NMOS transistor Q3 is electrically connected to the source of the third NMOS transistor Q3, and the cathode of the body diode of the third NMOS transistor Q3 is electrically connected to the drain of the third NMOS transistor Q3. The source of the third NMOS transistor Q3 is also electrically connected to the source of the fourth NMOS transistor Q4. The gate of the fourth NMOS transistor Q4 is subjected to a first voltage V1. The drain of the fourth NMOS transistor Q4 is electrically connected to the fourth pull-up circuit 73 and also electrically connected to the first data terminal 212 through the serial data line 50b. The anode of the body diode of the fourth NMOS transistor Q4 is electrically connected to the source of the fourth NMOS transistor Q4, and the cathode of the body diode of the fourth NMOS transistor Q4 is electrically connected to the drain of the fourth NMOS transistor Q4. The third Zener diode ZD3 is electrically connected between the gate and source of the third NMOS transistor Q3, and the fourth Zener diode ZD4 is electrically connected between the gate and source of the fourth NMOS transistor Q4.

[0084] The working principles of the third NMOS transistor Q3 and the fourth NMOS transistor Q4 are as follows: 1) When the functional chip 200 transmits low-level data to the super input / output chip 400, the third NMOS transistor Q3 and the fourth NMOS transistor Q4 enter the conduction state under the action of the first voltage. The low-level data from the first data terminal 212 is transmitted to the second data terminal 412 in sequence through the fourth NMOS transistor Q4 and the third NMOS transistor Q3, and is received by the super input / output chip 400.

[0085] When the functional chip 200 transmits high-level data to the super input / output chip 400, the high level is 1.8V. The third NMOS transistor Q3 and the fourth NMOS transistor Q4 are both cut off. The third pull-up circuit 71 outputs a high level of 3.3V. The 3.3V high level is transmitted to the second data terminal 412 and received by the super input / output chip 400.

[0086] 2) When the super input / output chip 400 transmits low-level data to the function chip 200, the third NMOS transistor Q3 and the fourth NMOS transistor Q4 enter the conduction state under the action of the first voltage. The low-level data from the second data terminal 412 is transmitted to the first data terminal 212 in sequence through the third NMOS transistor Q3 and the fourth NMOS transistor Q4, and is received by the super input / output chip 400.

[0087] When the super input / output chip 400 transmits high-level data to the function chip 200, the high level is 1.8V. The third NMOS transistor Q3 and the fourth NMOS transistor Q4 are both cut off. The fourth pull-up circuit 73 outputs a high level of 1.8V, which is transmitted to the first data terminal 212 and received by the function chip 200.

[0088] The body diode of the third NMOS transistor Q3 can prevent power from flowing back from the super input / output chip 400 to the functional chip 200. Simultaneously, the body diode of the fourth NMOS transistor Q4 can prevent power from flowing back from the functional chip 200 to the super input / output chip 400.

[0089] The third Zener diode ZD3 is used to regulate the gate-source voltage of the third NMOS transistor Q3, preventing Q3 from being broken down by high voltage and protecting Q3.

[0090] The fourth Zener diode ZD4 is used to regulate the gate-source voltage of the fourth NMOS transistor Q4, preventing the fourth NMOS transistor Q4 from being broken down by high voltage and protecting the fourth NMOS transistor Q4.

[0091] This embodiment employs a third NMOS transistor Q3 and a fourth NMOS transistor Q4, which not only transmits data from the functional chip or the super input / output chip, but also prevents power from flowing back into the super input / output chip or the functional chip, thereby improving the operational stability of the computer equipment. Simultaneously, this embodiment also protects the third NMOS transistor Q3 and the fourth NMOS transistor Q4 from high-voltage damage through the third Zener diode ZD3 and the fourth Zener diode ZD4.

[0092] In summary, the embodiments of this application read the temperature data of the functional chip through a serial interface, eliminating the need for a thermistor to sample the temperature data in the surrounding environment. This improves the accuracy of the temperature data, preventing interference from surrounding heat sources and other factors. Furthermore, it eliminates the need for an additional thermistor, reducing the complexity of PCB routing. Finally, the embodiments of this application are suitable not only for computer equipment using Intel standards but also for computer equipment using domestically produced CPUs, thus broadening its applicability.

[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A computer device, characterized in that, include: The functional chip is provided with a first serial interface, which is configured to transmit temperature data sampled by the functional chip. The first serial interface includes a first clock terminal and a first data terminal. Fan module; The super input / output chip is provided with a second serial interface and is electrically connected to the fan module. The second serial interface includes a second clock terminal and a second data terminal. The level conversion unit includes a first level conversion circuit and a second level conversion circuit. The first level conversion circuit is electrically connected to the second clock terminal and is also electrically connected to the first clock terminal through a preset serial clock line. The second level conversion circuit is electrically connected to the second data terminal and is also electrically connected to the first data terminal through a preset serial data line. Both the first and second level conversion circuits are configured to transmit level conversion data to the super input / output chip based on the temperature data transmitted by the functional chip, so that the super input / output chip controls the fan module to adjust the operating temperature of the functional chip.

2. The computer device according to claim 1, characterized in that, The first level conversion circuit includes a first pull-up circuit, a first switching unit, and a second pull-up circuit; The first terminal of the first switching unit is electrically connected to the first pull-up circuit and the second clock terminal respectively, and the second terminal of the first switching unit is electrically connected to the second pull-up circuit and is also electrically connected to the first clock terminal through the serial clock line. The first switching unit is configured to transmit a first clock signal input via the first clock terminal to the first pull-up circuit so that the first pull-up circuit performs level conversion on the first clock signal, or to transmit a second clock signal input via the second clock terminal to the second pull-up circuit so that the second pull-up circuit performs level conversion on the second clock signal.

3. The computer device according to claim 2, characterized in that, The first pull-up circuit includes a first resistor, a first voltage is applied to a first end of the first resistor, and a second end of the first resistor is electrically connected to a first end of the first switching unit; And / or, The second pull-up circuit includes a second resistor, a second voltage is applied to the first end of the second resistor, and the second end of the second resistor is electrically connected to the second end of the first switching unit.

4. The computer device according to claim 2, characterized in that, The first switching unit includes a first switch and a second switch connected in series. The first terminal of the first switch is electrically connected to the first pull-up circuit and the second clock terminal, respectively. The second terminal of the first switch is electrically connected to the first terminal of the second switch. The second terminal of the second switch is electrically connected to the second pull-up circuit and is also electrically connected to the first clock terminal through the serial clock line. Both the first switch and the second switch are configured to transmit a second clock signal input via the second clock terminal to the second pull-up circuit, so that the second pull-up circuit performs level conversion on the second clock signal, and the second switch is also configured to block power from flowing back from the first clock terminal to the second clock terminal; or, Both the first switch and the second switch are configured to transmit a first clock signal input via the first clock terminal to the first pull-up circuit, so that the first pull-up circuit performs level conversion on the first clock signal, and the first switch is also configured to block power from flowing back from the second clock terminal to the first clock terminal.

5. The computer device according to claim 4, characterized in that, The first switch is a first NMOS transistor, the second switch is a second NMOS transistor, and the first switching unit further includes a first Zener diode and a second Zener diode; A first voltage is applied to the gate of the first NMOS transistor. The drain of the first NMOS transistor is electrically connected to the first pull-up circuit and the second clock terminal, respectively. The anode of the body diode of the first NMOS transistor is electrically connected to the source of the first NMOS transistor, and the cathode of the body diode of the first NMOS transistor is electrically connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is also electrically connected to the source of the second NMOS transistor. A first voltage is applied to the gate of the second NMOS transistor. The drain of the second NMOS transistor is electrically connected to the second pull-up circuit and is also electrically connected to the first clock terminal through the serial clock line. The anode of the body diode of the second NMOS transistor is electrically connected to the source of the second NMOS transistor, and the cathode of the body diode of the second NMOS transistor is electrically connected to the drain of the second NMOS transistor. The first Zener diode is electrically connected between the gate and source of the first NMOS transistor, and the second Zener diode is electrically connected between the gate and source of the second NMOS transistor.

6. The computer device according to claim 1, characterized in that, The second level conversion circuit includes a third pull-up circuit, a second switching unit, and a fourth pull-up circuit; The first end of the second switching unit is electrically connected to the third pull-up circuit and the second data terminal, respectively; the second end of the second switching unit is electrically connected to the fourth pull-up circuit and is also electrically connected to the first data terminal through the serial data line. The second switching unit is configured to transmit first data input via the first data terminal to the third pull-up circuit so that the third pull-up circuit performs level conversion on the first data, or to transmit second data input via the second data terminal to the fourth pull-up circuit so that the fourth pull-up circuit performs level conversion on the second data.

7. The computer device according to claim 6, characterized in that, The third pull-up circuit includes a third resistor, a second voltage is applied to the first end of the third resistor, and the second end of the third resistor is electrically connected to the first end of the second switching unit; And / or, The fourth pull-up circuit includes a fourth resistor, a second voltage is applied to the first end of the fourth resistor, and the second end of the fourth resistor is electrically connected to the second end of the second switching unit.

8. The computer device according to claim 6, characterized in that, The second switching unit includes a third switch and a fourth switch connected in series. The first end of the third switch is electrically connected to the third pull-up circuit and the second data terminal, respectively. The second end of the third switch is electrically connected to the first end of the fourth switch. The second end of the fourth switch is electrically connected to the fourth pull-up circuit and is also electrically connected to the first data terminal through the serial data line. Both the third switch and the fourth switch are configured to transmit the first data input via the first data terminal to the third pull-up circuit, so that the third pull-up circuit performs level conversion on the first data, and the fourth switch is further configured to block power from the first data terminal from flowing back to the second data terminal; or, Both the third switch and the fourth switch are configured to transmit the second data input via the second data terminal to the fourth pull-up circuit, so that the fourth pull-up circuit performs level conversion on the second data, and the third switch is also configured to block power from flowing back from the second data terminal to the first data terminal.

9. The computer device according to claim 8, characterized in that, The third switch is a third NMOS transistor, the fourth switch is a fourth NMOS transistor, and the second switching unit also includes a third Zener diode and a fourth Zener diode; The gate of the third NMOS transistor is subjected to a first voltage. The drain of the third NMOS transistor is electrically connected to the third pull-up circuit and the second data terminal, respectively. The anode of the body diode of the third NMOS transistor is electrically connected to the source of the third NMOS transistor, and the cathode of the body diode of the third NMOS transistor is electrically connected to the drain of the third NMOS transistor. The source of the third NMOS transistor is also electrically connected to the source of the fourth NMOS transistor. The gate of the fourth NMOS transistor is subjected to a first voltage. The drain of the fourth NMOS transistor is electrically connected to the fourth pull-up circuit and is also electrically connected to the first data terminal through the serial data line. The anode of the body diode of the fourth NMOS transistor is electrically connected to the source of the fourth NMOS transistor, and the cathode of the body diode of the fourth NMOS transistor is electrically connected to the drain of the fourth NMOS transistor. The third Zener diode is electrically connected between the gate and source of the third NMOS transistor, and the fourth Zener diode is electrically connected between the gate and source of the fourth NMOS transistor.

10. The computer device according to any one of claims 1 to 9, characterized in that, The functional chip includes any one of a central processing unit, a power management chip, or a memory chip.

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