Adaptive termination and driving circuit of NVMe hard disk

Abstract

The utility model relates to data storage equipment technical field especially relates to a kind of self-adapting termination and driving circuit of NVMe hard disk, including main controller, multiple NVMe hard disk connectors, shared bus, dynamically configurable parallel termination and arbitration module;The main controller is connected multiple NVMe hard disk connectors by shared bus;Dynamically configurable parallel termination and arbitration module includes switchable termination resistance network and multiplexer;Shared bus has multi-branch topological structure, switchable termination resistance network is connected in series between the sending pin of main controller and the signal source end of this shared bus;The switchable termination resistance network includes multiple parallel impedance branch, and each impedance branch is formed by fixed value resistance and controlled switch device series connection;The data input end of multiplexer is connected to the receiving data line of each NVMe hard disk connector respectively, and the utility model can improve the signal integrity under multiple hard disk shared bus with simple hardware circuit structure.

Description

Technical Field

[0001] This utility model relates to the field of data storage device technology, and in particular to an adaptive termination and drive circuit for an NVMe hard drive. Background Technology

[0002] NVMe hard drives provide high-bandwidth storage via the PCIe bus; in specific application scenarios where controller pins or PCB routing space are limited, there is a design requirement to connect multiple hard drives using a multi-branch shared bus topology in order to achieve high-density, low-cost deployment.

[0003] However, this non-standard topology has inherent defects under high-speed signals: the signal will be severely reflected at the branch point due to impedance discontinuity, and multiple load changes will further degrade the signal integrity, leading to eye diagram closure, increased bit error rate, and difficulty in meeting the electrical specification requirements of PCIe links.

[0004] Existing technical solutions mostly focus on protocol switching, controller algorithms, or SSD internal architecture optimization, such as implementing interface protocol adaptation through logic circuits or improving controller scheduling strategies.

[0005] None of these methods address the fundamental problem of signal reflection and crosstalk caused by using the aforementioned non-standard topology by starting with the physical circuit construction on the host side.

[0006] Therefore, it is necessary to provide an innovative hardware circuit structure to overcome the electrical defects of multi-branch topologies and expand the reliable application scenarios of the PCIe bus under the specific design requirements. Utility Model Content

[0007] The technical problem to be solved by this utility model is to overcome the existing defects and provide an adaptive termination and drive circuit for NVMe hard drives. By connecting a switchable resistor network in series at the transmitting end of the main controller to dynamically match the impedance and suppress signal reflection, and by using a multiplexer to arbitrate the receiving channels of each hard drive at the receiving end, the signal integrity under a shared bus of multiple hard drives is improved with a simple hardware circuit structure, which can effectively solve the problems in the background technology.

[0008] To achieve the above objectives, this utility model provides the following technical solution: an adaptive termination and drive circuit for NVMe hard drives, including a main controller, multiple NVMe hard drive connectors, a shared bus, and a dynamically configurable parallel termination and arbitration module;

[0009] The main controller is connected to multiple NVMe hard drive connectors via a shared bus.

[0010] The dynamically configurable parallel termination and arbitration module includes a switchable termination resistor network and a multiplexer; the shared bus has a multi-branch topology, and the switchable termination resistor network is connected in series between the transmit pin of the main controller and the signal source terminal of the shared bus to provide selectable source-end matching impedance; the switchable termination resistor network includes multiple parallel impedance branches, each impedance branch is formed by a fixed resistor and a controlled switching device connected in series; wherein, the resistance values ​​of each fixed resistor are different, and the control terminals of each switching device are respectively connected to the general-purpose input / output pins of the main controller;

[0011] The data input terminals of the multiplexer are connected to the receive data lines of each NVMe hard drive connector, the control terminal of the multiplexer is connected to the main controller, and the output terminal of the multiplexer is connected to the receive pin of the main controller.

[0012] Preferably, the switching device includes an NMOS switch, a gate discharge resistor, and a ringing suppression resistor;

[0013] In the switchable termination resistor network, one end of the fixed resistor of each impedance branch is connected to the first node, and the other end is connected to the drain of the corresponding NMOS switch. The source of the NMOS switch is connected to the second node, and its gate is connected to the general-purpose input / output pin of the main controller after being connected in series with a ringing suppression resistor as the control terminal. The gate discharge resistor is connected between the gate and the source.

[0014] Preferably, the multiplexer is an analog switch integrated circuit with multiple differential input channels and one differential common output channel; each of its differential input channels is correspondingly connected to the receiving differential line pair of each NVMe hard disk connector; its address selection pin is connected to the main controller to receive the channel selection signal.

[0015] Preferably, it also includes a signal quality detection module; the input terminal of the signal quality detection module is connected to the signal line between the transmit pin of the main controller and the switchable termination resistor network, and the output terminal is connected to the main controller; the main controller dynamically adjusts the on / off state of each switching device in the switchable termination resistor network according to the signal quality parameters output by the signal quality detection module.

[0016] Preferably, the signal quality detection module includes a high-speed comparator and a digital-to-analog converter;

[0017] One input of the high-speed comparator is connected to the signal line between the transmit pin of the main controller and the switchable termination resistor network, and the other input is connected to the output of the digital-to-analog converter. The input of the digital-to-analog converter is connected to the general-purpose input / output pin of the main controller for comparison with the actual signal voltage. The output of the high-speed comparator is connected to the interrupt pin or general-purpose input / output pin of the main controller.

[0018] Compared with the prior art, the beneficial effects of this utility model are: by using a switchable termination resistor network composed of multiple impedance branches with different resistance values ​​and controlled switching devices connected in parallel, and directly connecting it in series between the controller's transmit pin and the shared bus, the source end matching impedance can be dynamically adjusted according to the number of connected hard drives, effectively suppressing signal reflection under the multi-branch structure and improving the physical layer signal integrity.

[0019] By using an analog switch integrated circuit with multiple differential input channels as a multiplexer, its input terminals are connected point-to-point to the independent receiving lines of each hard drive, and its output terminal is connected to the receiving pin of the controller. Arbitration of multiple hard drive receiving channels is achieved with a simple hardware circuit structure, avoiding signal conflicts, and the wiring is clear and the cost is low. Attached Figure Description

[0020] Figure 1 This is a block diagram of the overall structure of this utility model;

[0021] Figure 2 This is a circuit diagram of the switchable termination resistor network of this utility model;

[0022] Figure 3 This is the circuit diagram of the multiplexer of this utility model. Detailed Implementation

[0023] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0024] Please see Figure 1-3 This utility model provides a technical solution: an adaptive termination and drive circuit for NVMe hard drives, including a main controller, multiple NVMe hard drive connectors, a shared bus, and a dynamically configurable parallel termination and arbitration module;

[0025] The main controller is connected to multiple NVMe hard drive connectors via a shared bus.

[0026] The dynamically configurable parallel termination and arbitration module includes a switchable termination resistor network and a multiplexer; the shared bus has a multi-branch topology, and the switchable termination resistor network is connected in series between the transmit pin of the main controller and the signal source terminal of the shared bus to provide selectable source-end matching impedance; the switchable termination resistor network includes multiple parallel impedance branches, each impedance branch is formed by a fixed resistor and a controlled switching device connected in series; wherein, the resistance values ​​of each fixed resistor are different, and the control terminals of each switching device are respectively connected to the general-purpose input / output pins of the main controller;

[0027] The data input terminals of the multiplexer are connected to the receive data lines of each NVMe hard drive connector, the control terminal of the multiplexer is connected to the main controller, and the output terminal of the multiplexer is connected to the receive pin of the main controller.

[0028] Specifically, in a preferred embodiment, the main controller is a system-on-a-chip or a dedicated processor with PCIe root complex functionality, such as a server CPU or storage controller chip based on ARM or x86 architecture.

[0029] In this embodiment, the main controller provides a PCIe channel, which includes a set of differential output pins for transmitting data, a set of differential input pins for receiving data, and multiple sets of general-purpose input / output pins.

[0030] Among them, the differential output pin for transmitting data serves as the sole signal source. Its output signal is impedance matched by the switchable termination resistor network in the subsequent stage, and then drives the shared bus with multi-branch topology to broadcast instructions and data to all connected NVMe hard drive connectors.

[0031] The differential input pin for receiving data is connected to the common output of the multiplexer to receive responses and data from any target NVMe hard drive after being selected by the main controller through the general-purpose input / output pins. The configuration of multiple sets of general-purpose input / output pins ensures that all switching devices in the switchable termination resistor network and the channel selection of the multiplexer can be independently controlled.

[0032] The shared bus consists of high-speed signal traces on the printed circuit board, conforming to the electrical specifications of the PCIe protocol. This bus is not a point-to-point topology but rather employs a multi-branch structure. Specifically, differential traces originating from the host controller's transmit pins extend on the printed circuit board, sequentially passing through or near each NVMe hard drive connector, forming a physically shared transmission channel. This channel serves solely as a common transmission channel for broadcasting signals from the host controller to all NVMe hard drive connectors, while the receive pins of each NVMe hard drive connector are connected via their respective independent receive signal traces.

[0033] The NVMe hard drive connector is a standardized M.2 interface connector used to connect NVMe solid-state drives; the transmit pin of each connector is connected to the shared bus via a short wire; its receive pin is connected to a separate receive signal trace.

[0034] In practical applications, the switchable termination resistor network of this utility model includes two switchable termination resistor network circuit modules with identical structures, independent of each other and symmetrically arranged, which correspond to the positive and negative terminals in the high-speed differential signal pair, respectively. Figure 2 Taking one of the paths as an example, the structure of a single switchable termination resistor network circuit module is illustrated.

[0035] A switchable termination resistor network contains multiple parallel impedance branches. Figure 2 It is shown as four branches, but the actual number can be increased according to design needs; the structure of each impedance branch is exactly the same.

[0036] The switching device includes an NMOS switch, a gate discharge resistor, and a ringing suppression resistor;

[0037] In the switchable termination resistor network, one end of the fixed resistor in each impedance branch is connected to a common first node, which is directly connected to the transmit pin of the main controller, and the other end is connected to the drain of the corresponding NMOS switch. In this embodiment, the fixed resistor is a high-precision, low-temperature drift surface-mount resistor, such as a thin-film resistor with an accuracy of ±1%. The resistance values ​​of the fixed resistors R1, R2, R3, and R4 in all branches are different, and are designed with typical values ​​such as 50Ω, 75Ω, 100Ω, and 200Ω, respectively, to combine different equivalent parallel impedances. For example, a 50Ω branch can be selected when connecting a single hard drive, and an equivalent impedance of close to 35Ω can be combined when connecting multiple hard drives to match load changes.

[0038] The source of the NMOS switch is connected to a common second node, which is directly connected to the positive or negative terminal of the transmit differential pair of the shared bus (shown as single-ended in the figure). To ensure stable and reliable switching operation and avoid gate voltage oscillation and electrostatic damage, two necessary external resistors are set on the gate control circuit of the NMOS switch: a ringing suppression resistor and a gate discharge resistor.

[0039] The ringing suppression resistor has a small resistance value (e.g., 50Ω) and is connected in series between the gate and the general-purpose input / output control line from the main controller. It is used to dampen the ringing generated on the gate parasitic capacitance and lead inductance when the control signal changes rapidly, so as to ensure a clean switching waveform.

[0040] Its resistance is relatively large (e.g., 50kΩ), and it is connected between the gate and the source. When the general-purpose input / output control line is in a high-impedance state, this resistor can provide a discharge path for the gate charge, ensuring that the NMOS transistor is reliably turned off, and at the same time, it has a certain electrostatic discharge protection function.

[0041] The gates of NMOS transistors Q1, Q2, Q3, and Q4 in each branch are connected to different general-purpose input / output pins on the main controller through their respective ringing suppression resistors R9, R10, R11, and R12.

[0042] Specifically, the main controller, driven by software, controls different general-purpose input / output pins to output high or low levels based on the number of connected hard drives detected by the system or signal quality feedback. For example, when only one hard drive is connected, only the branch with R1 = 50Ω may be turned on; when two hard drives are connected, the branches with R1 = 50Ω and R2 = 75Ω may be turned on simultaneously. The parallel equivalent impedance of the two is about 30Ω, thereby dynamically matching the transmission line impedance that changes due to the increase in load and suppressing signal reflection.

[0043] Furthermore, the multiplexer is an analog switch integrated circuit with multiple differential input channels and one differential common output channel; each of its differential input channels is correspondingly connected to the receiving differential line pair of each NVMe hard disk connector; its address selection pin is connected to the main controller to receive the channel selection signal.

[0044] Specifically, in this embodiment, the multiplexer is implemented using an analog switch integrated circuit with four differential input channels and one differential common output channel. The specific model can be a chip designed for high-speed differential signal switching, featuring high bandwidth, low crosstalk, and low insertion loss.

[0045] The multiplexer has four differential input channels (1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B); the positive and negative input terminals of each differential input channel are connected to the corresponding NVMe hard drive connector's differential receive line pair via their own independent receive signal traces. The multiplexer routes the receive signal from the selected hard drive to the main controller by selecting one of these independent input channels.

[0046] The common differential output channel of the multiplexer has its positive and negative output terminals directly connected back to the receive pins of the main controller. The multiplexer has multiple address selection pins S0 and S1, which are connected to another set of general-purpose input / output pins of the main controller. By sending specific binary encoded signals to these address selection pins, the main controller can select one of the four input channels and conduct its differential signal to the common output channel, thereby sending the received data from the selected hard drive to the main controller.

[0047] To achieve closed-loop adaptive impedance matching, this invention further integrates a signal quality detection module. This module is an independent hardware circuit whose core function is to monitor the signal quality at the sampling node located between the main controller's transmit pin and the first node of the switchable termination resistor network in real time, and to feed the detection results back to the main controller.

[0048] The signal quality detection module mainly consists of a high-speed comparator and a digital-to-analog converter;

[0049] One input of the high-speed comparator is connected via a small coupling capacitor (not shown in the figure, used to isolate DC bias) to the signal line between the transmit pin of the main controller and the first node of the switchable termination resistor network, for sampling the actual transmitted signal. The other input is connected to the analog voltage output of the digital-to-analog converter (DAC). The input of the DAC is connected to the general-purpose input / output pin of the main controller. The main controller can programmatically set the DAC to output a precise reference voltage, which represents the threshold of allowable signal quality (such as the maximum allowable overshoot voltage). The high-speed comparator will continuously compare the sampled signal with the reference voltage. When the sampled signal quality deteriorates and its overshoot peak exceeds the reference voltage, the output level of the high-speed comparator will jump. The output of the high-speed comparator is connected to the interrupt pin or general-purpose input / output pin of the main controller to send a hardware interrupt signal to the main controller.

[0050] Upon receiving this interrupt, the main controller dynamically adjusts the on / off combinations of the corresponding switching devices in the switchable termination resistor network through its general-purpose input / output pins, thereby changing the parallel equivalent impedance value. After adjustment, the system monitors the signal quality again. Through this hardware closed loop, the circuit can automatically find the optimal source-end matching impedance under the current load conditions.

[0051] This connection enables the signal quality detection module to work in conjunction with the switchable termination resistor network and the main controller, maintaining signal integrity and improving the overall reliability and stability of the system during multiple hard drive hot-swapping or changes in operating status.

[0052] The circuit described in this solution is specifically implemented on a printed circuit board; the main controller chip, the dynamically configurable parallel termination and arbitration module, and multiple NVMe hard drive connectors are all soldered on this circuit board.

[0053] In this configuration, all resistors and switching transistors of the switchable termination resistor network are tightly arranged within 0.5 mm of the main controller's PCIe transmit pin pads; the common output differential pin of the multiplexer chip is directly connected to the main controller's PCIe receive pin pads via differential traces of equal length not exceeding 3 mm; the coupling capacitor and high-speed comparator input pin of the signal quality detection module are connected to the signal line between the main controller's transmit pin and the first node of the switchable termination resistor network via the shortest path.

[0054] The shared bus transmit signal lines from the switchable termination resistor network output to each hard disk connector are routed in a tree topology with equal lengths. The receive pins of each hard disk connector are directly connected to the corresponding input of the multiplexer in a point-to-point manner through their own independent differential traces. This layout structure ensures signal integrity and impedance controllability, constituting the specific physical product form of this utility model.

[0055] The working principle of this utility model is to achieve adaptive signal processing through a module composed of a switchable termination resistor network and a multiplexer.

[0056] The main controller controls the switching of multiple parallel branches in the terminating resistor network through its general purpose input / output pins, thereby dynamically adjusting the equivalent source impedance of the output to the shared bus to match the load impedance changes caused by the change in the number of connected hard drives and suppress signal reflection.

[0057] In the receiving path, each hard drive receiving line is connected to the input terminal of the multiplexer. The main controller selects the receiving channel of the target hard drive to the controller receiving pin by controlling its address selection pin, thus completing the signal receiving arbitration.

[0058] The working principle of this utility model is as follows: when in use, the transmit pins of multiple hard drives are connected in parallel to the shared bus brought out by the main controller.

[0059] When the system initializes or detects a change in hard drive status, the main controller controls the terminal resistor network switch according to the number of connected hard drives to configure a matching source impedance.

[0060] During data transmission, controller commands are broadcast via the shared bus; when data needs to be received, the controller multiplexer selects the receiving channel for the corresponding hard drive.

[0061] The signal quality detection module can sample and provide feedback on the transmitted signal, which is then used by the main controller for closed-loop fine-tuning of impedance configuration to ensure signal integrity.

Claims

1. An adaptive termination and drive circuit for NVMe hard drives, comprising a main controller, multiple NVMe hard drive connectors, a shared bus, and a dynamically configurable parallel termination and arbitration module, characterized in that: The main controller is connected to multiple NVMe hard drive connectors via a shared bus. The dynamically configurable parallel termination and arbitration module includes a switchable termination resistor network and a multiplexer; the shared bus has a multi-branch topology, and the switchable termination resistor network is connected in series between the transmit pin of the main controller and the signal source terminal of the shared bus to provide selectable source-end matching impedance; the switchable termination resistor network includes multiple parallel impedance branches, each impedance branch is formed by a fixed resistor and a controlled switching device connected in series; wherein, the resistance values ​​of each fixed resistor are different, and the control terminals of each switching device are respectively connected to the general-purpose input / output pins of the main controller; The data input terminals of the multiplexer are connected to the receive data lines of each NVMe hard drive connector, the control terminal of the multiplexer is connected to the main controller, and the output terminal of the multiplexer is connected to the receive pin of the main controller.

2. The adaptive termination and drive circuit for an NVMe hard drive according to claim 1, characterized in that: The switching device includes an NMOS switch, a gate discharge resistor, and a ringing suppression resistor; In the switchable termination resistor network, one end of the fixed resistor of each impedance branch is connected to the first node, and the other end is connected to the drain of the corresponding NMOS switch. The source of the NMOS switch is connected to the second node, and its gate is connected to the general-purpose input / output pin of the main controller after being connected in series with a ringing suppression resistor as the control terminal. The gate discharge resistor is connected between the gate and the source.

3. The adaptive termination and drive circuit for an NVMe hard drive according to claim 1, characterized in that: The multiplexer is an analog switch integrated circuit with multiple differential input channels and one differential common output channel; Each of its differential input channels is correspondingly connected to the receiving differential line pair of each NVMe hard drive connector; Its address selection pin is connected to the main controller to receive the channel strobe signal.

4. The adaptive termination and drive circuit for an NVMe hard drive according to claim 1, characterized in that: It also includes a signal quality detection module; the input terminal of the signal quality detection module is connected to the signal line between the transmit pin of the main controller and the switchable termination resistor network, and the output terminal is connected to the main controller; the main controller dynamically adjusts the on / off state of each switching device in the switchable termination resistor network according to the signal quality parameters output by the signal quality detection module.

5. The adaptive termination and drive circuit for an NVMe hard drive according to claim 4, characterized in that: The signal quality detection module includes a high-speed comparator and a digital-to-analog converter; One input of the high-speed comparator is connected to the signal line between the transmit pin of the main controller and the switchable termination resistor network, and the other input is connected to the output of the digital-to-analog converter. The input of the digital-to-analog converter is connected to the general-purpose input / output pin of the main controller for comparison with the actual signal voltage. The output of the high-speed comparator is connected to the interrupt pin or general-purpose input / output pin of the main controller.

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