An iis bus timing adjustment circuit

Abstract

The utility model relates to a kind of IIS bus timing adjustment circuit, including DSP host computer, and at least one ADC slave and DAC slave, and MCLK, BCLK, LRCK three clock lines, the one end of MCLK clock line is connected with host computer, and its other end is connected with ADC slave, DAC slave respectively;The one end of BCLK clock line is connected with host computer, and its other end is connected with ADC slave, DAC slave respectively;The one end of LRCK clock line is connected with host computer, and its other end is connected with ADC slave, DAC slave respectively;And the timing adjustment unit connected with the MCLK, BCLK, LRCK three clock lines respectively, the timing adjustment unit is used to generate advance or lag phase.The utility model is in three clock lines respectively parallel adjustable capacitor and adjustable resistance, and cooperate switch to realize lag or advance phase adjustment, to compensate the step-out problem of clock to data caused by PCB and wire distribution parameter;The circuit does not need active device, cost is low, power consumption is zero, applicable to various high fidelity audio equipment.

Description

Technical Field

[0001] This utility model relates to the field of digital audio data technology, and in particular to an IIS bus timing adjustment circuit. Background Technology

[0002] In audio processing systems, the main control DSP transmits audio data to the ADC and DAC via the IIS bus. The IIS standard protocol has strict setup / hold time requirements for MCLK (master clock), BCLK (bit clock), and LRCK (left and right channel clocks). However, parasitic parameters such as PCB traces, wire capacitance / inductance, and connector impedance can cause phase shifts between the clock and data, resulting in sampling errors and ultimately producing noises such as "clicks" and "pops" at the analog output.

[0003] In the prior art, in order to solve the above problems, a programmable delay unit is usually added inside the DSP. However, this method requires valuable logic resources and increases power consumption and cost. Clock buffers / PLLs can also be used to regenerate the clock, but they are active devices, which will lead to circuit complexity, EMI, and high cost. In addition, the PCB trace length can be manually modified, but this will result in a long board adjustment cycle, cannot adapt to the differences in traces between different batches, and is not suitable for mass production.

[0004] Therefore, there is an urgent need to propose a low-cost, passive, and online adjustable IIS timing adjustment circuit. Utility Model Content

[0005] Based on this, the purpose of this utility model is to overcome the defects or deficiencies of the prior art and provide an IIS bus timing adjustment circuit.

[0006] An IIS bus timing adjustment circuit includes a DSP master, at least one ADC slave and one DAC slave, and MCLK, BCLK, and LRCK clock lines. One end of the MCLK clock line is connected to the master, and the other end is connected to the ADC slave and the DAC slave, respectively. One end of the BCLK clock line is connected to the master, and the other end is connected to the ADC slave and the DAC slave, respectively. One end of the LRCK clock line is connected to the master, and the other end is connected to the ADC slave and the DAC slave, respectively. A timing adjustment unit is connected to the MCLK, BCLK, and LRCK clock lines, respectively. The timing adjustment unit is used to generate a leading or lagging phase.

[0007] In one embodiment, the timing adjustment unit includes a first adjustable capacitor C1, a second adjustable capacitor C2, a third adjustable capacitor C3, and a first switch S1. One end of the first adjustable capacitor C1 is connected to the MCLK clock line, and the other end is connected to the first switch S1. One end of the second adjustable capacitor C2 is connected to the BCLK clock line, and the other end is connected to the first switch S1. One end of the third adjustable capacitor C3 is connected to the LRCK clock line, and the other end is connected to the first switch S1. One end of the first switch S1 is connected to the first adjustable capacitor C1, the second adjustable capacitor C2, and the third adjustable capacitor C3, and the other end is grounded.

[0008] In one embodiment, the timing adjustment unit includes a first adjustable resistor R1, a second adjustable resistor R2, a third adjustable resistor R3, and a second switch S2. One end of the first adjustable resistor R1 is connected to the MCLK clock line, and the other end is connected to the second switch S2. One end of the second adjustable resistor R2 is connected to the BCLK clock line, and the other end is connected to the second switch S2. One end of the third adjustable resistor R3 is connected to the LRCK clock line, and the other end is connected to the second switch S2. One end of the second switch S2 is connected to the first adjustable resistor R1, the second adjustable resistor R2, and the third adjustable resistor R3, and the other end is grounded.

[0009] In one embodiment, the timing adjustment unit includes a first adjustable capacitor C1, a second adjustable capacitor C2, a third adjustable capacitor C3, and a first switch S1. One end of the first adjustable capacitor C1 is connected to the MCLK clock line, and its other end is connected to the first switch S1. One end of the second adjustable capacitor C2 is connected to the BCLK clock line, and its other end is connected to the first switch S1. One end of the third adjustable capacitor C3 is connected to the LRCK clock line, and its other end is connected to the first switch S1. One end of the first switch S1 is connected to the first adjustable capacitor C1, the second adjustable capacitor C2, and the third adjustable capacitor C3, respectively. The other end is grounded; further, it also includes a first adjustable resistor R1, a second adjustable resistor R2, a third adjustable resistor R3, and a second switch S2, wherein one end of the first adjustable resistor R1 is connected to the MCLK clock line, and the other end is connected to the second switch S2; one end of the second adjustable resistor R2 is connected to the BCLK clock line, and the other end is connected to the second switch S2; one end of the third adjustable resistor R3 is connected to the LRCK clock line, and the other end is connected to the second switch S2; one end of the second switch S2 is connected to the first adjustable resistor R1, the second adjustable resistor R2, and the third adjustable resistor R3 respectively, and the other end is grounded.

[0010] In one embodiment, the first switch S1 and the second switch S2 are any one of a DIP switch, a jumper cap, or a 0 Ω resistor pad.

[0011] In one embodiment, the values ​​of the first adjustable capacitor C1, the second adjustable capacitor C2, and the third adjustable capacitor C3 are in the range of 2 pF to 60 pF, and the values ​​of the first adjustable resistor R1, the second adjustable resistor R2, and the third adjustable resistor R3 are in the range of 0 Ω to 10 kΩ.

[0012] In one embodiment, a damping resistor R0 is connected in series on each of the MCLK clock line, BCLK clock line, and LRCK clock line.

[0013] In one embodiment, the resistance value of the damping resistor R0 is in the range of 0 Ω to 33 Ω.

[0014] To better understand and implement this invention, the following detailed description is provided in conjunction with the accompanying drawings. Attached Figure Description

[0015] Figure 1 A schematic diagram of the IIS bus timing adjustment circuit provided by this utility model. Detailed Implementation

[0016] The present invention will now be described in detail with reference to the accompanying drawings.

[0017] like Figure 1 As shown, an IIS bus timing adjustment circuit of this utility model includes a DSP host, at least one ADC slave and DAC slave, and MCLK clock lines, BCLK clock lines, and LRCK clock lines. One end of the MCLK clock line is connected to the host, and the other end is connected to the ADC slave and DAC slave respectively. One end of the BCLK clock line is connected to the host, and the other end is connected to the ADC slave and DAC slave respectively. One end of the LRCK clock line is connected to the host, and the other end is connected to the ADC slave and DAC slave respectively. A timing adjustment unit is connected to the MCLK clock line, BCLK clock line, and LRCK clock line respectively. The timing adjustment unit is used to generate a leading or lagging phase.

[0018] The ADC slave is used to convert analog audio signals into digital signals; the DAC slave is used to convert digital audio signals into analog audio signals; in this application, two ADC slaves and two DAC slaves are used, namely the first ADC slave ADC1, the second ADC slave ADC2, the first DAC slave DAC1, and the second DAC slave DAC2.

[0019] Furthermore, it also includes an active crystal oscillator Y connected to the DSP host, which can directly output a stable, low-jitter square wave or sine wave clock signal when connected to an external rated power supply.

[0020] In one embodiment, the timing adjustment unit includes a first adjustable capacitor C1, a second adjustable capacitor C2, a third adjustable capacitor C3, and a first switch S1. One end of the first adjustable capacitor C1 is connected to the MCLK clock line, and the other end is connected to the first switch S1. One end of the second adjustable capacitor C2 is connected to the BCLK clock line, and the other end is connected to the first switch S1. One end of the third adjustable capacitor C3 is connected to the LRCK clock line, and the other end is connected to the first switch S1. One end of the first switch S1 is connected to the first adjustable capacitor C1, the second adjustable capacitor C2, and the third adjustable capacitor C3, and the other end is grounded.

[0021] Turn on the first switch S1 and adjust the capacitance values ​​of the first adjustable capacitor C1, the second adjustable capacitor C2, and the third adjustable capacitor C3 respectively. This allows for fine-tuning of the timing of the corresponding clock lines. When the capacitance value of the adjustable capacitor is larger, the RC delay of the clock signal to ground increases, resulting in a delay in the time it takes for the clock edge to reach the slave device. When the capacitance value of the adjustable capacitor is smaller, the RC delay of the clock signal to ground decreases, resulting in an earlier time it takes for the clock edge to reach the slave device.

[0022] In one embodiment, the timing adjustment unit includes a first adjustable resistor R1, a second adjustable resistor R2, a third adjustable resistor R3, and a second switch S2. One end of the first adjustable resistor R1 is connected to the MCLK clock line, and the other end is connected to the second switch S2. One end of the second adjustable resistor R2 is connected to the BCLK clock line, and the other end is connected to the second switch S2. One end of the third adjustable resistor R3 is connected to the LRCK clock line, and the other end is connected to the second switch S2. One end of the second switch S2 is connected to the first adjustable resistor R1, the second adjustable resistor R2, and the third adjustable resistor R3, and the other end is grounded.

[0023] Turn on the second switch S2 and adjust the capacitance values ​​of the first adjustable resistor R1, the second adjustable resistor R2, and the third adjustable resistor R3 respectively. This allows for fine-tuning of the timing of the corresponding clock lines. The larger the resistance value of the adjustable resistor, the greater the RC delay of the clock signal to ground, which in turn causes the clock edge to arrive at the slave device later. The smaller the resistance value of the adjustable resistor, the smaller the RC delay of the clock signal to ground, which in turn causes the clock edge to arrive at the slave device earlier.

[0024] In one embodiment, the timing adjustment unit includes a first adjustable capacitor C1, a second adjustable capacitor C2, a third adjustable capacitor C3, and a first switch S1. One end of the first adjustable capacitor C1 is connected to the MCLK clock line, and its other end is connected to the first switch S1. One end of the second adjustable capacitor C2 is connected to the BCLK clock line, and its other end is connected to the first switch S1. One end of the third adjustable capacitor C3 is connected to the LRCK clock line, and its other end is connected to the first switch S1. One end of the first switch S1 is connected to the first adjustable capacitor C1, the second adjustable capacitor C2, and the third adjustable capacitor C3, respectively. The other end is grounded; further, it also includes a first adjustable resistor R1, a second adjustable resistor R2, a third adjustable resistor R3, and a second switch S2, wherein one end of the first adjustable resistor R1 is connected to the MCLK clock line, and the other end is connected to the second switch S2; one end of the second adjustable resistor R2 is connected to the BCLK clock line, and the other end is connected to the second switch S2; one end of the third adjustable resistor R3 is connected to the LRCK clock line, and the other end is connected to the second switch S2; one end of the second switch S2 is connected to the first adjustable resistor R1, the second adjustable resistor R2, and the third adjustable resistor R3 respectively, and the other end is grounded.

[0025] The first switch S1 and the second switch S2 can be turned on simultaneously, and the capacitance values ​​of the first adjustable capacitor C1, the second adjustable capacitor C2, and the third adjustable capacitor C3, as well as the capacitance values ​​of the first adjustable resistor R1, the second adjustable resistor R2, and the third adjustable resistor R3, can be adjusted respectively to fine-tune the timing of the corresponding clock lines. When the capacitance value of the adjustable capacitor is larger and the resistance value of the adjustable resistor is larger, the RC delay formed by the clock signal to ground increases, which in turn causes the clock edge to arrive at the slave end with a time lag. When the capacitance value of the adjustable capacitor is smaller and the resistance value of the adjustable resistor is smaller, the RC delay formed by the clock signal to ground decreases, which in turn causes the clock edge to arrive at the slave end earlier.

[0026] In this application, the clock frequency of the MCLK clock line is 24.576MHz; the clock frequency of the BCLK clock line is 12.288MHz; and the clock frequency of the LRCK clock line is 48KHz.

[0027] In this application, the first switch S1 and the second switch S2 are any one of a DIP switch, a jumper cap, or a 0 Ω resistor pad.

[0028] In this application, the adjustable capacitor has a value range of 2 pF to 60 pF, and the adjustable resistor has a value range of 0 Ω to 10 kΩ.

[0029] Furthermore, damping resistors (not shown in the figure) are connected in series on the MCLK clock line, BCLK clock line, and LRCK clock line respectively; in this application, the resistance value of the damping resistors ranges from 0 Ω to 33 Ω.

[0030] Compared to existing technologies, this invention uses adjustable capacitors and adjustable resistors connected in parallel on the three clock lines MCLK, BCLK, and LRCK, and a switch to achieve lag or lead phase adjustment, thereby compensating for the clock-to-data synchronization problem caused by the distribution parameters of the PCB and wiring. This circuit requires no active components, has low cost and zero power consumption, and can be quickly adjusted after the entire device is assembled, making it suitable for various high-fidelity audio devices.

[0031] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this application. The singular forms “a,” “the,” and “the” used in the embodiments and claims of this application are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that, unless otherwise stated, “a plurality” means two or more; the terms “first,” “second,” “third,” etc., are used only to distinguish and not to describe a particular order or sequence, nor should they be construed as indicating or implying relative importance. The term “and / or” as used herein refers to and includes any or all possible combinations of one or more associated listed items. When the above description relates to drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. In the description of this application, those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0032] The embodiments described above are merely examples of several implementations of this utility model, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these modifications and improvements all fall within the protection scope of this utility model.

Claims

1. An IIS bus timing adjustment circuit, characterized in that, include: DSP host, and at least one ADC slave and one DAC slave, The system includes MCLK clock line, BCLK clock line, and LRCK clock line. One end of the MCLK clock line is connected to the host, and the other end is connected to the ADC slave and DAC slave, respectively. One end of the BCLK clock line is connected to the host, and the other end is connected to the ADC slave and DAC slave, respectively. One end of the LRCK clock line is connected to the host, and the other end is connected to the ADC slave and DAC slave, respectively. And timing adjustment units connected to the MCLK clock line, BCLK clock line and LRCK clock line respectively, the timing adjustment units being used to generate lead or lag phases.

2. The IIS bus timing adjustment circuit according to claim 1, characterized in that: The timing adjustment unit includes a first adjustable capacitor (C1), a second adjustable capacitor (C2), a third adjustable capacitor (C3), and a first switch (S1). One end of the first adjustable capacitor (C1) is connected to the MCLK clock line, and the other end is connected to the first switch (S1). One end of the second adjustable capacitor (C2) is connected to the BCLK clock line, and the other end is connected to the first switch (S1). One end of the third adjustable capacitor (C3) is connected to the LRCK clock line, and the other end is connected to the first switch (S1). One end of the first switch (S1) is connected to the first adjustable capacitor (C1), the second adjustable capacitor (C2), and the third adjustable capacitor (C3), respectively, and the other end is grounded.

3. The IIS bus timing adjustment circuit according to claim 1, characterized in that: The timing adjustment unit includes a first adjustable resistor (R1), a second adjustable resistor (R2), a third adjustable resistor (R3), and a second switch (S2). One end of the first adjustable resistor (R1) is connected to the MCLK clock line, and the other end is connected to the second switch (S2). One end of the second adjustable resistor (R2) is connected to the BCLK clock line, and the other end is connected to the second switch (S2). One end of the third adjustable resistor (R3) is connected to the LRCK clock line, and the other end is connected to the second switch (S2). One end of the second switch (S2) is connected to the first adjustable resistor (R1), the second adjustable resistor (R2), and the third adjustable resistor (R3), and the other end is grounded.

4. The IIS bus timing adjustment circuit according to claim 1, characterized in that: The timing adjustment unit includes a first adjustable capacitor (C1), a second adjustable capacitor (C2), a third adjustable capacitor (C3), and a first switch (S1). One end of the first adjustable capacitor (C1) is connected to the MCLK clock line, and the other end is connected to the first switch (S1). One end of the second adjustable capacitor (C2) is connected to the BCLK clock line, and the other end is connected to the first switch (S1). One end of the third adjustable capacitor (C3) is connected to the LRCK clock line, and the other end is connected to the first switch (S1). One end of the first switch (S1) is connected to the first adjustable capacitor (C1), the second adjustable capacitor (C2), and the third adjustable capacitor (C3), respectively, and the other end is grounded. It also includes a first adjustable resistor (R1), a second adjustable resistor (R2), a third adjustable resistor (R3), and a second switch (S2). One end of the first adjustable resistor (R1) is connected to the MCLK clock line, and the other end is connected to the second switch (S2). One end of the second adjustable resistor (R2) is connected to the BCLK clock line, and the other end is connected to the second switch (S2). One end of the third adjustable resistor (R3) is connected to the LRCK clock line, and the other end is connected to the second switch (S2). One end of the second switch (S2) is connected to the first adjustable resistor (R1), the second adjustable resistor (R2), and the third adjustable resistor (R3), and the other end is grounded.

5. The IIS bus timing adjustment circuit according to claim 4, characterized in that: The first switch S1 and the second switch S2 are any one of a DIP switch, a jumper cap, or a 0 Ω resistor pad.

6. The IIS bus timing adjustment circuit according to any one of claims 2, 4, and 5, characterized in that: The values ​​of the first adjustable capacitor C1, the second adjustable capacitor C2, and the third adjustable capacitor C3 range from 2 pF to 60 pF.

7. The IIS bus timing adjustment circuit according to any one of claims 3, 4, and 5, characterized in that: The values ​​of the first adjustable resistor R1, the second adjustable resistor R2, and the third adjustable resistor R3 are in the range of 0 Ω to 10k Ω.

8. The IIS bus timing adjustment circuit according to any one of claims 2 to 5, characterized in that: Damping resistors R0 are connected in series on the MCLK clock line, BCLK clock line, and LRCK clock line, respectively.

9. The IIS bus timing adjustment circuit according to claim 8, characterized in that: The resistance value of the damping resistor R0 is in the range of 0 Ω to 33 Ω.

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