Dual-master control structure, mainboard and electronic product

Abstract

The application relates to the technical field of dual-master controller control, in particular to a dual-master controller control structure, a mainboard and an electronic product, the dual-master controller control structure comprising a master device module and a control module; the master device module comprising a first master controller and a second master controller; the control module comprising a switch and a controller, the switch being connected with the first master controller and the second master controller through a system management bus, and the switch being connected with a slave device through the system management bus; the controller being connected with the switch, the controller detecting a level pulse signal output by a first port of the first master controller and a second port of the second master controller, and controlling the switch to switch based on the level pulse signal. The application takes the level pulse signal as a judgment basis to determine autonomous switching between the master controllers, improves the flexibility of the work between the devices, ensures the operation of one master controller based on the switching condition, the control mode is simple, signal conflicts can be avoided, and better signal quality is provided.

Description

Technical Field

[0001] This application relates to the field of dual-master controller technology, and in particular to a dual-master controller structure, motherboard and electronic product. Background Technology

[0002] In electronic products, a typical complex motherboard includes multiple I / O pins. 2 The host controller channel, for example, an embedded controller (EC) typically has 4 I / O channels. 2 C main controller channel; Central Processing Unit (CPU) up to 8-way I / O 2 C main controller channel; Graphics Processing Unit (GPU) typically has 2 I / O channels. 2 C is the main controller channel; where I 2 The slave devices of the C master controller channel include temperature sensors, touchpads, and power supply components, etc. The slave devices communicate via I... 2 The C-channel of the main controller is connected to the main controller, thereby enabling the corresponding functions.

[0003] Electronic products with dual master controllers are high-performance products. The two master controllers switch according to the timing sequence. After a certain period of time after power-on, the initiative between the two master controllers is exchanged, with one master controller becoming a slave device and the other master controller running.

[0004] However, the scenarios of dual-master control are becoming increasingly flexible. Controlling by timing means that one master controller works and the other becomes a slave device within a certain period of time. This control method cannot meet the requirements of autonomous switching between dual master controllers and instantaneous response required by the system management bus. Summary of the Invention

[0005] To address at least the above-mentioned technical problems existing in the prior art, this application provides a dual-master controller structure, a motherboard, and an electronic product.

[0006] This application provides a dual-master controller structure, including a master control device module and a control module; the master control device module includes a first master controller and a second master controller; the control module includes a switch and a controller, the switch is connected to the first master controller and the second master controller via a system management bus, and the switch is also connected to a slave device via the system management bus; the controller is connected to the switch, and the controller detects the level pulse signals output from the first port of the first master controller and the second port of the second master controller, and controls the switch to switch based on the level pulse signals.

[0007] In some embodiments, the first master controller and the second master controller each include a comparison module and an information generation module; the comparison module compares output level information and actual level information, the output level information being the level information of the data bit sequence sent by the first master controller or the second master controller to the system management bus, and the actual level information being the current level information of the system management bus; the information generation module generates a level pulse signal based on the level comparison result of the comparison module and outputs it to the controller.

[0008] In some embodiments, when the output level information of the first master controller and the second master controller are consistent with the actual level information, the controller controls the switching switch to disconnect, or controls the switching switch to connect the first master controller or the second master controller to the slave device.

[0009] In some embodiments, when both the output level information and the actual level information are high, the controller controls the switching switch to disconnect; when both the output level information and the actual level information are low, the controller controls the switching switch to connect the first master controller or the second master controller to the slave device.

[0010] In some embodiments, the output level information and actual level information of the first master controller and the second master controller are inconsistent. The controller controls the switching switch to connect the first master controller to the slave device, or controls the switching switch to connect the second master controller to the slave device.

[0011] In some embodiments, the actual voltage level of the first master controller is low and the actual voltage level of the second master controller is high, and the controller controls the switching switch to connect the first master controller to the slave device; or the actual voltage level of the first master controller is high and the actual voltage level of the second master controller is low, and the controller controls the switching switch to connect the second master controller to the slave device.

[0012] In some embodiments, the switch connects the first master controller to the slave device, and the controller sends a level indication signal indicating that it is waiting to be released to the second master controller; the switch connects the second master controller to the slave device, and the controller sends a level indication signal indicating that it is waiting to be released to the first master controller.

[0013] In some embodiments, the switching switch includes a multiplexer.

[0014] This application also provides a motherboard that includes the aforementioned dual-master controller structure.

[0015] In another aspect, this application also provides an electronic product, including the above-described dual-master controller structure or including the above-described motherboard.

[0016] This application provides a dual-master controller control structure, motherboard, and electronic product. The first and second master controllers generate level pulse signals by detecting output and actual level information. The controller controls a switching switch to switch between the first and second master controllers based on these level pulse signals, thus granting either the first or second master controller bus control rights. This technical solution, using level pulse signals as a criterion to determine the switching between master controllers, enables autonomous switching, improves the flexibility of operation between devices, and ensures that only one master controller operates based on switching conditions. The control method is simple and avoids signal conflicts, providing superior signal quality. Attached Figure Description

[0017] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which: In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0018] Figure 1 A schematic diagram of a dual-master controller control structure provided in an embodiment of this application; Figure 2 Another schematic diagram of the dual-master controller control structure provided in the embodiments of this application; Figure 3 The circuit diagram of the switching switch in the dual master controller control structure provided in the embodiments of this application.

[0019] In the picture: 10: Main control module; 20: Control module; 3: Slave module; 11: First main controller; 12: Second main controller; 21: Controller; 22: Switch. Detailed Implementation

[0020] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] This application provides a dual-master control structure, including a master control module, a control module, and slave devices. The master control module includes a first master controller and a second master controller, i.e., a dual-master structure. The control module includes a controller and a switching switch. The slave devices include various types of slave devices. The controller controls the switching switch to switch according to the level pulse signals sent by the dual-master structure, which differs from the timing control switching in the prior art.

[0022] The following, in conjunction with the accompanying drawings, provides a detailed description of each module of the dual-master controller structure provided in the embodiments of this application, as well as the positional and connection relationships between the modules.

[0023] like Figure 1 As shown in the embodiment of this application, the control module 20 is located between the master control device module 10 and the slave device 30. The master controller in the master control device module 10 needs to send request information to the control module 20. The request information is a level pulse signal. The control module 20 controls a master controller to connect with the slave device 30 based on the request information.

[0024] The main control device module 10 includes two main controllers, namely the first main controller 11 and the second main controller 12. The control module 20 includes a controller 22 and a switch 21. The slave device 30 includes slave devices such as temperature sensors, touchpads, or power supply components.

[0025] Based on the request information (level pulse signal) sent by the first master controller 11 and the second master controller 12, the controller 22 controls the switch 21 to switch, giving one of the master controllers bus control rights. Specifically: [Example:] Figure 2 As shown in the embodiment of this application, the main control device module 10 includes a first main controller 11 and a second main controller 12; the control module 20 includes a switch 21 and a controller 22. The switch 21 is connected to the first main controller 11 and the second main controller 12 through a system management bus, and the switch 21 is also connected to the slave device 30 through the system management bus; the controller 22 is connected to the switch 21, and the controller 22 detects the level pulse signals output from the first port of the first main controller 11 and the second port of the second main controller 12, and controls the switch 21 to switch based on the level pulse signals.

[0026] In this embodiment, logical judgment is performed on the data bit sequences of the first master controller 11 and the second master controller 12. Specifically, the first master controller 11 and the second master controller 12 detect their own output level after sending each data bit sequence. The detection result of the output level determines which master controller has bus control. The first master controller 11 and the second master controller 12 each include a comparison module and an information generation module. The comparison module compares the output level information with the actual level information. The output level information is the level information of the data bit sequence sent by the first master controller 11 or the second master controller 12 to the system management bus, and the actual level information is the current level information of the system management bus. The information generation module generates a level pulse signal based on the level comparison result of the comparison module and outputs it to the controller 22. The controller 22 controls the switching switch 21 to switch, realizing the connection between one master controller and the slave device 30.

[0027] In this embodiment, the output level includes four detection results: when the output level information of the first main controller 11 and the second main controller 12 is consistent with the actual level information, there are two detection results: simultaneously outputting a high level and simultaneously outputting a low level. When the output level information of the first main controller 11 and the second main controller 12 is inconsistent with the actual level information, there are two detection results: one main controller is at a high level and the other main controller is at a low level. These are described in detail below.

[0028] In this embodiment of the application, when the output level information of the first master controller 11 and the second master controller 12 is consistent with the actual level information, the controller 22 controls the switching switch 21 to disconnect, or controls the switching switch 21 to connect the first master controller 11 or the second master controller 12 to the slave device 30.

[0029] When the output level information and actual level information of the first master controller 11 and the second master controller 12 are consistent, one scenario is that neither the first master controller 11 nor the second master controller 12 needs to communicate with the slave device 30. In this case, both the output level information and the actual level information are high, and the controller 22 controls the switch 21 to disconnect. Another scenario is that both the first master controller 11 and the second master controller 12 need to communicate with the slave device 30. In this case, both the output level information and the actual level information are low, and the controller 22 controls the switch 21 to connect either the first master controller 11 or the second master controller 12 to the slave device 30. The specific selection of the first master controller 11 or the second master controller 12 is determined according to the preset settings. For example, when both the first master controller 11 and the second master controller 12 request to connect to the slave device 30, if the first master controller 11 is given priority for communication by default, the controller 22 controls the switch 21 to connect the first master controller 11 to the slave device 30.

[0030] In this embodiment, the output level information of the first master controller 11 and the second master controller 12 are inconsistent with the actual level information. The controller 22 controls the switching switch 21 to connect the first master controller 11 to the slave device 30, or controls the switching switch 21 to connect the second master controller 12 to the slave device 30.

[0031] When the output level information and the actual level information of the first master controller 11 and the second master controller 12 are inconsistent, it indicates that one of the master controllers requests to connect to the slave device 30. The controller 22 needs to determine which master controller connects to the slave device 30 based on the level pulse signal.

[0032] For example, if the actual voltage level of the first master controller 11 is low and the actual voltage level of the second master controller 12 is high, the controller 22 controls the switch 21 to connect the first master controller 11 to the slave device 30; or, for example, if the actual voltage level of the first master controller 11 is high and the actual voltage level of the second master controller 12 is low, the controller 22 controls the switch 21 to connect the second master controller 12 to the slave device 30. That is, when the output voltage level of the first master controller 11 and the actual voltage level of the second master controller 12 are inconsistent with each other, the master controller with the actual voltage level low has control of the bus.

[0033] Continue to refer to Figure 2 As shown in this embodiment, after determining which master controller is connected to slave device 30, controller 22 pulls up the feedback signal of the other master controller and sends a waiting-to-release level indication signal to the other master controller. This means that the other master controller cannot have bus control and must wait to connect to slave device 30.

[0034] For example, switch 21 connects the first master controller 11 to the slave device 30, and controller 22 sends a level indication signal indicating that it is waiting to be released to the second master controller 12; switch 21 connects the second master controller 12 to the slave device 30, and controller 22 sends a level indication signal indicating that it is waiting to be released to the first master controller 11.

[0035] In this embodiment of the application, the switching switch 21 includes a multiplexer. For example... Figure 3 The diagram shows the logic circuit of a multiplexer. The input terminals of the multiplexer are connected to the first master controller 11, the second master controller 12, and the controller 22, respectively, and the output terminal is connected to the slave device 30. The multiplexer can select a signal from multiple analog or digital input signals and forward it, outputting different selected signals to the same output line.

[0036] This application provides a motherboard including the aforementioned dual-master controller structure. This application also provides an electronic product including the aforementioned dual-master controller structure or the aforementioned motherboard.

[0037] When using the dual-master control structure, the controller 22 simultaneously detects the level pulse signals of both master controllers to determine which master controller needs to communicate with the slave device 30. This process includes the following scenarios: When no master controller needs to communicate with slave device 30, the level pulse signal read by controller 22 is 0x00. At this time, switch 21 is turned off, no master controller is connected to slave device 30, and a level indication signal waiting to be released is sent to both master controllers. When the first master controller 11 needs to communicate with the slave device 30, both master controllers first send level pulse signals to the controller 22. When the controller 22 detects that the state of the two level pulse signals has changed to 0x01, the controller 22 controls the switching switch 21 to connect the first master controller 11 with the slave device 30. Then, it pulls up the level pulse signal of the second master controller 12, so that the second master controller 12 waits for the release level indication signal.

[0038] When the second master controller 12 needs to communicate with the slave device 30, both master controllers first send level pulse signals to the controller 22. When the controller 22 detects that the state of the two level pulse signals has changed to 0x02, the controller 22 controls the switching switch 21 to connect the second master controller 12 to the slave device 30. Then, it pulls up the level pulse signal of the first master controller 11, so that the first master controller 11 waits for the released level indication signal.

[0039] When the first master controller 11 and the second master controller 12 need to communicate with the slave device 30 at the same time, both master controllers send level pulse signals to the controller 22. When the controller 22 detects that the status of the two level pulse signals has changed to 0x03, it defaults to allowing the first master controller 11 to communicate first, and then pulls up the level pulse signal of the second master controller 12, so that the second master controller 12 waits for the release level indication signal.

[0040] This application provides a dual-master controller control structure, motherboard, and electronic product. The first master controller 11 and the second master controller 12 generate level pulse signals by detecting output level information and actual level information. The controller 22 controls the switching switch 21 to switch based on these level pulse signals, thus controlling either the first master controller 11 or the second master controller 12 to have bus control rights. This technical solution, based on level pulse signals as a judgment criterion, determines the switching between master controllers, enabling autonomous switching, improving the flexibility of operation between devices, and ensuring that only one master controller operates based on switching conditions. The control method is simple and avoids signal conflicts, providing better signal quality.

[0041] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0043] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A dual-master controller control structure, characterized in that, It includes a main control device module (10) and a control module (20); The main control device module (10) includes a first main controller (11) and a second main controller (12); The control module (20) includes a switch (21) and a controller (22). The switch (21) is connected to the first master controller (11) and the second master controller (12) via a system management bus, and the switch (21) is connected to the slave device (30) via the system management bus. The controller (22) is connected to the switch (21). The controller (22) detects the level pulse signals output by the first port of the first master controller (11) and the second port of the second master controller (12), and controls the switch (21) to switch based on the level pulse signals.

2. The dual-master controller control structure according to claim 1, characterized in that, The first main controller (11) and the second main controller (12) respectively include a comparison module and an information generation module; The comparison module compares the output level information and the actual level information. The output level information is the level information of the data bit sequence sent by the first master controller (11) or the second master controller (12) to the system management bus. The actual level information is the current level information of the system management bus. The information generation module generates a level pulse signal based on the level comparison result of the comparison module and outputs it to the controller (22).

3. The dual-master controller control structure according to claim 2, characterized in that, When the output level information of the first master controller (11) and the second master controller (12) is consistent with the actual level information, the controller (22) controls the switching switch (21) to disconnect, or controls the switching switch (21) to connect the first master controller (11) or the second master controller (12) to the slave device (30).

4. The dual-master controller control structure according to claim 3, characterized in that, When both the output level information and the actual level information are high, the controller (22) controls the switching switch (21) to open. Both the output level information and the actual level information are low level. The controller (22) controls the switching switch (21) to connect the first master controller (11) or the second master controller (12) to the slave device (30).

5. The dual-master controller control structure according to claim 4, characterized in that, The output level information of the first master controller (11) and the second master controller (12) is inconsistent with the actual level information. The controller (22) controls the switching switch (21) to connect the first master controller (11) to the slave device (30), or controls the switching switch (21) to connect the second master controller (12) to the slave device (30).

6. The dual-master controller control structure according to claim 5, characterized in that, The actual level information of the first master controller (11) is low level, and the actual level information of the second master controller (12) is high level. The controller (22) controls the switching switch (21) to connect the first master controller (11) to the slave device (30). The actual level information of the first master controller (11) is high level and the actual level information of the second master controller (12) is low level. The controller (22) controls the switching switch (21) to connect the second master controller (12) to the slave device (30).

7. The dual-master controller control structure according to claim 6, characterized in that, The switching switch (21) connects the first master controller (11) to the slave device (30), and the controller (22) sends a level indication signal indicating that it is waiting to be released to the second master controller (12); The switching switch (21) connects the second master controller (12) to the slave device (30), and the controller (22) sends a level indication signal waiting to be released to the first master controller (11).

8. The dual-master controller control structure according to any one of claims 1 to 7, characterized in that, The switching switch (21) includes a multiplexer.

9. A motherboard, characterized in that, Includes a dual master controller control structure as described in any one of claims 1 to 8.

10. An electronic product, characterized in that, It includes a dual-master controller structure as described in any one of claims 1 to 8 or a motherboard as described in claim 9.

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