Single-cc line implementation of type-c interface normal and reverse plug circuit

Abstract

The application relates to the technical field of Typec interface circuits, in particular to a circuit for realizing Typec interface normal and reverse insertion through a single CC line, which comprises a main control chip, a first analog switch, a second analog switch, a first Typec interface and a second Typec interface, the first analog switch is electrically connected with the main control chip and the first Typec interface respectively, and the second analog switch is electrically connected with the main control chip and the second Typec interface respectively. Through the first analog switch and the second analog switch, the equipment at the two groups of Typec interfaces can be detected and powered under the condition that the main control chip only has one group of CC lines, so that the requirement of setting two groups of Typec interfaces can be met without increasing too much cost.

Description

Technical Field

[0001] This application relates to the field of Type-C interface circuit technology, and in particular to a circuit that enables reversible insertion of a Type-C interface using a single CC line. Background Technology

[0002] Please see Figure 1 Some main control chips on the market only have one set of CC lines. They determine whether the external charging / discharging device is connected to the CC1 or CC2 pin of the Type-C interface by detecting the voltage of the two CC lines. However, when two Type-C interfaces are required, the main control chip cannot detect the devices connected to both Type-C interfaces.

[0003] Therefore, existing technologies have shortcomings and need to be improved. Utility Model Content

[0004] This application provides a circuit for implementing reversible insertion of a Type-C interface using a single CC line to solve the above-mentioned problems.

[0005] In a first aspect, this application provides a circuit for reversible insertion of a Type-C interface using a single CC line, including a main control chip, a first analog switch, a second analog switch, a first Type-C interface, and a second Type-C interface. The first analog switch is electrically connected to the main control chip and the first Type-C interface, and the second analog switch is electrically connected to the main control chip and the second Type-C interface.

[0006] Optionally, the main control chip includes IO1, IO2, CC1 and CC2 terminals, wherein IO1 and CC1 terminals are electrically connected to a first analog switch, and IO2 and CC2 terminals are electrically connected to a second analog switch.

[0007] Optionally, the first analog switch includes an S terminal and a D- terminal, and the S terminal and D- terminal of the first analog switch are electrically connected to the main control chip, respectively.

[0008] Optionally, the first analog switch further includes an HSD2+ terminal, an HSD2- terminal, an HSD1+ terminal, and an HSD1- terminal. The HSD2+ terminal of the first analog switch is electrically connected to the HSD1- terminal and electrically connected to the first Type-C interface. The HSD2- terminal of the first analog switch is electrically connected to the HSD1+ terminal and electrically connected to the first Type-C interface.

[0009] Optionally, the second analog switch includes an S terminal and a D- terminal, and the S terminal and D- terminal of the second analog switch are electrically connected to the main control chip respectively.

[0010] Optionally, the second analog switch further includes an HSD2+ terminal, an HSD2- terminal, an HSD1+ terminal, and an HSD1- terminal. The HSD2+ terminal of the second analog switch is electrically connected to the HSD1- terminal and electrically connected to the second Type-C interface. The HSD2- terminal of the second analog switch is electrically connected to the HSD1+ terminal and electrically connected to the second Type-C interface.

[0011] Optionally, the first Typec interface includes a CC1 terminal and a CC2 terminal, and the CC1 terminal and CC2 terminal of the first Typec interface are electrically connected to the first analog switch respectively.

[0012] Optionally, the second Typec interface includes a CC1 terminal and a CC2 terminal, and the CC1 terminal and CC2 terminal of the second Typec interface are electrically connected to the second analog switch respectively.

[0013] The technical solutions provided in this application have the following advantages compared with the prior art:

[0014] This application embodiment achieves the detection and power supply of devices at two sets of Type-C interfaces by setting a first analog switch and a second analog switch, when the main control chip only has one set of CC lines. This satisfies the requirement of setting two sets of Type-C interfaces without increasing the cost significantly. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0018] Figure 1 This is a circuit diagram showing the connection between a commercially available main control chip and a Type-C interface.

[0019] Figure 2 This is a circuit diagram illustrating a single CC line for reversible insertion of a Type-C interface, provided as an embodiment of this application.

[0020] Explanation of reference numerals in the attached figures:

[0021] 1. Main control chip; 2. First analog switch; 3. Second analog switch; 4. First Type-C interface; 5. Second Type-C interface. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0024] For ease of description, spatial relative terms may be used in the text to describe the relative position or movement of one element or feature relative to another element or feature, as shown in the figure. These relative terms include, for example, "inside," "outside," "middle," "outer," "below," "below," "above," "front," "back," etc. Such spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figure. For example, if the device in the figure undergoes a positional flip, orientation change, or change of motion, these directional indications will change accordingly. For instance, an element described as "below other elements or features" or "below other elements or features" will subsequently be oriented "above other elements or features" or "above other elements or features." Therefore, the example term "below" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or in other directions), and the spatial relative descriptors used in the text will be interpreted accordingly.

[0025] To address the technical problems in the prior art, this application provides a circuit for reversible insertion of a Type-C interface using a single CC line. This circuit enables the detection and power supply of devices at two Type-C interfaces when the main control chip has only one set of CC lines, by setting a first analog switch and a second analog switch. This satisfies the requirement of setting two Type-C interfaces without significantly increasing costs.

[0026] Figure 2 A circuit for reversible insertion of a Type-C interface using a single CC line, provided in this application embodiment, includes a main control chip 1, a first analog switch 2, a second analog switch 3, a first Type-C interface 4, and a second Type-C interface 5. The first analog switch 2 is electrically connected to the main control chip 1 and the first Type-C interface 4, respectively, and the second analog switch 3 is electrically connected to the main control chip 1 and the second Type-C interface 5, respectively.

[0027] In this application, the CC line is switched by setting the first analog switch 2 and the second analog switch 3, and the two CC lines of the two sets of Type-C interface terminals are detected in a time-division manner. This enables the detection and power supply of the device access at the two sets of Type-C interfaces when the main control chip 1 only has one set of CC lines, which meets the requirement of setting two sets of Type-C interfaces without increasing the cost significantly.

[0028] Furthermore, the main control chip 1 includes an IO1 terminal, an IO2 terminal, a CC1 terminal, a CC2 terminal, a VCC terminal, and a GND terminal. The IO1 terminal and the CC1 terminal are electrically connected to the first analog switch 2, and the IO2 terminal and the CC2 terminal are electrically connected to the second analog switch 3. The VCC terminal of the main control chip 1 is connected to VCC, and the GND terminal of the main control chip 1 is grounded.

[0029] Further, the first analog switch 2 includes an S terminal, a D- terminal, an HSD2+ terminal, an HSD2- terminal, an HSD1+ terminal, and an HSD1- terminal. The S terminal and the D- terminal of the first analog switch 2 are electrically connected to the main control chip 1, respectively. The HSD2+ terminal and the HSD1- terminal of the first analog switch 2 are electrically connected and electrically connected to the first Type-C interface 4. The HSD2- terminal and the HSD1+ terminal of the first analog switch 2 are electrically connected and electrically connected to the first Type-C interface 4. The S terminal of the first analog switch 2 is connected to the IO1 terminal of the main control chip 1, and the D- terminal of the first analog switch 2 is connected to the CC1 terminal of the main control chip 1.

[0030] Further, the second analog switch 3 includes an S terminal, a D- terminal, an HSD2+ terminal, an HSD2- terminal, an HSD1+ terminal, and an HSD1- terminal. The S terminal and D- terminal of the second analog switch 3 are electrically connected to the main control chip 1, respectively. The HSD2+ terminal and HSD1- terminal of the second analog switch 3 are electrically connected and electrically connected to the second Type-C interface 5. The HSD2- terminal and HSD1+ terminal of the second analog switch 3 are electrically connected and electrically connected to the second Type-C interface 5. The S terminal of the second analog switch 3 is connected to the IO2 terminal of the main control chip 1, and the D- terminal of the second analog switch 3 is connected to the CC2 terminal of the main control chip 1.

[0031] Further, the first Type-C interface 4 includes a CC1 terminal and a CC2 terminal. The CC1 terminal and CC2 terminal of the first Type-C interface 4 are electrically connected to the first analog switch 2, specifically, the CC1 terminal of the first Type-C interface 4 is electrically connected to the HSD2+ terminal and the HSD1- terminal of the first analog switch 2, and the CC2 terminal of the first Type-C interface 4 is electrically connected to the HSD2- terminal and the HSD1+ terminal of the first analog switch 2. The second Type-C interface 5 includes a CC1 terminal and a CC2 terminal. The CC1 terminal and CC2 terminal of the second Type-C interface 5 are electrically connected to the second analog switch 3, specifically, the CC1 terminal of the second Type-C interface 5 is electrically connected to the HSD2+ terminal and the HSD1- terminal of the second analog switch 3, and the CC2 terminal of the second Type-C interface 5 is electrically connected to the HSD2- terminal and the HSD1+ terminal of the second analog switch 3.

[0032] When the IO1 terminal of the main control chip 1 outputs a high level, VCC is connected to the CC1 terminal of the first Type-C interface 4, and the CC1 terminal of the main control chip 1 is connected to the CC2 terminal of the first Type-C interface 4; when the IO1 terminal of the main control chip 1 outputs a low level, VCC is connected to the CC2 terminal of the first Type-C interface 4, and the CC1 terminal of the main control chip 1 is connected to the CC1 terminal of the first Type-C interface 4, thereby realizing the detection and power supply of the first Type-C interface 4. Similarly, the detection and power supply process of the second Type-C interface 5 can be obtained.

[0033] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0034] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0036] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0037] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0038] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0039] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Since these modifications and variations fall within the scope of the claims and their equivalents, this application also intends to include these modifications and variations.

[0040] The above description describes specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A circuit for reversible insertion of a Type-C interface using a single CC line, characterized in that: It includes a main control chip, a first analog switch, a second analog switch, a first Type-C interface, and a second Type-C interface. The first analog switch is electrically connected to the main control chip and the first Type-C interface, and the second analog switch is electrically connected to the main control chip and the second Type-C interface.

2. The circuit for reversible insertion of a Type-C interface using a single CC line as described in claim 1, characterized in that: The main control chip includes IO1, IO2, CC1 and CC2 terminals. IO1 and CC1 terminals are electrically connected to a first analog switch, and IO2 and CC2 terminals are electrically connected to a second analog switch.

3. The circuit for reversible insertion of a Type-C interface using a single CC line as described in claim 1, characterized in that: The first analog switch includes an S terminal and a D- terminal, and the S terminal and D- terminal of the first analog switch are electrically connected to the main control chip respectively.

4. The circuit for reversible insertion of a Type-C interface using a single CC line as described in claim 3, characterized in that: The first analog switch further includes an HSD2+ terminal, an HSD2- terminal, an HSD1+ terminal, and an HSD1- terminal. The HSD2+ terminal of the first analog switch is electrically connected to the HSD1- terminal and is electrically connected to the first Type-C interface. The HSD2- terminal of the first analog switch is electrically connected to the HSD1+ terminal and is electrically connected to the first Type-C interface.

5. The circuit for reversible insertion of a Type-C interface using a single CC line according to claim 1, characterized in that: The second analog switch includes an S terminal and a D- terminal, and the S terminal and D- terminal of the second analog switch are electrically connected to the main control chip respectively.

6. The circuit for reversible insertion of a Type-C interface using a single CC line according to claim 5, characterized in that: The second analog switch further includes an HSD2+ terminal, an HSD2- terminal, an HSD1+ terminal, and an HSD1- terminal. The HSD2+ terminal of the second analog switch is electrically connected to the HSD1- terminal and electrically connected to the second Type-C interface. The HSD2- terminal of the second analog switch is electrically connected to the HSD1+ terminal and electrically connected to the second Type-C interface.

7. The circuit for reversible insertion of a Type-C interface using a single CC line according to claim 1, characterized in that: The first Type-C interface includes a CC1 terminal and a CC2 terminal, and the CC1 terminal and CC2 terminal of the first Type-C interface are electrically connected to the first analog switch respectively.

8. The circuit for reversible insertion of a Type-C interface using a single CC line according to claim 1, characterized in that: The second Typec interface includes a CC1 terminal and a CC2 terminal, and the CC1 terminal and CC2 terminal of the second Typec interface are electrically connected to the second analog switch respectively.

Images