An IO unit and a low-power chip containing the same

Abstract

The utility model discloses a kind of IO unit and the low-power chip comprising IO unit, IO unit includes outer pin, pin drive circuit, IO power port, control signal input port and N latching unit, N=2;Each latching unit connects IO power port, is powered by IO power supply;Latching unit includes data input end, control input end and data output end, the data input end of N latching unit is respectively connected from the N input signals of kernel, the level of the input signal is kernel voltage;The control input end of N latching unit is all connected control signal input port, for input control signal;The data output end of at least one latching unit connects pin drive circuit, pin drive circuit connects outer pin.The IO unit of the utility model does not need to keep power kernel domain, chip layout is easy, structure is simple, power consumption is low, small, low in cost.

Description

Technical Field

[0001] This invention belongs to the field of low-power SoC / MCU technology, and particularly relates to an IO unit and a low-power chip containing the IO unit. Background Technology

[0002] A SoC / MCU consists of a core (specifically, the low-voltage digital region CORE, which includes the processor and GPIO control system, to distinguish it from I / O units) and several I / O units. For example... Figure 1 As shown, a typical bidirectional I / O unit has signal ports such as output data (OD) input from the core, output enable (OE) input from the core, and pin input (C) sent to the core. The output data (OD) and output enable (OE) drive the external pin outputs of the I / O unit, generating the required levels and states on the external pins of the chip. Most bidirectional I / O units also have signal ports such as pull-up control (PU), pull-down control (PD), and several parameter configuration (OS) to control the pull-up resistor or current, pull-down resistor or current, drive capability, edge characteristics, and other configurations of the I / O unit. Except for the pin C output to the core, all other signals mentioned above are input from the core, driven by the I / O functions or controlled by the configuration circuitry within the core, and are all connected to the core's digital units.

[0003] With advancements in manufacturing processes, the static leakage current of digital units accounts for an increasingly larger proportion of power consumption. Low-power chips divide the digital unit circuitry into at least two power supply regions, such as a power-off core region and a non-power-off core region. The vast majority of digital units are placed in the power-off core region, allowing them to be powered off in sleep mode. A very small portion of digital units are placed in the non-power-off core region for systemic tasks such as handling sleep / wake cycles and isolating I / O signals after the power-off core region is powered off. For example... Figure 2 As shown, 1 is the I / O unit, and several I / O units are usually arranged around the chip. 2 is the uninterrupted core domain (with diagonal shading), which has a small area. The rest are the power-off core domains 3 (with dotted shading).

[0004] Since the output data OD, output enable OE, pull-up control PU, pull-down control PD, and other signals of each IO unit are all controlled by the kernel, in order to avoid the above signals entering an uncertain state after the power-off kernel domain is powered off, causing abnormal external state of the IO pins, there are usually three conventional solutions in the existing technology.

[0005] Option 1 is to place the I / O function drivers or configuration circuits of all I / O units in the uninterruptible kernel domain 2, such as... Figure 2 As shown in path A, the disadvantages are a large uninterruptible kernel domain area and a large static leakage current. Solution two involves placing the main I / O function driver or configuration circuit of the I / O unit in the power-off kernel domain 3, and placing some isolation units and state-maintaining memory units in the uninterruptible kernel domain 2, such as... Figure 2 As shown in path B, the IO signal traces need to cross regions, resulting in significant signal delay and complex wiring.

[0006] like Figure 2 As shown, the middle area of ​​the chip is reserved for the core, which, in addition to digital unit circuitry, also includes memory 4, analog module 5, etc., partially separating the digital units from the I / O units, resulting in a relatively long connection distance between the I / O units and the digital units. With advancements in manufacturing processes, signal trace delays are increasing. To ensure the speed and quality of I / O signals, such as... Figure 2 As shown, Scheme 1 and Scheme 2 usually require the addition of sporadic uninterruptible kernel domains 21 for placing I / O signal buffers nearby, which are called improved versions of Scheme 1 and Scheme 2.

[0007] Option 3 is a further upgrade of Option 2, moving the isolation unit and the state-preserving storage unit to the newly added uninterruptible kernel domain 21, simplifying the I / O signal buffer. Existing technology CN112908961A is similar to Option 3, placing the isolation unit and the state-preserving storage unit in the logic signal channel. This means that the aforementioned uninterruptible kernel domain 21 is not scattered, but rather arranged in a circle close to the I / O unit.

[0008] The shortcomings of all the above-mentioned existing technical solutions are that they all require an uninterruptible core domain and an ultra-low power LDO buck converter to provide uninterruptible core power, resulting in high total power consumption and numerous chip traces, making wiring difficult. Utility Model Content

[0009] Purpose of the utility model: In order to solve the problems of insufficient power consumption of IO units and chips as a whole and the difficulty of IO wiring in the prior art, this utility model provides an IO unit and a low-power chip containing an IO unit.

[0010] Technical solution: An I / O unit includes external pins, a pin driver circuit, an I / O power supply port, a control signal input port, and N latch units, where N ≥ 2; each latch unit is connected to the I / O power supply port and powered by the I / O power supply; each latch unit includes a data input terminal, a control input terminal, and a data output terminal; the data input terminals of the N latch units are respectively connected to N input signals from the kernel, and the level of the input signals is the kernel voltage; the control input terminals of the N latch units are all connected to the control signal input port for inputting control signals; the data output terminal of at least one latch unit is connected to the pin driver circuit, and the pin driver circuit is connected to the external pins.

[0011] Furthermore, it also includes a logic comparison unit. The first input terminal of the logic comparison unit receives the level input result of the external pin. The second input terminal of the logic comparison unit is connected to the data output terminal of a latch unit. The output terminal of the logic comparison unit is connected to the core.

[0012] Furthermore, it also includes a reset input terminal, which is connected to at least one latch unit and is used to input a reset signal.

[0013] Furthermore, it also includes a hold state return circuit, which includes a level shifting circuit from the IO power supply voltage to the core voltage. The input of the hold state return circuit is connected to the data output of a latch unit, and the output of the hold state return circuit is connected to the core.

[0014] Furthermore, it also includes an inverter or a buffer, and the control signal input port is connected to the control input terminal of each latch unit via the inverter or buffer.

[0015] Furthermore, the N input signals from the kernel include at least two of the following: a signal for controlling the pull-up of the I / O unit, a signal for controlling the pull-down of the I / O unit, a signal for driving the level of the external pin of the I / O unit, and a signal for enabling the output of the external pin of the I / O unit.

[0016] Furthermore, it also includes a switch for controlling pull-up and a switch for controlling pull-down, with at least one data output terminal of the latch unit connected to the switch for controlling pull-up and at least one data output terminal of the latch unit connected to the switch for controlling pull-down.

[0017] A low-power chip with I / O units includes the aforementioned I / O units, control signals, I / O power supplies, and a power-off core power supply, and also includes I / O function driver or configuration circuitry; the I / O power supply port of the I / O unit is connected to the I / O power supply, and the control signal input port is connected to the control signal; the I / O function driver or configuration circuitry is powered by the power-off core power supply, and the signals generated by the I / O function driver or configuration circuitry are directly connected to the data input terminals of each latch unit without passing through the uninterrupted core domain.

[0018] Furthermore, it includes at least one sleep state, in which the I / O power supply is powered and the power-off kernel power supply is turned off.

[0019] Furthermore, there are multiple I / O units, and the control signal is a global signal that is not targeted at any individual I / O unit.

[0020] Compared with the prior art, the I / O unit and low-power chip containing the I / O unit provided by this utility model have the following beneficial effects:

[0021] (1) From a system perspective, this utility model designs the latch unit within the IO unit. The IO unit is powered by the IO power supply, eliminating the need for uninterruptible power supply from the core power supply. This eliminates the need for an ultra-low power LDO step-down converter, resulting in a simple structure, small area, and low cost.

[0022] (2) The I / O function driver or configuration circuit in the low-power chip can be automatically placed in the power-off core domain close to the corresponding I / O unit by the automatic placement and routing tool. The relevant signals can be routed nearby, with small routing delay and good signal quality. It is even so close that there is no need for I / O signal buffers, further eliminating the insertion delay of buffered digital units. For example Figure 4 7 in the diagram represents the I / O function driver or configuration circuit, located in the power-off kernel domain 3. This I / O function driver or configuration circuit connects directly to the I / O unit without passing through the power-off kernel domain, ensuring low latency and high quality for I / O-related signals. Furthermore, its signals do not require the same latency characteristics as in existing technologies. Figure 2 Such access to and from the uninterruptible core domain reduces the number of chip traces, makes wiring easier, lowers wiring resource costs, and reduces wiring parasitic capacitance, thereby increasing speed. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of a conventional I / O unit in existing technology;

[0024] Figure 2 This is a schematic diagram of the layout and I / O signal routing of existing low-power chips.

[0025] Figure 3 This is a schematic diagram of the structure of the IO unit in Embodiment 1;

[0026] Figure 4 This is a schematic diagram of the low-power chip layout and I / O signal routing for Example 1;

[0027] Figure 5 This is a schematic diagram of the structure of the IO unit in Embodiment 2. Detailed Implementation

[0028] The present invention will be further explained below with reference to the accompanying drawings and specific embodiments.

[0029] Example 1:

[0030] An I / O unit, such as Figure 3 As shown, it includes external pins (PIN), pin driver circuit, IO power supply port VDDIO, control signal input port ISO, and N latch units, where N≥2.

[0031] Each latch unit is connected to the I / O power port VDDIO (not shown in the diagram) and is powered by the I / O power supply. Each latch unit includes a data input terminal D, a control input terminal G, and a data output terminal Q. The data input terminals of the N latch units are respectively connected to N input signals P1 to PN from the kernel (labeled by function in the diagram: OS, OD, OE, PU, ​​PD, etc.). The level of the input signals is the kernel voltage, and they are used for parameter configuration, driving the external pin level of the I / O unit, enabling the external pin output of the I / O unit, controlling the pull-up of the I / O unit, and controlling the pull-down of the I / O unit, etc. Buffers or inverters can also be inserted into the output of the latch units as needed to control the configuration of the I / O units, such as drive capability. The control input terminals of the latch units are all connected to the control signal input port ISO for inputting control signals; at least one latch unit's data output terminal is connected to a pin driver circuit, which is connected to an external pin. The data output terminal of the latch unit can output a signal with the same polarity as the data input signal or an output signal with the opposite polarity. The latch units are powered by the I / O power supply, and the signal output from the data output terminal is the I / O voltage.

[0032] The IO unit may also include pull-up resistors, pull-down resistors, switches that control the pull-up, and switches that control the pull-down. The pull-up resistors and pull-down resistors are electrically connected to external pins. The data output terminal of at least one latch unit is connected to the switch that controls the pull-up, and the data output terminal of at least one latch unit is connected to the switch that controls the pull-down.

[0033] The control signal can be a first level, representing the normal operating state; or a second level, representing the sleep isolation state. In this embodiment, the first level is high and the second level is low, or vice versa, with the first level low and the second level high, to distinguish between the normal operating state and the sleep isolation state. In the normal operating state, the latch unit is used for logic pass-through (including same or opposite polarity). At this time, the latch unit may include level shifting to convert the core voltage input signal into an IO voltage output signal. In the sleep isolation state, the latch unit is used to latch data, so that the output is held at the last moment before the control signal transitions to the sleep isolation state level.

[0034] Preferably, the I / O unit often also needs to be used for level detection of external pins, and should also include a logic comparison unit. The logic comparison unit can be implemented using XOR gates, XNOR gates, or equivalent logic. The first input of the logic comparison unit receives the level input result XC of the external pin. The second input of the logic comparison unit is connected to the data output of a latch unit. The output of the logic comparison unit is connected to the core, outputting an internal signal CC for detecting level changes of the external pin. Optionally, an enable logic can be added to perform the logic comparison only when the control signal is in a sleep isolation state. Optionally, such as... Figure 3 As shown, the latch unit described above multiplexes the latch unit corresponding to the external pin level of the driving IO unit. Preferably, the internal signal CC is an IO voltage signal connected to the wake-up module under the IO power domain. Figure 3 As shown, similar to conventional I / O units, it also includes a signal port C sent to the core, which is a core voltage signal. Its driving circuit can be powered by a power-off core power supply, and it powers on or off together with the core digital circuitry, without requiring a continuous core power supply. Optionally, if the chip has a continuous core domain and contains a wake-up module, then the internal signal CC is a core voltage signal and is powered by a continuous core power supply. In this case, CC and the signal port C sent to the core can optionally be combined into a single signal port, distinguished according to the state of the control signal.

[0035] A low-power chip includes the aforementioned I / O units, control signals, I / O power supplies, and a power-off-enabled core power supply, and further includes I / O function driver or configuration circuitry. The I / O power supply ports of the I / O units are connected to the I / O power supply, and the control signal input ports are connected to control signals. The I / O function driver or configuration circuitry is powered by the power-off-enabled core power supply, and the signals generated by the I / O function driver or configuration circuitry are directly connected to the data input terminals of each latch unit without passing through the uninterrupted core domain, such as... Figure 4 As shown. In addition, low-power chips can still include an uninterruptible power supply (UPS) core domain, except that the I / O units are located in the I / O power domain and do not require UPS core power supply.

[0036] The low-power chip includes at least one sleep state, in which the I / O power supply is powered and the power-off core power supply is turned off to reduce power consumption.

[0037] The low-power chip may contain multiple I / O units, and the control signal is a global signal that is not targeted at any individual I / O unit.

[0038] Example 2:

[0039] The difference between Embodiment 2 and Embodiment 1 is that the IO unit in Embodiment 2 has richer functions.

[0040] It may also include a reset input terminal RST, such as Figure 5 As shown, the reset input terminal RST is connected to at least one latch unit. The reset input terminal is used to input a reset signal to ensure that the output of the latch unit is in a state of not driving the external IO pin during reset or power-on.

[0041] It may also include a state return circuit, such as Figure 5As shown, the hold state return circuit includes a level shifting circuit from the IO voltage to the core voltage. The input of the hold state return circuit is connected to the data output of a latch unit, and the output ROD of the hold state return circuit is connected to the core. When the control signal is in sleep isolation state, the latch unit always maintains its output unchanged. After the system wakes up, the core domain can be powered off and power restored. The ROD outputs the state held by the latch unit to the core. The IO function driver or configuration circuit restores its memory from this return state, and then the control signal is restored to the normal operating state, and the latch unit is released. The hold state return circuit can be powered by a power-off-enabled core power supply, and can be powered on or off together with the core digital circuits, without requiring a continuous core power supply.

[0042] It may also include an inverter or a buffer, wherein the control signal input port ISO is first boosted by the inverter or buffer before being connected to the control input of each latch unit.

[0043] Unless otherwise specified, the connections mentioned above include both direct and indirect connections.

Claims

1. An I / O unit, characterized in that, It includes external pins, pin driver circuits, I / O power supply ports, control signal input ports, and N latch units, where N ≥ 2. Each latch unit is connected to the I / O power supply port and is powered by the I / O power supply. Each latch unit includes a data input terminal, a control input terminal, and a data output terminal. The data input terminals of the N latch units are respectively connected to N input signals from the core, and the level of the input signals is the core voltage. The control input terminals of the N latch units are all connected to the control signal input port for inputting control signals. The data output terminal of at least one latch unit is connected to the pin driver circuit, and the pin driver circuit is connected to the external pins.

2. The I / O unit according to claim 1, characterized in that, It also includes a logic comparison unit. The first input of the logic comparison unit is the level input result of the external pin. The second input of the logic comparison unit is connected to the data output of a latch unit. The output of the logic comparison unit is connected to the core.

3. The I / O unit according to claim 1 or 2, characterized in that, It also includes a reset input terminal, which is connected to at least one latch unit and is used to input a reset signal.

4. The I / O unit according to claim 1 or 2, characterized in that, It also includes a hold state return circuit, which includes a level shifting circuit from the IO power supply voltage to the core voltage. The input of the hold state return circuit is connected to the data output of a latch unit, and the output of the hold state return circuit is connected to the core.

5. The I / O unit according to claim 1 or 2, characterized in that, It also includes an inverter or a buffer, and the control signal input port is connected to the control input terminal of each latch unit through the inverter or buffer.

6. The I / O unit according to claim 1 or 2, characterized in that, The N input signals from the kernel include at least two of the following: a signal for controlling the pull-up of the I / O unit, a signal for controlling the pull-down of the I / O unit, a signal for driving the level of the external pin of the I / O unit, and a signal for enabling the output of the external pin of the I / O unit.

7. The I / O unit according to claim 1 or 2, characterized in that, It also includes a switch for controlling pull-up and a switch for controlling pull-down, with at least one data output terminal of the latch unit connected to the switch for controlling pull-up and at least one data output terminal of the latch unit connected to the switch for controlling pull-down.

8. A low-power chip containing I / O units, characterized in that, It includes an I / O unit as described in any one of claims 1-7, a control signal, an I / O power supply, and a power-off kernel power supply, and also includes an I / O function driver or configuration circuit; the I / O power supply port of the I / O unit is connected to the I / O power supply, and the control signal input port is connected to the control signal; the I / O function driver or configuration circuit is powered by the power-off kernel power supply, and the signal generated by the I / O function driver or configuration circuit is directly connected to the data input terminal of each latch unit without passing through the uninterrupted kernel domain.

9. The low-power chip according to claim 8, characterized in that, It includes at least one sleep state, in which I / O power is supplied and the power-off kernel power is turned off.

10. The low-power chip according to claim 8 or 9, characterized in that, There are multiple I / O units, and the control signal is a global signal that is not targeted at any individual I / O unit.

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