A multifunctional logic operation circuit based on ferroelectric field effect transistor

Abstract

The utility model discloses a kind of multifunctional logic operation circuit based on ferroelectric field effect transistor, it includes first and second voltage input end, core operation module and result output end, core operation module is composed of two ferroelectric field effect transistors and a reconfigurable switch network, this network contains at least three controlled switch devices and is connected with the source and drain of two ferroelectric field effect transistors;By responding to the on-off state of controlled switch device change multiple control signals, core operation module can dynamically change the electrical connection relationship between two ferroelectric field effect transistors, make the result output end connected to unique output node generate corresponding voltage, to represent different logic operation or data matching result;Advantage is through unified logic output path and hardware level dynamic reconfiguration, in same hardware structure, NOR, IMP and so on multiple logic operation and NV-TCAM function are realized, significantly improve the functional diversity, flexibility and reduce the complexity of peripheral circuit and power consumption.

Description

Technical Field

[0001] This utility model belongs to the field of in-memory computing circuit technology, and relates to an in-memory computing logic operation circuit, especially a multifunctional logic operation circuit based on a ferroelectric field-effect transistor (FeFET). Background Technology

[0002] Traditional von Neumann computing architectures, due to their storage-compute separation design, require constant data transfer and movement between memory and the arithmetic logic unit (ALU). With the advent of the big data era, data volume is growing exponentially. When processing large-scale data, frequent data transfer and movement create a "memory wall" (limited memory capacity or bandwidth) and a "power wall" (excessive power consumption due to constant read / write operations) between memory and the ALU, severely limiting system energy efficiency and computing performance. To overcome this bottleneck, the in-memory computing paradigm emerged, its core idea being to integrate computational functions into storage units, thereby reducing data movement.

[0003] There are many types of non-volatile devices used for in-memory computing, such as memristors, phase-change memories, and ferroelectric field-effect transistors (FeFETs). FeFETs have attracted much attention due to their high on / off ratio, low power consumption, nanosecond-level operating speed, and good compatibility with standard CMOS processes. Existing technologies have already utilized FeFETs to construct in-memory computing units.

[0004] The IEEE paper "FeMPIM: A FeFET-Based Multifunctional Processing-in-Memory Cell" discloses a FeFET-based multifunctional in-memory computing unit (FeMPIM). This multifunctional in-memory computing unit is constructed using two FeFETs and two CMOS transistors. Its core innovation lies in its sophisticated external signal timing control, enabling a single in-memory computing unit to support multiple operating modes: in storage mode, it can independently read and write to both FeFETs; in computing mode, it can perform various basic logical operations such as OR, AND, NOR, and XOR; and in TCAM mode, it can achieve fast content search and matching functions. This multifunctional in-memory computing unit has the following limitations: 1. When this unit implements some logical functions, or when it is performing logical transformation, the logical output path of this unit cannot be uniformly implemented. In practical applications, additional circuits or operations need to be introduced to receive output signals from different logical output paths. For arrays with high integration, this will greatly increase resource consumption.

[0005] 2. The signal path and operating mode of this unit are controlled by a relatively complex set of preset timing logic. While this design achieves versatility, it fails to provide a more refined and flexible control mechanism to dynamically change the electrical connections between FeFETs within the unit. This design limits the unit's ability to expand into more computational modes through simple configuration. For example, it falls short when implementing complex logic operations requiring step-by-step processing, such as implied (IMP) logic, thus creating a bottleneck in functional diversity and circuit scalability.

[0006] In summary, while existing technologies utilizing ferroelectric field-effect transistors (FeFETs) to construct in-memory computing units, such as the FeMPIM scheme, have made progress in functional integration, they still suffer from significant shortcomings in the uniformity of logic output paths and the functional reconfigurability of the hardware architecture. Therefore, researching a multifunctional logic circuit that unifies logic output paths and allows for dynamic reconfiguration of circuit connection topologies within the unit through configuration control signals, thereby enabling more flexible and efficient implementation of richer logic operations and non-volatile ternary content-addressable memory (NV-TCAM) functionality, has become a key direction for further improving in-memory computing performance. Summary of the Invention

[0007] The technical problem to be solved by this utility model is to provide a multifunctional logic operation circuit based on ferroelectric field effect transistors. It can realize multiple logic operations and non-volatile ternary content-addressable memory (NV-TCAM) functions in the same hardware structure by configuring control signals. It can also fundamentally realize the unification of logic output paths and endow the circuit hardware with inherent reconfigurability. Thus, while improving the diversity and flexibility of functions, it significantly reduces the complexity of peripheral circuits and system power consumption.

[0008] The technical solution adopted by this utility model to solve the above-mentioned technical problems is: a multifunctional logic operation circuit based on ferroelectric field-effect transistors, comprising: First voltage input terminal and second voltage input terminal; The core computing module consists of a first ferroelectric field-effect transistor, a second ferroelectric field-effect transistor, and a reconfigurable switching network, and has a unique output node. The gates of the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor are respectively connected to the first voltage input terminal and the second voltage input terminal. The reconfigurable switching network is connected to the source and drain of the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor, and includes at least three controlled switching devices. The core computing module is configured to: respond to multiple control signals, dynamically change the electrical connection relationship between the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor by changing the on / off state of the controlled switching device, and then, based on the different electrical connection relationships and the threshold voltage states of the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor, generate a voltage on the output node that represents different logic operations or data matching results. The result output terminal is connected to the output node.

[0009] Further defining the circuit, it includes a first control terminal, a second control terminal, a third control terminal, a fourth control terminal, a fifth control terminal, and a sixth control terminal. The controlled switching devices are a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The gate of the first NMOS transistor is connected to the second control terminal, and its source is connected to the first control terminal. The gate of the second NMOS transistor is connected to the third control terminal. The gate of the third NMOS transistor is connected to the fourth control terminal, and its drain is connected to the fifth control terminal. The on / off states of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are changed accordingly by the control signals received by the second control terminal, the third control terminal, and the fourth control terminal. The source of the first ferroelectric field-effect transistor is connected to the drain of the second NMOS transistor, and its drain is connected to the sixth control terminal. The source of the second ferroelectric field-effect transistor is connected to the drain of the first NMOS transistor and the source of the second NMOS transistor, and its drain is connected to the source of the third NMOS transistor. The output node is the first control terminal.

[0010] Preferably, the electrical connection relationship has at least the following two types: Under the first electrical connection relationship, the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all in the on state. At this time, the sources of the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor are connected to each other through the on-state second NMOS transistor, forming a parallel discharge path jointly controlled by the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor. Under the second electrical connection relationship, there are two sub-states: In the first sub-state, both the first NMOS transistor and the second NMOS transistor are in the on state, and the third NMOS transistor is in the off state, thus forming an independent discharge path controlled by the first ferroelectric field-effect transistor. In the second sub-state, both the first NMOS transistor and the third NMOS transistor are in the on state, while the second NMOS transistor is in the off state, thus forming an independent pull-up path controlled by the second ferroelectric field-effect transistor.

[0011] Preferably, the core computing module is configured to perform a NOR operation: by establishing and maintaining the first electrical connection relationship, and based on the threshold voltage states of the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor, a voltage representing the result of the NOR operation is generated at the first control terminal; Wherein, the first voltage input terminal and the second voltage input terminal are configured to receive a low level, and the fifth control terminal and the sixth control terminal are configured to receive the same low-level reference potential; The second control terminal is configured to have two operating modes: pre-charge and evaluation. In the pre-charge operating mode, the second control terminal is configured to receive a low-level control signal, and the first control terminal is pre-charged to the read voltage. In the evaluation operating mode, the second control terminal, the third control terminal, and the fourth control terminal are configured to receive a high-level control signal to establish and maintain the first electrical connection.

[0012] Further defined, the voltage representation relationship of the NOR logic operation result is configured as follows: when at least one of the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor is in a low threshold voltage state, the voltage on the first control terminal represents the NOR logic operation result as logic '0'; when both the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor are in a high threshold voltage state, the voltage on the first control terminal represents the NOR logic operation result as logic '1'.

[0013] Preferably, the core operation module is configured to perform an implicit logic operation on logic signal A implied by logic signal B, i.e., (NOT A) OR B: by establishing and maintaining a first sub-state under the second electrical connection relationship, and based on the threshold voltage state of the first ferroelectric field-effect transistor, a voltage representing an intermediate result corresponding to NOT A is generated at the first control terminal; by establishing and maintaining a second sub-state under the second electrical connection relationship, and based on the intermediate result and the threshold voltage state of the second ferroelectric field-effect transistor, a voltage representing the result of the implicit logic operation is generated at the first control terminal; Wherein, the first voltage input terminal and the second voltage input terminal are configured to receive a low level, the fifth control terminal is configured to receive a high level reference potential, and the sixth control terminal is configured to receive a low level reference potential; The second control terminal is configured to have two operating modes: pre-charge and evaluation. In the pre-charge operating mode, the second control terminal is configured to receive a low-level control signal, and the first control terminal is pre-charged to the read voltage. In the evaluation operating mode, the second control terminal is configured to receive a high-level control signal, and the third and fourth control terminals are configured to receive different combinations of control signals to establish and maintain the first sub-state and the second sub-state, respectively.

[0014] Further specified, the logic signal A is stored through the threshold voltage state of the first ferroelectric field-effect transistor, and the logic signal B is stored through the threshold voltage state of the second ferroelectric field-effect transistor; The voltage representation relationship of the intermediate result is configured as follows: when the logic signal A is logic signal '1' and the first ferroelectric field-effect transistor is in a low threshold voltage state, the voltage on the first control terminal represents the intermediate result as logic '0'; when the logic signal A is logic signal '0' and the first ferroelectric field-effect transistor is in a high threshold voltage state, the voltage on the first control terminal represents the intermediate result as logic '1'. The voltage representation relationship of the implied logic operation result is configured as follows: when the intermediate result is logic '1', and the second ferroelectric field-effect transistor is in a high threshold voltage state or a low threshold voltage state, the voltage at the first control terminal represents the implied logic operation result as logic '1'; when the intermediate result is logic '0', and the logic signal B is logic signal '1', and the second ferroelectric field-effect transistor is in a low threshold voltage state, the voltage at the first control terminal represents the implied logic operation result as logic '1'; when the intermediate result is logic '0', and the logic signal B is logic signal '0', and the second ferroelectric field-effect transistor is in a high threshold voltage state, the voltage at the first control terminal represents the implied logic operation result as logic '0'. The third control terminal and the fourth control terminal are configured to receive high-level control signals and low-level control signals respectively, so as to establish and maintain the first sub-state; The third control terminal and the fourth control terminal are configured to receive low-level control signals and high-level control signals respectively, so as to establish and maintain the second sub-state.

[0015] Preferably, the core computing module is configured to implement the functions of a non-volatile ternary content-addressable memory to obtain data matching results, including data storage, data search, and data matching; The threshold voltage state combination of the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor is configured as non-volatile memory ternary data to realize the data storage, wherein the ternary data includes logical data '0', '1' and 'X'; During the data search, the first voltage input terminal and the second voltage input terminal are configured to receive a low level, and the fifth control terminal and the sixth control terminal are configured to receive a low-level reference potential; the second control terminal is configured to have two operating modes: pre-charge and search enable; in the pre-charge operating mode, the second control terminal is configured to receive a low-level control signal, and the first control terminal is pre-charged to the read voltage; in the search enable operating mode, the second control terminal is configured to receive a high-level control signal, and the third control terminal and the fourth control terminal are configured to receive a level combination corresponding to the logic data to be searched, so as to establish and maintain the first sub-state or the second sub-state required for the data search; The voltage response of the first control terminal is configured to determine whether the searched logical data matches the stored logical data, thereby achieving the data matching.

[0016] Further specifying, the threshold voltage state combination of the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor is configured as follows: when storing logic data '0', the first ferroelectric field-effect transistor is in a low threshold voltage state and the second ferroelectric field-effect transistor is in a high threshold voltage state; when storing logic data '1', the first ferroelectric field-effect transistor is in a high threshold voltage state and the second ferroelectric field-effect transistor is in a low threshold voltage state; when storing logic data 'X', both the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor are in a high threshold voltage state.

[0017] Further specifying, the level combination configured for the third control terminal and the fourth control terminal is as follows: when searching for logic data '0', the third control terminal is configured to receive a low-level control signal, and the fourth control terminal is configured to receive a high-level control signal; when searching for logic data '1', the third control terminal is configured to receive a high-level control signal, and the fourth control terminal is configured to receive a low-level control signal. The voltage response of the first control terminal is as follows: when the searched logical data matches the stored logical data, the first control terminal maintains a high level; when the searched logical data does not match the stored logical data, the first control terminal presents a low level.

[0018] Compared with the prior art, the advantages of this utility model are: 1) This invention fundamentally solves the technical problem of inconsistent logic output paths in existing technologies by fixing the result output terminal to the single output node (such as the first control terminal) of the core computing module. Regardless of the logic function (such as NOR or IMP) or operating mode (such as NV-TCAM search) configured for the circuit, the final result is output from this single, fixed physical node. This eliminates the additional signal gating or receiving circuits required in existing technologies due to inconsistent logic output paths, greatly simplifies peripheral circuit design, and reduces the resource overhead and complexity of the integrated array.

[0019] 2) This invention introduces a reconfigurable switching network containing at least three controlled switching devices, and dynamically changes the electrical connection between two FeFETs in response to multiple control signals, thereby achieving inherent reconfigurability at the hardware level. This directly overcomes the rigid architecture problem caused by relying on complex preset timing logic control in existing technologies. Specifically, this invention allows the same hardware circuit to flexibly switch between different modes, such as parallel discharge paths (e.g., the first electrical connection relationship) and independent control paths (e.g., the second electrical connection relationship), simply by changing the combination of control signals. This efficiently supports various computing paradigms, from basic Boolean logic (e.g., NOR) to complex logic requiring step-by-step operations (e.g., IMP), breaking through the bottlenecks of existing technologies in terms of functional diversity and flexibility.

[0020] 3) The symmetrical structure and reconfigurable nature of this circuit naturally integrate all the hardware elements required to build a non-volatile ternary content-addressable memory (NV-TCAM). By dynamically configuring electrical connections, this circuit can search for different logical data, successfully expanding its application scope from general logic operations to high-performance in-memory search, significantly improving the functional density and energy efficiency of the in-memory computing architecture.

[0021] 4) This invention achieves powerful reconfigurability while maintaining the simplicity of the circuit structure and fully utilizes the non-volatile memory characteristics of FeFETs to reduce static power consumption. Due to its good compatibility with standard CMOS processes, this circuit is very suitable for high-density, large-scale integration, providing a practical circuit-level solution for overcoming the "memory wall" and "power wall". Attached Figure Description

[0022] Figure 1 The transfer characteristic curve of a single FeFET (I) ds -V gs (Curve) Schematic diagram; Figure 2 This is a schematic diagram of the multifunctional logic operation circuit of this utility model; Figure 3A schematic diagram for writing a high threshold voltage state (HVT) into the first ferroelectric field-effect transistor Fe1; Figure 4 A schematic diagram for writing a low threshold voltage state (LVT) into the first ferroelectric field-effect transistor Fe1; Figure 5 A schematic diagram illustrating the writing of a high threshold voltage state (HVT) into the second ferroelectric field-effect transistor Fe2; Figure 6 A schematic diagram for writing a low threshold voltage state (LVT) into the second ferroelectric field-effect transistor Fe2; Figure 7 A schematic diagram for reading the threshold voltage state of the first ferroelectric field-effect transistor Fe1; Figure 8 A schematic diagram for reading the threshold voltage state of the second ferroelectric transistor Fe2; Figure 9 for Figure 2 The diagram shown illustrates the implementation of NOR logic operation by a multi-functional logic circuit. Figure 10 for Figure 2 The diagram shown illustrates the implementation of implied (IMP) logic operations by a multifunctional logic operation circuit. Figure 11 for Figure 2 The diagram shown illustrates the implementation of a non-volatile ternary content-addressable memory (NV-TCAM) using a multi-functional logic operation circuit. Detailed Implementation

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0024] A ferroelectric field-effect transistor (FeFET) is constructed by adding a layer of ferroelectric material to the gate of a traditional metal-oxide-semiconductor field-effect transistor (MOSFET). Ferroelectric materials are materials containing spontaneously polarizable crystals, possessing two polarization states—positive and negative—that can be reversed by an external electric field. When an electric field is applied, the electric dipoles formed in the ferroelectric material's crystal structure align with the direction of the electric field. After the electric field is removed, the electric dipoles retain this polarization state, thus making the ferroelectric material non-volatile. When a positive voltage is applied to the gate of an N-type FeFET, the ferroelectric layer polarizes downwards, and its polarization charge enhances the gate electric field, effectively lowering the threshold voltage. This induces electrons to form a conductive channel, at which point the FeFET turns on, a state known as the low threshold voltage (Low V) state. THWhen a negative voltage is applied to the gate of an N-type FeFET, the ferroelectric layer polarization direction is upward, and its polarization charge weakens the gate electric field, which is equivalent to raising the threshold voltage. This causes the conductive channel to be depleted and unable to conduct, at which point the FeFET is turned off, a state known as the high threshold voltage state (LVT). TH State, HVT).

[0025] In a FeFET, the drain-source current is called Id. ds The voltage between the gate and source is called V. gs The voltage between the drain and source is called V. ds . Figure 1 The transfer characteristic curves of a single FeFET are shown (I). ds -V gs The curve exhibits obvious hysteresis characteristics. Figure 1 As shown, in V ds When V = 1V, apply V gs At 0.4V, electrons are induced downwards by the polarization direction of the ferroelectric layer, forming a conductive channel. ds The voltage V increases instantaneously to around 4.5 mA; then gradually decreases. gs I ds It did not decrease until V gs At -1.4V, the polarization direction of the ferroelectric layer changes to upward, the conductive channel disappears, and the FeFET is in HVT. ds Reduce to 0mA; cancel V at -1.4V. gs Afterwards, the polarization direction of the ferroelectric layer remains upward, and the FeFET remains in the high-voltage voltammetry (HVT). Due to the non-volatility of ferroelectric materials, even if V is removed... gs The voltage and the polarization direction of the ferroelectric layer do not change, so the threshold voltage of the FeFET remains unchanged, thus enabling the FeFET to achieve non-volatile data storage.

[0026] This invention proposes a multifunctional logic operation circuit based on a ferroelectric field-effect transistor, such as... Figure 2 As shown, it includes: a first voltage input terminal V in1 Second voltage input terminal V in2 First control terminal V ML Second control terminal V WL Third control terminal V SL Fourth control terminal V SCL Fifth control terminal V O and the sixth control terminal V TThe core computing module has a single output node and includes: a first NMOS transistor M1, whose gate is connected to the second control terminal V. WL Its source is connected to the first control terminal V. ML The second NMOS transistor M2 has its gate connected to the third control terminal V. SL The third NMOS transistor, M3, has its gate connected to the fourth control terminal, V. SCL Its drain is connected to the fifth control terminal V. O The first ferroelectric field-effect transistor Fe1 has its gate connected to the first voltage input terminal V. in1 Its source is connected to the drain of the second NMOS transistor M2, and its drain is connected to the sixth control terminal V. T The second ferroelectric field-effect transistor Fe2 has its gate connected to the second voltage input terminal V. in2 Its source is connected to the drain of the first NMOS transistor M1 and the source of the second NMOS transistor M2, and its drain is connected to the source of the third NMOS transistor M3; the three controlled switching devices, the first NMOS transistor M1, the second NMOS transistor M2, and the third NMOS transistor M3, constitute a reconfigurable switching network; the output node is the first control terminal V. ML The core computing module is configured to respond to multiple control signals via the second control terminal V. WL Third control terminal V SL and the fourth control terminal V SCL The received control signal correspondingly changes the on / off states of the first NMOS transistor M1, the second NMOS transistor M2, and the third NMOS transistor M3, dynamically altering the electrical connection between the first ferroelectric field-effect transistor Fe1 and the second ferroelectric field-effect transistor Fe2. Based on these different electrical connections and the threshold voltage states of Fe1 and Fe2, a voltage representing different logic operations or data matching results is generated at the output node. The result output terminal is connected to the output node, i.e., the first control terminal V. ML It is used to output the results of logical operations or data matching operations of the core computing module.

[0027] To further specify, the electrical connection relationships must have at least the following two types: Under the first electrical connection relationship, the first NMOS transistor M1, the second NMOS transistor M2, and the third NMOS transistor M3 are all in the on state. At this time, the sources of the first ferroelectric field-effect transistor Fe1 and the second ferroelectric field-effect transistor Fe2 are connected to each other through the on-state second NMOS transistor M2, forming a parallel discharge path jointly controlled by the first ferroelectric field-effect transistor Fe1 and the second ferroelectric field-effect transistor Fe2.

[0028] Under the second electrical connection relationship, there are two sub-states: In the first sub-state, both the first NMOS transistor M1 and the second NMOS transistor M2 are in the ON state, while the third NMOS transistor M3 is in the OFF state. This forms an independent discharge path controlled by the first ferroelectric field-effect transistor Fe1. In the second sub-state, both the first NMOS transistor M1 and the third NMOS transistor M3 are in the ON state, while the second NMOS transistor M2 is in the OFF state. This forms an independent pull-up path controlled by the second ferroelectric field-effect transistor Fe2.

[0029] As mentioned above, both the first ferroelectric field-effect transistor Fe1 and the second ferroelectric field-effect transistor Fe2 are N-type ferroelectric field-effect transistors.

[0030] Figure 3 A schematic diagram is shown showing the writing of a high threshold voltage state (HVT) into the first ferroelectric field-effect transistor Fe1. Figure 4 A schematic diagram illustrates the writing of a low threshold voltage state (LVT) to a first ferroelectric field-effect transistor Fe1. During the write operation on the first ferroelectric field-effect transistor Fe1, the second control terminal V... WL and the third control terminal V SL Maintaining a high level, the second voltage input terminal V in2 Fourth control terminal V SCL Fifth control terminal V O and the sixth control terminal V T The voltage level remains low. Under this condition, the first NMOS transistor M1 and the second NMOS transistor M2 remain on, while the third NMOS transistor M3 remains off. The first ferroelectric field-effect transistor Fe1 is subjected to its V... gs (from the first voltage input terminal V) in1 and the first control terminal V ML The internal polarization state will change due to the influence of the voltage difference (which determines the polarization). Figure 3 In the middle, when the first control terminal V ML Connect to high voltage V w And the first voltage input terminal V in1 After applying a low voltage (0V), the V of the first ferroelectric field-effect transistor Fe1... gs =-V W V W At 2V, the polarization direction of the ferroelectric layer of the first ferroelectric field-effect transistor Fe1 is upward, so the first ferroelectric field-effect transistor Fe1 is written into the high threshold voltage state (HVT). Figure 4 In the middle, when the first control terminal V ML Connect to a low voltage (0V), and the first voltage input terminal V in1 Connect to high voltage V w Subsequently, the V of the first ferroelectric field-effect transistor Fe1 gs =V WAt this time, the polarization direction of the ferroelectric layer of the first ferroelectric field-effect transistor Fe1 is downward, so the first ferroelectric field-effect transistor Fe1 is written to the low threshold voltage state (LVT).

[0031] Figure 5 A schematic diagram is shown illustrating the writing of a high threshold voltage state (HVT) into the second ferroelectric field-effect transistor Fe2. Figure 6 A schematic diagram illustrates the writing of a low threshold voltage state (LVT) to a second ferroelectric field-effect transistor Fe2. During the write operation on the second ferroelectric field-effect transistor Fe2, the second control terminal V... WL Maintain a high level, third control terminal V SL Fourth control terminal V SCL Fifth control terminal V O and the sixth control terminal V T The voltage level remains low. Under this condition, the first NMOS transistor M1 remains on, while the second NMOS transistors M2 and M3 remain off, preventing the threshold voltage state of the first ferroelectric field-effect transistor Fe1 from being affected. The second ferroelectric field-effect transistor Fe2 is affected by its V... gs (From the second voltage input terminal V) in2 and the first control terminal V ML The internal polarization state will change due to the influence of the voltage (which determines the polarization). Figure 5 In the middle, when the first control terminal V ML Connect to high voltage V w And the second voltage input terminal V in2 After applying a low voltage (0V), the V of the second ferroelectric field-effect transistor Fe2... gs =-V W V W At 2V, the polarization direction of the ferroelectric layer of the second ferroelectric field-effect transistor Fe2 is upward, so the second ferroelectric field-effect transistor Fe2 is written to the high threshold voltage state (HVT). Figure 6 In the middle, when the first control terminal V ML Connect to a low voltage (0V), and the second voltage input terminal V in2 Connect to high voltage V w Subsequently, the V of the second ferroelectric field-effect transistor Fe2 gs =V W At this time, the polarization direction of the ferroelectric layer of the second ferroelectric field-effect transistor Fe2 is downward, so the second ferroelectric field-effect transistor Fe2 is written into the low threshold voltage state (LVT).

[0032] It should be noted that, in order to prevent the second ferroelectric field-effect transistor Fe2, which has been pre-written with a threshold voltage state, from being affected by the first control terminal V when the first ferroelectric field-effect transistor Fe1 is written with a threshold voltage state, MLDue to the influence of this, the writing order is specified as follows: first, the first ferroelectric field-effect transistor Fe1 is written, and then the second ferroelectric field-effect transistor Fe2 is written.

[0033] Ferroelectric field-effect transistors can utilize their different threshold voltage states (HVT or LVT) to achieve non-volatile data storage. Figure 7 A schematic diagram showing the threshold voltage state of the first ferroelectric field-effect transistor Fe1 is presented. Figure 8 A schematic diagram showing the threshold voltage state of the second ferroelectric field-effect transistor Fe2 is presented.

[0034] Figure 7 In the process of reading the threshold voltage state of the first ferroelectric field-effect transistor Fe1, the first voltage input terminal V in1 Fourth control terminal V SCL Fifth control terminal V O and the sixth control terminal V T When connected to a low level, the third control terminal V SL A high-level signal is applied to turn on the second NMOS transistor M2. First, the second control terminal V... WL A low-level input turns off the first NMOS transistor M1, and the first control terminal V... ML Precharge to read voltage V read =2V; then the second control terminal V WL Switching to a high level turns on the first NMOS transistor M1; then observe the first control terminal V. ML The threshold voltage state of the first ferroelectric field-effect transistor Fe1 is determined by whether the voltage at the first control terminal V drops. ML If the voltage drops, it indicates that the first ferroelectric field-effect transistor Fe1 is in a low threshold voltage (LVT) state; if the first control terminal V ML If the voltage remains constant, it indicates that the first ferroelectric field-effect transistor Fe1 is in a high threshold voltage state (HVT).

[0035] Figure 8 In the process of reading the threshold voltage state of the second ferroelectric field-effect transistor Fe2, the second voltage input terminal V in2 When connected to a low level, the third control terminal V SL A low-level input turns off the second NMOS transistor M2, and the fourth control terminal V... SCL A high-level signal turns on the third NMOS transistor M3, and the fifth control terminal V... O and the sixth control terminal V T Connect to a low level. First, connect the second control terminal V. WL A low-level input turns off the first NMOS transistor M1, and the first control terminal V... ML Precharge to read voltage V read=2V; then the second control terminal V WL Switching to a high level turns on the first NMOS transistor M1; then observe the first control terminal V. ML The threshold voltage state of the second ferroelectric field-effect transistor Fe2 is determined by whether the voltage at the first control terminal V drops. ML If the voltage drops, it indicates that the second ferroelectric field-effect transistor Fe2 is in a low threshold voltage (LVT) state; if the first control terminal V ML If the voltage remains constant, it indicates that the second ferroelectric field-effect transistor Fe2 is in a high threshold voltage (HVT) state.

[0036] The multifunctional logic operation circuit is used to implement the following function: the core operation module is configured to perform NOR logic operation: by establishing and maintaining a first electrical connection relationship, and based on the threshold voltage states of the first ferroelectric field-effect transistor Fe1 and the second ferroelectric field-effect transistor Fe2, at the first control terminal V ML The voltage that generates the result of a logical or non-logical operation is generated.

[0037] Figure 9 Showing Figure 2 The diagram shown illustrates a multi-functional logic circuit implementing a NOR logic operation. The result of the NOR logic operation is controlled by the first control terminal V. ML The high and low levels of the logic signal represent the logic signal '1' and '0', respectively. The rule for NOR logic operation is: when both logic signals A and B are logic signals '0', the output is logic signal '1'; otherwise, the output is logic signal '0'.

[0038] Write phase: according to Figure 3 or Figure 4 Write the threshold voltage state corresponding to logic signal A into the first ferroelectric field-effect transistor Fe1, according to... Figure 5 or Figure 6 Write the threshold voltage state corresponding to logic signal B to the second ferroelectric field-effect transistor Fe2. Logic signal '1' corresponds to the low threshold voltage state (LVT), and logic signal '0' corresponds to the high threshold voltage state (HVT).

[0039] Circuit configuration phase: After writing is complete, input voltage to the first voltage input terminal V. in1 Second voltage input terminal V in2 Apply a low level to the fifth control terminal V O and the sixth control terminal V T Apply the same low level as the reference potential.

[0040] Execution phase: First, the second control terminal V... WL Configured for pre-charge operation mode, sending power to the second control terminal VWL Applying a low-level control signal turns off the first NMOS transistor M1, thereby turning off the first control terminal V. ML Precharge to read voltage V read Then connect the second control terminal V. WL Configure it to evaluation mode, and set the second control terminal V WL Switching to a high-level control signal turns on the first NMOS transistor M1 and sends a signal to the third control terminal V. SL Applying a high-level control signal turns on the second NMOS transistor M2, sending a signal to the fourth control terminal V. SCL A high-level control signal is applied to turn on the third NMOS transistor M3 to establish and maintain the first electrical connection, thereby allowing the first control terminal V to be controlled according to the threshold voltage states of the first ferroelectric field-effect transistor Fe1 and the second ferroelectric field-effect transistor Fe2. ML Generates a voltage representing the result of a logical or non-logical operation. Reads the voltage from the first control terminal V. ML The voltage, as long as at least one of the logic signals A or B is logic signal '1' (i.e., at least one of the first ferroelectric field-effect transistors Fe1 and Fe2 is in a low threshold voltage (LVT) state and is turned on), at least one discharge path is open, and the first control terminal V ML The voltage will quickly discharge to a low level, or the result of the NOT operation will be logic '0'; only when both logic signals A and B are logic signals '0' (i.e., the first ferroelectric field-effect transistor Fe1 and the second ferroelectric field-effect transistor Fe2 are both in the high threshold voltage state (HVT) and turned off), both discharge paths are blocked, and the first control terminal V ML Maintain pre-charge voltage V read The result of the OR operation is '1'. Therefore, the result of the logical operation is NOT(A OR B), which means... .

[0041] The second function of this multi-functional logic operation circuit is that the core operation module is configured to perform implied (IMP) logic operations, specifically, logic signal A implies logic signal B, i.e., (NOT A) OR B: by establishing and maintaining the first sub-state under the second electrical connection relationship, and based on the threshold voltage state of the first ferroelectric field-effect transistor Fe1, at the first control terminal V ML A voltage is generated at the first control terminal V, representing the intermediate result corresponding to NOT A; by establishing and maintaining the second sub-state under the second electrical connection relationship, and based on the intermediate result and the threshold voltage state of the second ferroelectric transistor Fe2, a voltage is generated at the first control terminal V. MLA voltage representing the result of a logical operation is generated. Logic signal A is stored using the threshold voltage state of the first ferroelectric field-effect transistor Fe1, and logic signal B is stored using the threshold voltage state of the second ferroelectric field-effect transistor Fe2.

[0042] Figure 10 Showing Figure 2 The diagram shown illustrates a multi-functional logic operation circuit implementing implied (IMP) logic operations. The result of the implied logic operation is controlled by the first control terminal V. ML The high and low levels of the signal indicate the logic level. The rule for IMP logic operation is: when logic signal A is logic signal '1' and logic signal B is logic signal '0', the output is logic signal '0'; otherwise, the output is logic signal '1'.

[0043] Write phase: according to Figure 3 or Figure 4 Write the threshold voltage state corresponding to logic signal A into the first ferroelectric field-effect transistor Fe1, according to... Figure 5 or Figure 6 Write the threshold voltage state corresponding to logic signal B into the second ferroelectric field-effect transistor Fe2.

[0044] Circuit configuration phase: After writing is complete, input voltage to the first voltage input terminal V. in1 Second voltage input terminal V in2 Apply a low level to the fifth control terminal V O Apply a high-level reference potential to the sixth control terminal V. T Apply a low-level reference potential.

[0045] Execution phase: First, the second control terminal V... WL Configured for pre-charge operation mode, sending power to the second control terminal V WL Applying a low-level control signal turns off the first NMOS transistor M1, causing the first control terminal V to... ML Precharge to read voltage V read Then connect the second control terminal V. WL Configure it to evaluation mode, and set the second control terminal V WL Switching to a high-level control signal turns on the first NMOS transistor M1. If the circuit is considered a symmetrical structure, then a "left-first, right-second" operation can be performed during calculation. The calculation is divided into two steps: first, a signal is sent to the third control terminal V. SL Applying a high-level control signal turns on the second NMOS transistor M2, sending a signal to the fourth control terminal V. SCL Applying a low-level control signal turns off the third NMOS transistor M3 to establish and maintain the first sub-state, thereby allowing control at the first control terminal V based on the threshold voltage state of the first ferroelectric field-effect transistor Fe1. MLGenerate a voltage representing the intermediate result corresponding to NOT A; then read the first control terminal V. ML If the logic signal A is logic signal '1' (i.e., the first ferroelectric field-effect transistor Fe1 is in a low threshold voltage (LVT) state and is turned on), then the first control terminal V ML Discharging to a low level, the intermediate result NOT A of the first step is logic '0'; if logic signal A is logic signal '0' (i.e., the first ferroelectric field-effect transistor Fe1 is in a high threshold voltage state (HVT) and is turned off), then the first control terminal V ML The voltage maintains the pre-charge voltage V read The intermediate result NOT A from the first step remains unchanged, and is logic '1'. The second step involves sending a signal to the third control terminal V. SL Applying a low-level control signal turns off the second NMOS transistor M2, sending a signal to the fourth control terminal V. SCL A high-level control signal is applied to turn on the third NMOS transistor M3 to establish and maintain the second sub-state. This allows the signal to be applied at the first control terminal V based on intermediate results and the threshold voltage state of the second ferroelectric transistor Fe2. ML Generate a voltage representing the result of the logical operation; then read the first control terminal V. ML If the intermediate result NOT A in the first step is logic '1', then regardless of the threshold voltage state of the second ferroelectric field-effect transistor Fe2 caused by the logic signal B, the final first control terminal V... ML All will maintain the pre-charge voltage V read If the intermediate result NOT A in the first step is logic '0', and logic signal B is logic signal '1' (the second ferroelectric field-effect transistor Fe2 is in a low threshold voltage state (LVT) and is turned on), then the first control terminal V ML The voltage is pulled up to the fifth control terminal V through the second ferroelectric field-effect transistor Fe2 and the third NMOS transistor M3. O The applied high-level reference potential will eventually output logic '1'; if the intermediate result NOT A in the first step is logic '0', but logic signal B is logic signal '0' (the second ferroelectric field-effect transistor Fe2 is in a high threshold voltage state (HVT) and is turned off), then the first control terminal V ML The voltage cannot be pulled up, remaining at a low level, ultimately resulting in a logic '0' output. Therefore, the implied logic operation result is (NOT A) OR B, i.e. .

[0046] The multifunctional logic circuit is used to implement the core operation module, which is configured to implement the non-volatile ternary content-addressable memory (NV-TCAM) function to obtain data matching results, including data storage, data search, and data matching.

[0047] Figure 11 Showing Figure 2 The diagram shows a multi-functional logic operation circuit implementing the function of a non-volatile ternary content-addressable memory (NV-TCAM). This NV-TCAM employs a separate path design, meaning that write operations during data storage and data search operations use different physical paths. This ensures that the threshold voltage state of the ferroelectric field-effect transistor is not accidentally changed during data search, effectively avoiding read interference and significantly improving the reliability and operational lifespan of the non-volatile memory.

[0048] This NV-TCAM is a NOR type structure, characterized by the following: when at least one bit of the search data and the stored data do not match, the first control terminal V... ML The voltage will change.

[0049] The implementation of NV-TCAM functions is based on its data storage, data search, and data matching: 1) Data storage First, according to Figure 3 or Figure 4 Write the threshold voltage state corresponding to logic signal A into the first ferroelectric field-effect transistor Fe1, according to... Figure 5 or Figure 6 The threshold voltage state corresponding to the logic signal B is written to the second ferroelectric field-effect transistor Fe2. Then, the threshold voltage states of the first ferroelectric field-effect transistor Fe1 and the second ferroelectric field-effect transistor Fe2 are used to non-volatilely store the three data elements ('0', '1', and 'X'), where the logic data 'X' is an indeterminate state, which can be treated as either logic data '0' or logic data '1'. Because ferroelectric field-effect transistors are non-volatile, the stored logic data is retained even when the NV-TCAM is powered off, achieving non-volatile storage. The specific data storage rules, i.e., the configuration of the threshold voltage state combinations of the first ferroelectric field-effect transistor Fe1 and the second ferroelectric field-effect transistor Fe2, are shown in Table 1.

[0050] Table 1. Threshold voltage states written to the first ferroelectric field-effect transistor Fe1 and the second ferroelectric field-effect transistor Fe2 when storing logic data in NV-TCAM.

[0051] As shown in Table 1, the storage of three data points is achieved through the following combinations of threshold voltage states: when storing logic data '0', a low threshold voltage state (LVT) and a high threshold voltage state (HVT) are written to the first ferroelectric field-effect transistor Fe1 and the second ferroelectric field-effect transistor Fe2, respectively; when storing logic data '1', a high threshold voltage state (HVT) and a low threshold voltage state (LVT) are written to the first ferroelectric field-effect transistor Fe1 and the second ferroelectric field-effect transistor Fe2, respectively; when storing logic data 'X', a high threshold voltage state (HVT) is written to both the first ferroelectric field-effect transistor Fe1 and the second ferroelectric field-effect transistor Fe2.

[0052] 2) Data Search To the first voltage input terminal V in1 Second voltage input terminal V in2 Apply a low level to the fifth control terminal V. O and the sixth control terminal V T Connect to a low-level reference potential.

[0053] Second control terminal V WL It is configured to operate in two modes: pre-charge and search enable. During the pre-charging phase, the second control terminal V WL Configured to pre-charge operating mode, sending power to the second control terminal V WL Applying a low-level control signal turns off the first NMOS transistor M1, thereby turning off the first control terminal V. ML Precharge to read voltage V read .

[0054] During the search execution phase, the second control terminal V WL Configured to search-enabled operating mode, the second control terminal V WL Switching to a high-level control signal turns on the first NMOS transistor M1. Then, based on the logic data to be searched, the third control terminal V is... SL and the fourth control terminal V SCL Different combinations of voltage levels are applied, as shown in Table 2.

[0055] Table 2 shows the gate voltage levels applied to the second NMOS transistor M2 and the third NMOS transistor M3 during NV-TCAM logic data search.

[0056] As shown in Table 2, when the search logic data is '0', the third control terminal V... SL and the fourth control terminal V SCL Apply a low-level control signal (0V) and a high-level control signal (1V) respectively to establish and maintain the second sub-state; when searching for logic data '1', apply a control signal to the third control terminal V.SL and the fourth control terminal V SCL Apply a high-level control signal (1V) and a low-level control signal (0V) respectively to establish and maintain the first sub-state.

[0057] 3) Data matching By detecting the first control terminal V ML Pre-charge voltage V read Whether a voltage drop occurs is used to determine whether the searched logical data matches the stored logical data. Specifically, if the searched logical data completely matches the stored logical data (or the stored logical data is 'X'), then the first control terminal V... ML An effective discharge path cannot be formed between the first control terminal V and the low level (ground). ML The voltage will remain at the pre-charge voltage V. read The first control terminal V remains unchanged; if the searched logical data does not match at least one bit with the stored logical data, then... ML An effective discharge path is formed between the voltage level and the low level (ground), causing the first control terminal V to... ML The voltage is rapidly pulled down to 0V. Based on the first sub-state (the searched logic data is '1') or the second sub-state (the searched logic data is '0') and the threshold voltage states of the first ferroelectric field-effect transistor Fe1 and the second ferroelectric field-effect transistor Fe2 (which determine the stored logic data), the first control terminal V is made... ML A voltage representing the data matching result is generated at the first control terminal V. That is, by monitoring the first control terminal V... ML By determining the final voltage state, it is possible to accurately determine whether the searched logical data matches the stored logical data.

Claims

1. A multifunctional logic operation circuit based on a ferroelectric field-effect transistor, characterized in that... include: First voltage input terminal and second voltage input terminal; The core computing module consists of a first ferroelectric field-effect transistor, a second ferroelectric field-effect transistor, and a reconfigurable switching network, and has a unique output node. The gates of the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor are respectively connected to the first voltage input terminal and the second voltage input terminal. The reconfigurable switching network is connected to the source and drain of the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor, and includes at least three controlled switching devices. The core computing module is configured to: respond to multiple control signals, dynamically change the electrical connection relationship between the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor by changing the on / off state of the controlled switching device, and then, based on the different electrical connection relationships and the threshold voltage states of the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor, generate a voltage on the output node that represents different logic operations or data matching results. The result output terminal is connected to the output node.

2. The multifunctional logic operation circuit based on a ferroelectric field-effect transistor according to claim 1, characterized in that... The circuit further includes a first control terminal, a second control terminal, a third control terminal, a fourth control terminal, a fifth control terminal, and a sixth control terminal. The controlled switching devices are a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The gate of the first NMOS transistor is connected to the second control terminal, and its source is connected to the first control terminal. The gate of the second NMOS transistor is connected to the third control terminal. The gate of the third NMOS transistor is connected to the fourth control terminal, and its drain is connected to the fifth control terminal. The on / off states of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are changed accordingly by the control signals received by the second control terminal, the third control terminal, and the fourth control terminal. The source of the first ferroelectric field-effect transistor is connected to the drain of the second NMOS transistor, and its drain is connected to the sixth control terminal. The source of the second ferroelectric field-effect transistor is connected to the drain of the first NMOS transistor and the source of the second NMOS transistor, and its drain is connected to the source of the third NMOS transistor. The output node is the first control terminal.

3. A multifunctional logic operation circuit based on a ferroelectric field-effect transistor according to claim 2, characterized in that... The electrical connection relationship has at least two of the following: Under the first electrical connection relationship, the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all in the on state. At this time, the sources of the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor are connected to each other through the on-state second NMOS transistor, forming a parallel discharge path jointly controlled by the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor. Under the second electrical connection relationship, there are two sub-states: In the first sub-state, both the first NMOS transistor and the second NMOS transistor are in the on state, and the third NMOS transistor is in the off state, thus forming an independent discharge path controlled by the first ferroelectric field-effect transistor. In the second sub-state, both the first NMOS transistor and the third NMOS transistor are in the on state, while the second NMOS transistor is in the off state, thus forming an independent pull-up path controlled by the second ferroelectric field-effect transistor.

4. A multifunctional logic operation circuit based on a ferroelectric field-effect transistor according to claim 3, characterized in that... The core computing module is configured to perform NOR operations: by establishing and maintaining the first electrical connection, and based on the threshold voltage states of the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor, a voltage representing the result of the NOR operation is generated at the first control terminal. Wherein, the first voltage input terminal and the second voltage input terminal are configured to receive a low level, and the fifth control terminal and the sixth control terminal are configured to receive the same low-level reference potential; The second control terminal is configured to have two operating modes: pre-charge and evaluation. In the pre-charge operating mode, the second control terminal is configured to receive a low-level control signal, and the first control terminal is pre-charged to the read voltage. In the evaluation operating mode, the second control terminal, the third control terminal, and the fourth control terminal are configured to receive a high-level control signal to establish and maintain the first electrical connection.

5. A multifunctional logic operation circuit based on a ferroelectric field-effect transistor according to claim 4, characterized in that... The voltage representation relationship of the NOR logic operation result is configured as follows: when at least one of the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor is in a low threshold voltage state, the voltage on the first control terminal represents the NOR logic operation result as logic '0'; when both the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor are in a high threshold voltage state, the voltage on the first control terminal represents the NOR logic operation result as logic '1'.

6. A multifunctional logic operation circuit based on a ferroelectric field-effect transistor according to claim 3, characterized in that... The core computing module is configured to perform an implicit logic operation on logic signal A implied by logic signal B, namely (NOT A) OR B: by establishing and maintaining a first sub-state under the second electrical connection relationship, and based on the threshold voltage state of the first ferroelectric field-effect transistor, a voltage representing an intermediate result corresponding to NOT A is generated at the first control terminal; by establishing and maintaining a second sub-state under the second electrical connection relationship, and based on the intermediate result and the threshold voltage state of the second ferroelectric field-effect transistor, a voltage representing the result of the implicit logic operation is generated at the first control terminal; Wherein, the first voltage input terminal and the second voltage input terminal are configured to receive a low level, the fifth control terminal is configured to receive a high level reference potential, and the sixth control terminal is configured to receive a low level reference potential; The second control terminal is configured to have two operating modes: pre-charge and evaluation. In the pre-charge operating mode, the second control terminal is configured to receive a low-level control signal, and the first control terminal is pre-charged to the read voltage. In the evaluation operating mode, the second control terminal is configured to receive a high-level control signal, and the third and fourth control terminals are configured to receive different combinations of control signals to establish and maintain the first sub-state and the second sub-state, respectively.

7. A multifunctional logic operation circuit based on a ferroelectric field-effect transistor according to claim 6, characterized in that... The logic signal A is stored through the threshold voltage state of the first ferroelectric field-effect transistor, and the logic signal B is stored through the threshold voltage state of the second ferroelectric field-effect transistor. The voltage representation relationship of the intermediate result is configured as follows: when the logic signal A is logic signal '1' and the first ferroelectric field-effect transistor is in a low threshold voltage state, the voltage on the first control terminal represents the intermediate result as logic '0'; when the logic signal A is logic signal '0' and the first ferroelectric field-effect transistor is in a high threshold voltage state, the voltage on the first control terminal represents the intermediate result as logic '1'. The voltage representation relationship of the implied logic operation result is configured as follows: when the intermediate result is logic '1', and the second ferroelectric field-effect transistor is in a high threshold voltage state or a low threshold voltage state, the voltage at the first control terminal represents the implied logic operation result as logic '1'; when the intermediate result is logic '0', and the logic signal B is logic signal '1', and the second ferroelectric field-effect transistor is in a low threshold voltage state, the voltage at the first control terminal represents the implied logic operation result as logic '1'; when the intermediate result is logic '0', and the logic signal B is logic signal '0', and the second ferroelectric field-effect transistor is in a high threshold voltage state, the voltage at the first control terminal represents the implied logic operation result as logic '0'. The third control terminal and the fourth control terminal are configured to receive high-level control signals and low-level control signals respectively, so as to establish and maintain the first sub-state; The third control terminal and the fourth control terminal are configured to receive low-level control signals and high-level control signals respectively, so as to establish and maintain the second sub-state.

8. A multifunctional logic operation circuit based on a ferroelectric field-effect transistor according to claim 3, characterized in that... The core computing module is configured to implement the functions of a non-volatile ternary content-addressable memory to obtain data matching results, including data storage, data search, and data matching. The threshold voltage state combination of the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor is configured as non-volatile memory ternary data to realize the data storage, wherein the ternary data includes logical data '0', '1' and 'X'; During the data search, the first voltage input terminal and the second voltage input terminal are configured to receive a low level, and the fifth control terminal and the sixth control terminal are configured to receive a low-level reference potential; the second control terminal is configured to have two operating modes: pre-charge and search enable; in the pre-charge operating mode, the second control terminal is configured to receive a low-level control signal, and the first control terminal is pre-charged to the read voltage; in the search enable operating mode, the second control terminal is configured to receive a high-level control signal, and the third control terminal and the fourth control terminal are configured to receive a level combination corresponding to the logic data to be searched, so as to establish and maintain the first sub-state or the second sub-state required for the data search; The voltage response of the first control terminal is configured to determine whether the searched logical data matches the stored logical data, thereby achieving the data matching.

9. A multifunctional logic operation circuit based on a ferroelectric field-effect transistor according to claim 8, characterized in that... The threshold voltage state combination of the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor is configured as follows: when storing logic data '0', the first ferroelectric field-effect transistor is in a low threshold voltage state and the second ferroelectric field-effect transistor is in a high threshold voltage state; when storing logic data '1', the first ferroelectric field-effect transistor is in a high threshold voltage state and the second ferroelectric field-effect transistor is in a low threshold voltage state; when storing logic data 'X', both the first ferroelectric field-effect transistor and the second ferroelectric field-effect transistor are in a high threshold voltage state.

10. A multifunctional logic operation circuit based on a ferroelectric field-effect transistor according to claim 8 or 9, characterized in that... The level combination configured for the third control terminal and the fourth control terminal is as follows: when searching for logic data '0', the third control terminal is configured to receive a low-level control signal, and the fourth control terminal is configured to receive a high-level control signal; when searching for logic data '1', the third control terminal is configured to receive a high-level control signal, and the fourth control terminal is configured to receive a low-level control signal. The voltage response of the first control terminal is as follows: when the searched logical data matches the stored logical data, the first control terminal maintains a high level; when the searched logical data does not match the stored logical data, the first control terminal presents a low level.

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