Universal flash memory storage module and electronic device
Patent Information
- Application Number
- CN202522228313.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-21
- Publication Date
- 2026-10-27
- Estimated Expiration
- 2035-10-21
AI Technical Summary
但是UFS芯片采用球栅阵列封装(Ball Grid Array,BGA),即直接焊接在主板上,这种封装方式不方便插拔更换和扩容,给笔记本电脑在研发测试阶段进行问题分析带来一定的困难,并且不利于UFS芯片的异步验证导入,增加终端用户使用的不便以及客户售后的维护成本
[0015]应当理解,本部分所描述的内容并非旨在标识本申请的实施例的关键或重要特征,也不用于限制本申请的范围。本申请的其它特征将通过以下的说明书而变得容易理解。
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Figure CN224907588U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic storage, and more particularly to a general-purpose flash memory storage module and electronic device. Background Technology
[0002] Universal Flash Storage (UFS) chips are storage systems that integrate non-volatile memory technology (NAND Flash) and a flash controller protocol, primarily used in consumer electronics. Due to the rapid iteration of UFS chips, their widespread application in consumer electronics, and their decreasing cost, UFS chips are increasingly used in personal laptops. However, UFS chips use Ball Grid Array (BGA) packaging, meaning they are directly soldered onto the motherboard. This packaging method is inconvenient for replacement and capacity expansion, posing challenges for problem analysis during the R&D and testing phase of laptops. It also hinders the asynchronous verification and implementation of UFS chips, increasing inconvenience for end users and after-sales maintenance costs for customers. Utility Model Content
[0003] This application provides a general-purpose flash memory storage module and electronic device to at least solve the above-mentioned technical problems existing in the related art.
[0004] A first aspect of this application provides a universal flash memory module, comprising: a printed circuit board having a pad array and signal traces thereon, the signal traces being used to connect the pad array to an M.2 interface; a universal flash memory chip for storing data, soldered to a first area of the printed circuit board via the pad array; and an M.2 interface located in a second area of the printed circuit board for pluggable connection to an M.2 slot of an external device, thereby enabling a physical connection between the universal flash memory chip and the external device, and enabling data transmission between the universal flash memory chip and the external device based on the physical connection.
[0005] In one embodiment, the general-purpose flash memory module includes a power management circuit, which includes a main power input circuit and an interface power circuit. The main power input circuit is used to provide operating power to the general-purpose flash memory chip, and the interface power circuit is used to provide interface voltage to the M.2 interface.
[0006] In one embodiment, the general-purpose flash memory module further includes a detection circuit for detecting whether the general-purpose flash memory module is correctly inserted into the M.2 slot of the external device, and when the general-purpose flash memory module is detected to be correctly inserted into the M.2 slot of the external device, a detection signal is sent to the external device to instruct the external device to transmit data with the general-purpose flash memory module.
[0007] In one embodiment, the physical dimensions of the general-purpose flash memory module are 22 mm wide, and the interface type of the general-purpose flash memory module is M.2 interface.
[0008] In one possible implementation, the capacity of the general-purpose flash memory storage module is 128 gigabytes or 256 gigabytes.
[0009] A second aspect of this application provides an electronic device comprising: a central processing unit (CPU) supporting a general-purpose flash memory protocol and a high-speed serial computer expansion bus standard; and an M.2 slot electrically connected to the CPU; wherein the aforementioned general-purpose flash memory module is inserted into the M.2 slot of the electronic device via an M.2 interface, thereby connecting the general-purpose flash memory module to the CPU.
[0010] In one possible implementation, the central processing unit is used to detect a clock signal from the M.2 slot when the device is powered on, and to determine, based on the clock signal, whether the device inserted into the M.2 slot of the electronic device is a general flash memory storage module or a solid-state drive.
[0011] In one possible implementation, the central processing unit is specifically configured to determine that the device type inserted into the M.2 slot of the electronic device is a solid-state drive and enable the high-speed serial computer expansion bus standard when the frequency of the clock signal detected is high; and to determine that the device type inserted into the M.2 slot of the electronic device is a general-purpose flash memory module and enable the general-purpose flash memory protocol when the frequency of the clock signal detected is low.
[0012] In one possible implementation, the central processing unit (CPU) is a large-core platform or a Qualcomm platform. The CPU's two high-speed data transmission channels are connected to a general-purpose flash memory module via an M.2 slot, enabling the general-purpose flash memory storage protocol. Two of the CPU's four independent data transmission channels are connected to a solid-state drive (SSD) via an M.2 slot, enabling the high-speed serial computer expansion bus standard. The general-purpose flash memory module and the SSD share the same M.2 slot in a time-sharing manner.
[0013] In one implementation, the central processing unit (CPU) is a small-core platform. Two of the CPU's four independent data transmission channels are connected to a general-purpose flash memory module via an M.2 slot, enabling the general-purpose flash memory protocol. The other two independent data transmission channels are connected to a solid-state drive (SSD) via an M.2 slot, enabling the high-speed serial computer expansion bus standard. The general-purpose flash memory module and the SSD share the same M.2 slot in a time-sharing manner.
[0014] This application discloses a universal flash memory module, comprising a printed circuit board (PCB), a universal flash memory chip, and an M.2 interface. The PCB has a pad array and signal traces. The universal flash memory chip is soldered to a first area of the PCB via the pad array. The M.2 interface is located in a second area of the PCB and is used for pluggable connection to an external device's M.2 slot. The signal traces connect the pad array to the M.2 interface. Integrating the universal flash memory chip onto the PCB and connecting it to an external device's M.2 slot via the M.2 interface on the PCB enables a physical connection between the universal flash memory chip and the external device. This physical connection allows for data transmission between the universal flash memory chip and the external device, achieving a pluggable connection that facilitates replacement and expansion, reduces difficulties in R&D and testing, saves maintenance costs, and provides customers with diverse and flexible storage options.
[0015] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description
[0016] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which: In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
[0017] Figure 1 This paper shows a schematic diagram of the structure of a general-purpose flash memory storage module according to an embodiment of this application; Figure 2 This paper shows a schematic diagram of the structure of another general-purpose flash memory storage module according to an embodiment of this application; Figure 3 This paper shows a pinout diagram of a general-purpose flash memory module according to an embodiment of this application; Figure 4 This illustration shows a schematic diagram of the connection structure between an electronic device and a general-purpose flash memory storage module or solid-state drive according to an embodiment of this application; Figure 5 A pin diagram of an electronic device according to an embodiment of this application is shown.
[0018] Explanation of the labels in the diagram: 1. Printed circuit board; 2. General-purpose flash memory chip; 3. M.2 interface; 4. Power management circuit. Detailed Implementation
[0019] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0020] Figure 1 This paper illustrates a schematic diagram of the structure of a general-purpose flash memory storage module according to an embodiment of this application. Figure 1 As shown, the general-purpose flash memory module includes a printed circuit board (PCB) 1, a general-purpose flash memory chip (UFS chip) 2, and an M.2 interface 3. The PCB 1 is a multi-layer circuit board with a pad array and signal traces. The signal traces include differential pairs and are used to connect the pad array to the M.2 interface 3. The general-purpose flash memory chip 2 uses a ball grid array (BGA) package and integrates NAND flash memory cells and a UFS protocol controller. The UFS chip 2 is soldered to the first area of the PCB 1 via the pad array. This first area refers to the top layer of the PCB 1, and the general-purpose flash memory chip 2 is used to store data. The M.2 interface 3 is located in the second area of the PCB 1, which is the edge area of the PCB 1. The M.2 interface 3, i.e., the gold-plated conductive contact at the edge of the PCB 1, is a key physical structure for the pluggable design. The M.2 interface 3 connects to the M.2 slot of an external device in a pluggable manner, realizing the electrical connection and mechanical fixation between the general-purpose flash memory module and the external device slot. Therefore, the general-purpose flash memory chip 2 is connected to the printed circuit board 1 via a pad array, and signal traces connect the pad array to the M.2 interface 3. The M.2 interface 3 is then connected to an external device in a pluggable manner. Thus, using the printed circuit board as a carrier, the general-purpose flash memory chip 2 and the external device can be connected in a pluggable manner, and data transmission between the general-purpose flash memory chip 2 and the external device can be achieved based on this connection. The external device is an electronic device with an M.2 slot capable of data transmission with the storage device, such as a laptop computer.
[0021] In addition, the printed circuit board 1 is equipped with decoupling capacitors, which are arranged near the power supply pins of the UFS chip 2 for filtering and voltage regulation.
[0022] Specifically, the pad array on the printed circuit board 1 can use a 0.1mm thick stencil. Solder paste is printed on the pad array of the printed circuit board 1, with the solder paste thickness controlled at 0.12mm ± 0.02mm. The UFS chip 2 can be soldered to the pad array of the printed circuit board 1 through solder balls with a 0.5mm pitch. The peak soldering temperature is 245℃ ± 5℃. The UFS chip 2 is precisely placed on the pad array by a pick-and-place machine for reflow soldering. The M.2 interface 3 is fixed to the second area of the printed circuit board 1 by wave soldering.
[0023] Asynchronous verification refers to verifying the compatibility and performance of key components independently of the motherboard design during the product development cycle. Its core requirements are physical pluggability, enabling rapid replacement of different models or versions of components for testing, signal monitoring for easy detection of critical signals, high iteration efficiency, reduced soldering and desoldering time, and accelerated testing cycles. This application achieves pluggability between the UFS chip 2 and external devices by integrating the UFS chip 2 onto the printed circuit board 1 to form a universal flash memory storage module.
[0024] In one embodiment, the physical dimensions of the general-purpose flash memory module are 22 mm wide, and the interface type of the general-purpose flash memory module is M.2.
[0025] This application packages a general-purpose flash memory chip into a general-purpose flash memory module. This module has the same physical form as a solid-state drive (SSD), meaning its physical dimensions are 22 mm wide and its length can be various sizes to meet the M.2 specification, such as 42 mm, 30 mm, or 80 mm. The interface type is M.2, specifically M.2 Key, where M represents the interface key type and indicates the key notch position of the M.2 slot. It has 75 pins. This physical form of the general-purpose flash memory module ensures compatibility with existing M.2 slots in external devices. Furthermore, the interface version of the general-purpose flash memory module is S3, where S indicates a single-sided component layout and 3 is the interface version iteration identifier.
[0026] In one possible implementation, such as Figure 2 As shown, the general-purpose flash memory module includes a power management circuit 4, which includes a main power input circuit and an interface power circuit. The main power input circuit is used to provide operating power to the general-purpose flash memory chip, and the interface power circuit is used to provide interface voltage to the M.2 interface.
[0027] The power management circuit is integrated on the printed circuit board 1 to achieve efficient conversion and distribution of electrical energy. It includes a main power input circuit and an interface power circuit. The main power input circuit receives power from the motherboard and converts it into multiple operating voltages required by the UFS chip 2, providing operating power to the UFS chip 2. For example, it converts the 3.3V voltage input from the motherboard into the 1.8V or 1.2V voltage required by the UFS chip 2. The interface power circuit provides a stable interface voltage to the input and output pins of the M.2 interface 3 to ensure the integrity of data transmission.
[0028] In one possible implementation, the capacity of the general-purpose flash memory storage module is 128 gigabytes or 256 gigabytes.
[0029] Mainstream manufacturers' demand for low-capacity storage modules is concentrated in 128GB and 256GB, covering the basic storage needs of most electronic devices. The cost of 128GB and 256GB UFS chips has reached an inflection point for mass production, with the lowest cost per gigabyte. Higher capacities require multi-chip stacking or advanced processes, leading to increased costs for general-purpose flash memory storage modules. Therefore, considering practicality and cost, the preferred capacity specifications for this general-purpose flash memory storage module are 128GB or 256GB. This achieves an optimal balance between cost, power consumption, and performance while meeting mainstream market demands, effectively addressing the supply gap left by the discontinuation of low-capacity SSDs, and avoiding energy waste caused by over-configuration. The 128GB general-purpose flash memory storage module is approximately $9 cheaper than an SSD of the same capacity. Although the general-purpose flash memory storage module is $0.35 more expensive than the UFS chip BGA packaging method, it saves on after-sales maintenance and R&D research costs. End users can easily replace or expand the storage capacity themselves, and asynchronous verification is supported, accelerating product development cycles.
[0030] It is understandable that the capacity of the general-purpose flash memory storage module in this application is not limited to 128GB and 256GB. Based on market and usage needs, the capacity of the general-purpose flash memory storage module can also be 64GB, 512GB, 1TB, etc.
[0031] In one embodiment, the universal flash memory module further includes a detection circuit for detecting whether the universal flash memory module is correctly inserted into the M.2 slot of an external device, and when the universal flash memory module is correctly inserted into the M.2 slot of the external device, sending a detection signal to the external device, the detection signal being used to instruct the external device to transmit data with the universal flash memory module.
[0032] The detection circuit is mainly used to detect the physical connection status of the general flash memory module and the M.2 slot of the external device in real time after the general flash memory module is physically connected to the external device. When it detects that the general flash memory module is correctly inserted into the M.2 slot of the external device, it sends a detection signal to the external device. This detection signal indicates that the general flash memory module is correctly inserted into the M.2 slot of the external device and data transmission can be carried out. This ensures that data transmission between the general flash memory module and the external device will not occur if the general flash memory module is not fully inserted or the connection is unstable. Figure 3 The following is a pin diagram of a general-purpose flash memory module according to an embodiment of this application, as shown below. Figure 3 As shown, the detection circuit of this application is mainly implemented through a detection pin, which is... Figure 3 Pin 69, shown as the PEDET pin, is designed to be active low. When the general-purpose flash memory module is correctly inserted into the M.2 slot, the PEDET pin is grounded, generating a low-level signal. This low-level signal is sent to an external device, which can then recognize the connection of the general-purpose flash memory module and perform corresponding data transmission with it. When the general-purpose flash memory module is not correctly inserted into the M.2 slot, the PEDET pin remains high, and the external device cannot recognize the connection of the general-purpose flash memory module and does not perform data transmission.
[0033] The detection circuit design enables the general-purpose flash memory module to achieve reliable hot-swapping functionality and connection status detection, providing users with a safe and reliable user experience while ensuring the integrity and reliability of data transmission.
[0034] The second aspect of this application discloses an electronic device, which includes a central processing unit (CPU) and an M.2 slot. The CPU supports the Universal Flash Memory (UFS) protocol and the PCIe protocol, which are two different communication protocols. The M.2 slot is a high-speed internal expansion interface that is electrically connected to the CPU. The universal flash memory module disclosed in the first aspect of this application is inserted into the M.2 slot of the electronic device through its M.2 interface, thereby connecting the universal flash memory module with the electronic device and realizing data transmission between the universal flash memory module and the electronic device.
[0035] The M.2 slot is a key interface in laptops used to connect high-speed storage devices. It is characterized by its small size, high performance, and flexible design. The physical characteristics of the M.2 slot are: a fixed width of 22mm, and the common size of the M.2 interface connected to it is 2242, which means a width of 22mm and a length of 42mm. In one possible implementation, the central processing unit is used to detect a clock signal from the M.2 slot when the device is powered on, and to determine, based on the clock signal, whether the device inserted into the M.2 slot of the electronic device is a general-purpose flash memory or a solid-state drive.
[0036] The electronic device of this application can connect to a general-purpose flash memory module or an SSD via its M.2 slot. However, the general-purpose flash memory module and the SSD use different communication protocols when transmitting data with the electronic device. The general-purpose flash memory module communicates with the electronic device using the UFS protocol, while the SSD communicates using the PCIe protocol. Therefore, it is crucial for the CPU of the electronic device to determine the type of device inserted into the M.2 slot. Since the UFS and PCIe protocols require different base clock frequencies, the type of device inserted into the M.2 slot can be determined based on the clock frequency. After the system powers on, the CPU detects the clock signal from the M.2 slot during startup and determines whether the device inserted into the M.2 slot is a general-purpose flash memory module or a solid-state drive based on the clock signal.
[0037] Furthermore, when the CPU detects a high frequency clock signal, it determines that the device type inserted into the M.2 slot of the electronic device is a solid-state drive (SSD), and the electronic device uses the PCIe protocol to transmit data with the SSD; when the CPU detects a low frequency clock signal, it determines that the device type inserted into the M.2 slot of the electronic device is a general-purpose flash memory module (UFS), and the electronic device uses the UFS protocol to transmit data with the general-purpose flash memory module.
[0038] The UFS protocol is based on the M-PHY specification, requiring a base clock of 19.2MHz, and generates a low-frequency clock signal. The PCIe protocol, based on the PCIe specification, requires a base clock of 100MHz, and generates a high-frequency clock signal. The CPU detects the clock signal from the M.2 slot. When the detected clock signal frequency is 100MHz, it determines that the device type in the M.2 slot of the electronic device is a solid-state drive (SSD), and the electronic device uses the PCIe protocol to transfer data with the SSD. When the detected clock signal frequency is 19.2MHz, it determines that the device type in the M.2 slot of the electronic device is a general-purpose flash memory module (GSM), and uses the UFS protocol to transfer data with the GSM.
[0039] Figure 4 This application illustrates a schematic diagram of the connection structure between an electronic device and a general-purpose flash memory storage module or solid-state drive, as shown in the embodiment of this application. Figure 4As shown, when the CPU is a large-core platform or a Qualcomm platform, the CPU's two high-speed data transmission channels are connected to the general-purpose flash memory module through the M.2 slot, enabling the UFS protocol; two of the CPU's four independent data transmission channels are connected to the solid-state drive through the M.2 slot, enabling the PCIe protocol, and the general-purpose flash memory module and the solid-state drive share the same M.2 slot in a time-sharing manner.
[0040] The CPUs on both the high-performance and Qualcomm platforms natively integrate a 2-lane UFS controller, meaning two high-speed data transfer channels. When an electronic device determines that the device inserted into the M.2 slot is a general-purpose flash memory module, the CPU's two high-speed data transfer channels connect to the general-purpose flash memory module through the M.2 slot, and the CPU uses the UFS protocol to transfer data with the general-purpose flash memory module. In addition, the CPUs on both the high-performance and Qualcomm platforms also include four independent data transfer channels. When an electronic device determines that the device inserted into the M.2 slot is a solid-state drive (SSD), two of the CPU's four independent data transfer channels connect to the SSD through the M.2 slot, and the CPU uses the PCIe protocol to transfer data with the SSD. This allows general-purpose flash memory modules and SSDs to time-share the same M.2 slot. That is, at different times, the electronic device's M.2 slot can be used to transfer data between a general-purpose flash memory module via the UFS protocol and an SSD via the PCIe protocol, without interference between the two modes.
[0041] Figure 5 A pin diagram of an electronic device according to an embodiment of this application is shown.
[0042] like Figure 5 As shown, when the CPU is a small-core platform, two of the four independent data transmission channels of the CPU are connected to the general-purpose flash memory module through the M.2 slot, enabling the UFS protocol. The other two independent data transmission channels are connected to the solid-state drive through the M.2 slot, enabling the PCIe protocol. The general-purpose flash memory module and the solid-state drive share the same M.2 slot in a time-sharing manner.
[0043] CPUs on small-core platforms do not integrate high-speed data transfer channels suitable for general-purpose flash memory modules. Therefore, when the CPU is on a small-core platform and the electronic device determines that the device inserted into the M.2 slot is a general-purpose flash memory module, two of the CPU's four independent data transfer channels connect to the general-purpose flash memory module through the M.2 slot. The CPU then uses the UFS protocol to transfer data with the general-purpose flash memory module. Figure 5In electronic devices, the PCIe 9 and PCIe 10 pins consist of four pairs of differential signal lines. When the electronic device determines that the device inserted into the M.2 slot is a solid-state drive (SSD), the other two of the CPU's four independent data transfer channels connect to the SSD through the M.2 slot. The CPU then enables the PCIe protocol to transfer data with the SSD. Figure 5 The M.2 slot in an electronic device has four pairs of differential signal lines for PCIe 11 and PCIe 12. It's understood that since SSDs transmit data to electronic devices via high-speed data transfer channels, an SSD can connect to any two of the four high-speed data transfer channels (PCIe 9, PCIe 10, PCIe 11, and PCIe 12) to achieve data transfer. Therefore, it's possible to time-share the same M.2 slot between a general-purpose flash memory module and an SSD. That is, at different times, the M.2 slot can be used to transfer data between a general-purpose flash memory module via the UFS protocol and an SSD via the PCIe protocol; the two modes do not interfere with each other.
[0044] By using a single M.2 slot to be compatible with both UFS and PCIe protocols, the general-purpose flash memory module achieves a pluggable design for the UFS chip through the M.2 interface, solving the problem of the non-replaceable BGA package.
[0045] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.
[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.
[0047] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A universal flash memory storage module, characterized in that, The general-purpose flash memory storage module includes: A printed circuit board having a pad array and signal traces thereon, the signal traces being used to connect the pad array to an M.2 interface; A general-purpose flash memory chip, used for storing data, is soldered to a first area of the printed circuit board via the pad array; The M.2 interface is located in the second area of the printed circuit board and is used to connect to the M.2 slot of an external device in a pluggable manner, so as to realize a physical connection between the general-purpose flash memory chip and the external device, and to realize data transmission between the general-purpose flash memory chip and the external device based on the physical connection.
2. The universal flash memory storage module according to claim 1, characterized in that, The general-purpose flash memory module includes a power management circuit, which includes a main power input circuit and an interface power circuit. The main power input circuit is used to provide operating power to the general-purpose flash memory chip, and the interface power circuit is used to provide interface voltage to the M.2 interface.
3. The universal flash memory storage module according to claim 1, characterized in that, The universal flash memory module also includes a detection circuit for detecting whether the universal flash memory module is correctly inserted into the M.2 slot of the external device, and when the universal flash memory module is correctly inserted into the M.2 slot of the external device, sending a detection signal to the external device, the detection signal being used to instruct the external device to transmit data with the universal flash memory module.
4. The universal flash memory storage module according to claim 1, characterized in that, The physical dimensions of the general-purpose flash memory module are 22 mm wide, and the interface type of the general-purpose flash memory module is M.2 interface.
5. The universal flash memory storage module according to claim 1, characterized in that, The capacity of the general-purpose flash memory storage module is 128 gigabytes or 256 gigabytes.
6. An electronic device, characterized in that, The electronic device includes: The central processing unit supports the general-purpose flash memory storage protocol and the high-speed serial computer expansion bus standard; The M.2 slot is electrically connected to the central processing unit; Wherein, the general-purpose flash memory module as described in any one of claims 1-5 is inserted into the M.2 slot of the electronic device via the M.2 interface, thereby connecting the general-purpose flash memory module to the central processing unit.
7. The electronic device according to claim 6, characterized in that, The central processing unit is used to detect the clock signal from the M.2 slot when the device is powered on, and to determine the type of device inserted into the M.2 slot of the electronic device as a general flash memory module or a solid-state drive based on the clock signal.
8. The electronic device according to claim 7, characterized in that, Specifically, when the frequency of the clock signal is detected to be high, the central processing unit determines that the device type inserted into the M.2 slot of the electronic device is a solid-state drive and enables the high-speed serial computer expansion bus standard. When the frequency of the clock signal is detected to be low, the device type inserted into the M.2 slot of the electronic device is determined to be a general flash memory module, and the general flash memory protocol is enabled.
9. The electronic device according to claim 6, characterized in that, The central processing unit is a large-core platform or a Qualcomm platform. The two high-speed data transmission channels of the central processing unit are connected to the general-purpose flash memory module through the M.2 slot, and the general-purpose flash memory storage protocol is enabled. Two of the four independent data transmission channels of the central processing unit are connected to the solid-state drive through the M.2 slot, enabling the high-speed serial computer expansion bus standard; The general-purpose flash memory storage module and the solid-state drive share the same M.2 slot in a time-sharing manner.
10. The electronic device according to claim 6, characterized in that, The central processing unit is a small core platform. Two of the four independent data transmission channels of the central processing unit are connected to the general-purpose flash memory module through the M.2 slot, enabling the general-purpose flash memory storage protocol. The other two independent data transmission channels are connected to the solid-state drive through the M.2 slot, enabling the high-speed serial computer expansion bus standard; The general-purpose flash memory module and the solid-state drive share the same M.2 slot in a time-sharing manner.