A multi-stage filtering-based SVG reactive power compensation circuit

Abstract

The utility model provides a kind of SVG reactive compensation circuit based on multistage filtering, including sampling interface circuit;Difference amplification circuit, connection sampling interface circuit, the voltage state signal of collection is differentially amplified;Current conditioning circuit carries out filtering and limiting amplitude protection processing;Comparison output circuit, generate corresponding drive control signal;DC-DC step-down power management circuit, provide working power supply for each functional module;Communication interface circuit, realize with the differential serial communication of external monitoring system.The utility model is combined by RC filtering on signal path and direct current bus multistage capacitor filtering on power path, forms multistage filtering module, ensures the accuracy of sampling signal and the quality of compensation current, realizes efficient, stable dynamic reactive compensation, improves the power factor of power grid.

Description

Technical Field

[0001] This utility model relates to the technical field of SVG reactive power compensation circuits, specifically an SVG reactive power compensation circuit based on multi-level filtering. Background Technology

[0002] With the acceleration of urbanization and the continuous expansion of power systems, distribution networks are characterized by complex equipment, numerous users, and diverse geographical conditions. Furthermore, they are susceptible to external factors such as user capacity expansion and urban construction, leading to a relatively high probability of faults. Among distribution network faults, the vast majority are single-phase grounding faults, causing an increase in voltage between non-faulty phases and ground, which can easily lead to system overvoltage, insulation breakdown, and potentially escalate into phase-to-phase short circuits. To improve the power factor of the distribution network, reduce energy losses during power transmission, and ensure energy transmission efficiency, reactive power compensation devices are typically installed in the distribution network.

[0003] In industrial settings, a substandard power factor directly leads to increased grid losses, decreased utilization of power supply equipment, and even fines from the power sector. To address this issue, it's necessary to first identify the core causes of the substandard power factor, and then, considering the technical characteristics of the Static Var Generator (SVG), configure a compensation scheme. Substandard power factors in industrial settings are primarily caused by the following three categories of factors: 1. High proportion of inductive loads (the main reason): A large number of inductive electrical equipment are used in industrial production. These devices need to consume reactive power to generate magnetic fields, which is the main source of reactive power. Motor equipment: such as fans, water pumps, compressors, machine tool motors, etc., account for more than 60% of the total industrial electricity consumption.

[0004] 2. Widespread application of nonlinear loads (minor but aggravating impact): With the popularization of power electronics technology, the proportion of nonlinear loads in industrial applications (such as frequency converters, rectifiers, UPS, electric locomotives, etc.) is increasing year by year. These devices not only generate harmonics, but also indirectly lead to an increase in reactive power: Nonlinear loads convert AC to DC through the "rectification-filtering" stage, and their current waveform is non-sinusoidal (containing a large number of harmonic components), which will lead to an increase in the phase difference between the grid voltage and the current, and an increase in the equivalent reactive power.

[0005] 3. Inappropriate configuration of compensation equipment (human / design factors): If the enterprise has configured reactive power compensation equipment, but the power factor still does not meet the standards, for example, if the fixed capacity compensation is only designed according to the maximum load, overcompensation will occur under light load. Delayed compensation method: Using the traditional "contactor switching capacitor" method leads to compensation failure.

[0006] Based on this, to solve the above problems, this utility model proposes a novel reactive power compensation circuit that can not only achieve stable support for DC bus voltage and real-time acquisition of voltage status signals, but also perform non-contact sampling of grid current and isolated control of power circuits. Simultaneously, it also possesses excellent filtering performance, effectively suppressing high-frequency interference and noise, and improving the power factor of the power grid. Utility Model Content

[0007] In view of the shortcomings of the existing technology, the purpose of this utility model is to provide an SVG reactive power compensation circuit based on multi-level filtering to solve the problems mentioned in the background technology.

[0008] To achieve the above objectives, this utility model employs the following technical solution: an SVG reactive power compensation circuit based on multi-stage filtering, comprising a sampling interface circuit that provides a stable DC bus voltage through multiple sets of parallel capacitor networks and collects voltage status signals of key DC-side nodes in real time; a differential amplifier circuit connected to the sampling interface circuit that differentially amplifies the collected voltage status signals and performs first-stage filtering through a built-in RC filter network; a current conditioning circuit that collects grid current signals through a current transformer, converts the current signals into voltage signals, and performs filtering and amplitude limiting protection processing; a comparison output circuit connected to the differential amplifier circuit and the current conditioning circuit that compares the processed signal with a set threshold to generate a corresponding drive control signal; a DC-DC step-down power management circuit that converts high DC voltage into a stable and low-voltage DC power supply to provide operating power for each functional module circuit; a communication interface circuit that enables differential serial communication with an external monitoring system to upload operating status data and receive control commands; a real-time clock circuit that provides a clock signal; and a power control circuit connected to the comparison output circuit that drives power switching devices through optocoupler isolation to achieve isolated control and power distribution of the power circuit.

[0009] Compared with the prior art, the beneficial effects of this utility model are as follows: This invention combines RC filtering on the signal path with multi-stage capacitor filtering on the DC bus in the power path to form a multi-stage filtering module, ensuring the accuracy of the sampled signal and the quality of the compensation current, achieving efficient and stable dynamic reactive power compensation, and improving the power factor of the power grid. Attached Figure Description

[0010] The disclosure of this utility model is illustrated with reference to the accompanying drawings. It should be understood that the drawings are for illustrative purposes only and are not intended to limit the scope of protection of this utility model. In the drawings, the same reference numerals are used to refer to the same parts. Wherein: Figure 1This is a schematic diagram of the overall structure of the SVG reactive power compensation circuit based on multi-level filtering proposed in one embodiment of the present invention. Figure 2 This is a schematic diagram of the sampling interface circuit structure proposed in one embodiment of the present invention; Figure 3 This is a schematic diagram of the differential amplifier circuit structure proposed in one embodiment of the present invention; Figure 4 This is a schematic diagram of the current conditioning circuit structure proposed in one embodiment of the present invention; Figure 5 This is a schematic diagram of the DC-DC buck power management circuit structure proposed in one embodiment of the present invention; Figure 6 This is a schematic diagram of the communication interface circuit structure proposed in one embodiment of the present invention; Figure 7 This is a schematic diagram of the real-time clock circuit structure proposed in one embodiment of the present invention; Figure 8 This is a schematic diagram of the power control circuit structure proposed in one embodiment of the present invention; Figure 9 This is a schematic diagram of the comparison output circuit structure proposed in one embodiment of the present invention. Detailed Implementation

[0011] It is readily understood that, based on the technical solution of this utility model, those skilled in the art can propose various interchangeable structural methods and implementations without altering the essential spirit of this utility model. Therefore, the following detailed embodiments and accompanying drawings are merely illustrative descriptions of the technical solution of this utility model and should not be considered as the entirety of this utility model or as limitations or restrictions on the technical solution of this utility model.

[0012] As one embodiment of this utility model, the present utility model provides a technical solution: an SVG reactive power compensation circuit based on multi-stage filtering, such as... Figure 1 - Figure 9 As shown, it includes: The sampling interface circuit is configured to provide a stable DC bus voltage through a network of multiple parallel capacitors and to acquire the voltage status signals of key DC-side nodes in real time. The differential amplifier circuit, connected to the sampling interface circuit, is configured to differentially amplify the acquired voltage state signal and implement the first-stage filtering through the built-in RC filter network. The current conditioning circuit is configured to acquire the grid current signal through a current transformer, convert the current signal into a voltage signal, and perform filtering and amplitude limiting protection. The comparison output circuit is connected to the differential amplifier circuit and the current conditioning circuit. It is configured to compare the processed signal with a set threshold and generate a corresponding drive control signal. The DC-DC step-down power management circuit is configured to convert the input high DC voltage into a stable low DC power supply to provide operating power for the various functional module circuits in the system. The communication interface circuit is configured to enable differential serial communication with an external monitoring system, and to upload operating status data and receive control commands. A real-time clock circuit, configured to provide a time reference for system control by supplying a real-time clock signal; The power control circuit, connected to the comparator output circuit, is configured to drive power switching devices through optocoupler isolation to achieve isolated control and power distribution of the power circuit.

[0013] In one embodiment of this utility model, such as Figure 2 As shown, the sampling interface circuit contains multiple sets of parallel capacitor networks that constitute the second-stage DC bus filter of the system. Specifically, it includes parallel capacitor groups C12 and C55, parallel capacitor groups C21, C22 and C54, and high-frequency decoupling capacitor C23.

[0014] In specific implementation, capacitors C21, C22, and C54 are connected in parallel, with one end connected to the REFCAP pin of U1B and the other end connected to the GND pin, forming a set of parallel filter capacitors; capacitors C12 and C55 are connected in parallel, with one end connected between the GND pin and the AVDD pin of U1B, forming another set of parallel capacitors; high-frequency decoupling capacitor C23 is connected between the system GND and the REFIO pin of U1B. The chip U1B, through its REFIO, REFGND, REFCAP, AGND, and AVDD pins, supports and performs secondary filtering of the DC bus voltage on the one hand, and collects the status signals of key nodes on the DC side on the other hand, thereby realizing the monitoring and control of the DC bus voltage.

[0015] Based on the above technical concept, it can be understood that the main filter capacitor group composed of C21, C22, and C54 connected in parallel, and the auxiliary capacitor group composed of C12 and C55 connected in parallel, together provide a low-impedance path for the DC bus, realizing energy storage and low-to-medium frequency ripple suppression for the bus voltage. Simultaneously, the high-frequency decoupling capacitor C23 is used to filter out high-frequency switching noise. Thus, the control chip U1B samples the voltage of these capacitor nodes in real time through its REFIO and REFCAP pins, converting the energy state and ripple information of the DC bus into electrical signals, thereby simultaneously completing voltage support and multi-point sampling.

[0016] In one embodiment of this utility model, such as Figure 3As shown, a differential amplifier circuit is used to achieve high-precision extraction and amplification of weak differential signals. When it is necessary to monitor the voltage across a sampling resistor (such as 1 milliohm) connected in series in the main circuit, the generated original differential signal may only be at the millivolt level, and is superimposed on a common-mode voltage of several hundred volts and mixed with high-frequency switching noise.

[0017] In practice, the differential amplifier circuit includes operational amplifiers U51A and U51B, input resistor networks R401, R402, R403 and R470, R471, R472, ring feedback resistor networks R404, R405, R406, input protection circuits D21, D22, and RC filter networks R361, C361, R362, C362.

[0018] The non-inverting input U1+ and inverting input U1- of the operational amplifier are connected to the differential signal inputs UA and / or UN through a resistor network consisting of multiple resistors, which is used to acquire and amplify the differential signal.

[0019] Furthermore, the constructed resistor network includes: resistors R401, R402, and R403 connected in series at the positive input terminal UA of the differential signal, and resistors R470, R471, and R472 connected in series, used to jointly set the input impedance and common-mode rejection ratio of the circuit; a series loop feedback resistor network composed of resistors R404, R405, and R406, which is connected across the output terminal of UA and the two input terminals to stabilize the closed-loop gain of the circuit; wherein, bidirectional clamping diodes D21 and D22 are connected in parallel on the differential signal input path of the differential amplifier circuit to achieve overvoltage protection; at the same time, the constructed resistor network also includes two RC low-pass filter circuits composed of resistor R361 and capacitor C361 and resistor R362 and capacitor C362 respectively, which are directly connected in parallel between the differential input terminal and ground GND, thus forming the first stage of filtering before the signal enters the operational amplifier, effectively suppressing high-frequency interference.

[0020] The principle is as follows: high-frequency noise is filtered out by an input RC filter composed of R361, C361 and R362, C362; then, a precision resistor network composed of R401, R402, R403 and R470, R471, R472 guides the signal to the input of operational amplifier U1A; finally, a ring feedback resistor network formed by R404, R405, R406 sets and stabilizes the amplification factor (e.g., 100 times), amplifying the weak millivolt differential signal into a volt-level single-ended output, while greatly suppressing common-mode interference, thus providing a clean, amplified, and accurate signal for subsequent circuits.

[0021] In one embodiment of this utility model, such as Figure 4As shown, the current conditioning circuit includes a current transformer CT1, parallel sampling resistors R21 and R22, parallel filter capacitors C100 and C101, and bidirectional limiting protection diodes D31 and D32, which are used to realize non-contact sampling and signal conditioning of the main circuit current.

[0022] In practice, the primary side pins 1In+ and 2In- of the current transformer CT1 are connected in series to the main circuit to sample the current, and the secondary side outputs corresponding differential current signals IA+ and IA-. On the secondary side, sampling resistors R21 and R22 are connected in parallel between IA+ and IA-, converting the current signal output by CT1 into a differential voltage signal. Filter capacitors C100 and C101 are also connected in parallel between IA+ and IA-, forming a differential low-pass filter together with the parallel resistors to suppress high-frequency noise. To prevent overvoltage surges, two diodes D31 and D32 are connected in reverse parallel between the IA+ and IA- signal lines, forming a bidirectional clamping protection circuit to limit the differential voltage within a safe range. Finally, the conditioned clean differential signals (IA+ and IA-) are output to the subsequent processing circuit.

[0023] In one embodiment of this utility model, such as Figure 5 As shown, the DC-DC step-down power management circuit includes a DC-DC power chip U21, input filter capacitors C4 and C51, enable resistor R90, feedback resistors R70 and R20, freewheeling diode D8, bootstrap capacitor C71, and output filter capacitor group C81, C200, C01, C02, and C03, to achieve efficient DC voltage conversion and regulation.

[0024] In practice, input filter capacitors C4 and C51 are connected in parallel between the input voltage VIN and GND; one end of enable resistor R90 is connected to VIN, and the other end is connected to the EN pin of chip U21; one end of feedback resistor R70 is connected to the output voltage VOUT, and the other end, together with resistor R20, is connected to the FB pin of U21, and the other end of resistor R20 is connected to GND; the anode of freewheeling diode D8 is connected to GND, and the cathode is connected to the SW pin of U21; one end of bootstrap capacitor C71 is connected to the BOOT pin of U21, and the other end is connected to the SW pin; the output filter capacitor group C81, C200, C01, C02, and C03 are connected in parallel between the output terminal VOUT and GND.

[0025] Understandably, the input voltage VIN first undergoes high-frequency noise filtering through parallel input filter capacitors C4 and C51. The chip's enable pin (EN) is connected to VIN via resistor R90 for pull-up startup. Simultaneously, its feedback pin (FB) is connected to the output terminal VOUT via a voltage divider network composed of resistors R70 and R20 to set the output voltage. The switch pin (SW) acts as a power node, connected to the output through a power inductor L1. The freewheeling diode D8 is connected between the SW pin and ground (GND) to provide a freewheeling path for the inductor current. The bootstrap capacitor C71 is connected between the BOOT pin and the SW pin to drive the internal high-side MOSFET. Finally, the output voltage is smoothed and filtered by a parallel output filter capacitor group (C81, C200, C01, C02, and C03), thus providing a stable and clean DC power supply for the subsequent load.

[0026] In one embodiment of this utility model, such as Figure 6 As shown, the communication interface circuit includes chip U64, bus bias resistors R07 and R08, termination matching resistors R88 and R87, decoupling capacitor C234, and transient voltage suppression protection TVS diodes D54 (SMAJ12CA), D67, and D68; ensuring communication reliability and anti-interference capability.

[0027] In practical implementation, the differential output buses A and B of chip U64 are connected to networks Screen_B and Screen_A respectively through bias resistors R07 and R08 to establish a stable idle level; terminating matching resistors R88 and R87 are connected across lines A and B respectively to suppress signal reflection; on the bus side, transient voltage suppression protection is employed: TVS diode D54 is connected across lines A and B to provide differential mode protection; simultaneously, TVS diodes D67 and D68 are connected in parallel between line A and ground (GND485) and line B and ground respectively to provide common mode protection. The power supply pin VDD5 of chip U64 is connected to GND485 through decoupling capacitor C234 to ensure power supply stability.

[0028] In one embodiment of this utility model, such as Figure 7 As shown, the proposed real-time clock circuit is used to maintain continuous clock operation when the main power supply is disconnected.

[0029] In one embodiment of this utility model, such as Figure 8 As shown, the power control circuit includes an optocoupler UK1, a switching transistor Qk, gate drive resistors Rk1, Rk2, Rk3, Rk4, filter capacitors Ck1, Ck2, Ck3, C001, and a power inductor L6, to achieve safe isolation drive and power management of the power circuit.

[0030] In practical implementation, the input terminal of optocoupler UK1 is connected to the control signal through a current-limiting network composed of resistors Rk1 and Rk2, and its output terminal drives the gate of the switching transistor Qk; the gate drive resistor Rk3 is connected in series between the output terminal of UK1 and the gate of Qk to suppress oscillation, and the resistor Rk4 is connected between the gate of Qk and the source (ground) to ensure reliable turn-off; the filter capacitors Ck1 and Ck2 are connected in parallel between the power supply and ground on the output side of the optocoupler for decoupling, and the capacitor Ck3 and the resistor Rk4 are connected in parallel to form a gate RC discharge circuit; the power inductor L6 is connected between the drain of the switching transistor Qk and the output terminal, and through the series filter capacitor C001, the filtering of the power path and energy distribution management are realized.

[0031] Based on the above technical concept, it can be understood that this circuit uses the optocoupler UK1 (model TLP127) as the core to achieve electrical isolation of the control signal. The input terminals (pins 1 and 2) of the optocoupler UK1 are connected to the control signal (RelayCtrl) through a current-limiting network composed of resistors RK1 and RK2, and the input power supply (24V3) is filtered by capacitors CK1 and CK2. The output terminals (pins 4 and 3) of UK1 directly drive the gate of the switching transistor Qk. Resistor RK3 is connected in series in the drive circuit to suppress gate oscillation, while resistor RK4 is connected in parallel between the gate and source (ground) of Qk to form an RC pull-down circuit to ensure its reliable turn-off. Finally, the controlled power path is filtered at the output through power inductor L6 and filter capacitor C001, thereby realizing the isolation control and distribution management of the entire power path.

[0032] In one embodiment of this utility model, such as Figure 9 As shown, the comparator output circuit includes chip U59B as the core comparator. Its non-inverting input is connected to the input signal Vin through resistor R340, and grounded through resistor R359 to set the bias; the inverting input is connected to the reference voltage through resistor R349; a negative feedback network consisting of resistors R360 and R339 connected in series is connected between the inputs of U59B to set the hysteresis threshold of the circuit and prevent output oscillation; and at the output of chip U59B, capacitor C250 is connected between the output pin of U59B and GND to filter out high-frequency noise and stabilize the output signal.

[0033] Furthermore, the comparator output circuit is powered by an 8.5V supply and shares a common GND reference ground. This configuration enables the comparison of the input voltage and the stable drive output.

[0034] In the embodiments of this utility model, the working principle of the SVG reactive power compensation circuit based on multi-stage filtering is as follows: S1. Based on the differential amplifier circuit and the current conditioning circuit, the mains voltage and current signals are collected respectively. It can be understood that the internal circuit of this module contains an RC filter network to perform the first stage of filtering on the original signal, effectively suppressing high-frequency noise. S2. The processed clean signal is sent to the main control chip, which is powered by a DC-DC step-down power management circuit. Based on the time information provided by the system main control chip and the real-time clock circuit, the reactive power detection and compensation algorithm is run to generate control commands. S3. The control command forms a drive signal through the comparison output circuit, which in turn controls the power switch in the power control circuit. It can be understood that the action of this power switch determines how the energy in the sampling interface circuit is injected into the grid through the inverter bridge to compensate for reactive current. It should be noted that in this implementation, the DC sampling circuit itself is a powerful multi-stage filtering network: its multiple sets of parallel capacitors, including C12 / C55, C21 / C22 / C54, constitute a second-stage (medium frequency / low frequency) filter for the DC bus voltage, thereby ensuring the voltage quality of the compensation current source. S4. The data is uploaded to an external monitoring system via a communication interface circuit so that operators can monitor and intervene in real time.

[0035] Thus, this utility model combines RC filtering on the signal path with multi-stage capacitor filtering on the DC bus in the power path to form a multi-stage filtering module, ensuring the accuracy of the sampled signal and the quality of the compensation current, thereby achieving efficient and stable dynamic reactive power compensation.

[0036] The technical scope of this utility model is not limited to the content described above. Those skilled in the art can make various modifications and variations to the above embodiments without departing from the technical concept of this utility model, and all such modifications and variations should fall within the protection scope of this utility model.

Claims

1. An SVG reactive power compensation circuit based on multi-stage filtering, characterized in that: include: The sampling interface circuit provides a stable DC bus voltage through multiple sets of parallel capacitor networks and collects the voltage status signals of key nodes on the DC side in real time; the differential amplifier circuit is connected to the sampling interface circuit, performs differential amplification on the collected voltage status signals, and implements first-stage filtering through a built-in RC filter network; the current conditioning circuit collects the grid current signal through a current transformer, converts the current signal into a voltage signal, and performs filtering and amplitude limiting protection processing. The comparison output circuit is connected to the differential amplifier circuit and the current conditioning circuit. It compares the processed signal with a set threshold to generate a corresponding drive control signal. The DC-DC step-down power management circuit converts high DC voltage into a stable low-voltage DC power supply to provide operating power for various functional module circuits; the communication interface circuit enables differential serial communication with an external monitoring system, completing the uploading of operating status data and the reception of control commands; the real-time clock circuit provides a clock signal; and the power control circuit, connected to the comparison output circuit, drives the power switching device through optocoupler isolation to achieve isolated control and power distribution of the power circuit.

2. The SVG reactive power compensation circuit based on multi-stage filtering according to claim 1, characterized in that: In the sampling interface circuit, the multiple sets of parallel capacitor networks constitute the second-stage DC bus filter, including: capacitors C21, C22, and C54, which are connected in parallel, with one end connected to the REFCAP pin of U1B and the other end connected to the GND pin, forming a set of parallel filter capacitors; capacitors C12 and C55, which are connected in parallel, with one end connected between the GND pin and the AVDD pin of U1B, forming another set of parallel capacitors; and high-frequency decoupling capacitor C23, which is connected between the system GND and the REFIO pin of U1B.

3. The SVG reactive power compensation circuit based on multi-stage filtering according to claim 1, characterized in that: The differential amplifier circuit includes an operational amplifier. The non-inverting input terminal U1+ and the inverting input terminal U1- of the operational amplifier are connected to the differential signal input terminals UA and / or UN through a resistor network consisting of multiple resistors, for the purpose of acquiring and amplifying the differential signal.

4. The SVG reactive power compensation circuit based on multi-stage filtering according to claim 3, characterized in that: The resistor network comprises: resistors R401, R402, and R403 connected in series at the positive input terminal UA of the differential signal, and resistors R470, R471, and R472 connected in series; a series ring feedback resistor network consisting of resistors R404, R405, and R406, which is connected across the output terminal of UA and the two input terminals; wherein, bidirectional clamping diodes D21 and D22 are connected in parallel on the differential signal input path of the differential amplifier circuit; Meanwhile, the resistor network also includes two RC low-pass filter circuits, each consisting of resistor R361 and capacitor C361, and resistor R362 and capacitor C362, which are directly connected in parallel between the differential input terminal and ground GND.

5. The SVG reactive power compensation circuit based on multi-stage filtering according to claim 1, characterized in that: The current conditioning circuit includes a current transformer CT1, parallel sampling resistors R21 and R22, parallel filter capacitors C100 and C101, and bidirectional limiting protection diodes D31 and D32, which are used to realize non-contact sampling and signal conditioning of the main circuit current. Specifically, the primary side pins 1In+ and 2In- of the current transformer CT1 are connected in series to the main circuit to sample the current, and the secondary side outputs corresponding differential current signals IA+ and IA-; the sampling resistors R21 and R22 are connected in parallel between IA+ and IA-; the filter capacitors C100 and C101 are also connected in parallel between IA+ and IA-; and the two diodes D31 and D32 are connected in reverse parallel between the IA+ and IA- signal lines.

6. The SVG reactive power compensation circuit based on multi-stage filtering according to claim 1, characterized in that: The DC-DC step-down power management circuit includes chip U21, input filter capacitors C4 and C51, enable resistor R90, feedback resistors R70 and R20, freewheeling diode D8, bootstrap capacitor C71, and output filter capacitor bank. Specifically, the input filter capacitors C4 and C51 are connected in parallel between the input voltage VIN and GND; one end of the enable resistor R90 is connected to VIN, and the other end is connected to the EN pin of chip U21; one end of the feedback resistor R70 is connected to the output voltage VOUT, and the other end, together with resistor R20, is connected to the FB pin of U21, with the other end of resistor R20 connected to GND; the anode of the freewheeling diode D8 is connected to GND, and the cathode is connected to the SW pin of U21; one end of the bootstrap capacitor C71 is connected to the BOOT pin of U21, and the other end is connected to the SW pin; the output filter capacitor group is connected in parallel between the output terminal VOUT and GND.

7. The SVG reactive power compensation circuit based on multi-stage filtering according to claim 1, characterized in that: The communication interface circuit includes chip U64, bus bias resistors R07 and R08, termination matching resistors R88 and R87, decoupling capacitor C234, and TVS diodes D54, D67, and D68. In this configuration, the differential output buses A and B of chip U64 are connected to networks Screen_B and Screen_A respectively via bias resistors R07 and R08 to establish a stable idle level; the terminating matching resistors R88 and R87 are connected across lines A and B respectively to suppress signal reflection; TVS diode D54 is connected across lines A and B to provide differential mode protection; simultaneously, TVS diodes D67 and D68 are connected in parallel between lines A and B and ground respectively; the power supply pin VDD5 of chip U64 is connected to GND485 via decoupling capacitor C234 to ensure power supply stability.

8. The SVG reactive power compensation circuit based on multi-stage filtering according to claim 1, characterized in that: The power control circuit includes an optocoupler UK1, a switching transistor Qk, gate drive resistors Rk1, Rk2, Rk3, Rk4, filter capacitors Ck1, Ck2, Ck3, C001, and a power inductor L6. The input terminal of the optocoupler UK1 is connected to the control signal through a current-limiting network composed of resistors Rk1 and Rk2, and its output terminal drives the gate of the switching transistor Qk. The gate driving resistor Rk3 is connected in series between the output terminal of UK1 and the gate of Qk to suppress oscillation, and resistor Rk4 is connected between the gate and source of Qk. Filter capacitors Ck1 and Ck2 are connected in parallel between the power supply and ground on the output side of the optocoupler. The power inductor L6 is connected between the drain and the output terminal of the switching transistor Qk, and through the series connection of the filter capacitor C001, it realizes the filtering of the power path and energy distribution management.

9. The SVG reactive power compensation circuit based on multi-stage filtering according to claim 1, characterized in that: The comparison output circuit includes a chip U59B, whose non-inverting input terminal is connected to the input signal Vin through a resistor R340 and grounded through a resistor R359 to set the bias; the inverting input terminal is connected to the reference voltage through a resistor R349. A negative feedback network consisting of resistors R360 and R339 connected in series is connected between the input terminals of U59B to set the hysteresis threshold of the circuit and prevent output oscillation. At the output terminal of chip U59B, capacitor C250 is connected between the output pin of U59B and GND to filter out high-frequency noise and stabilize the output signal.

10. The SVG reactive power compensation circuit based on multi-stage filtering according to claim 1, characterized in that: The comparison output circuit is powered by an 8.5V power supply and shares the GND reference ground.

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