A self-discharge circuit and electronic device

Abstract

The utility model relates to electronic circuit technology discloses a self -discharging circuit and electronic equipment, include: power supply end, PMOS pipe, PNP pipe, NPN pipe, first resistance, second resistance, third resistance, fourth resistance, fifth resistance and load unit, wherein, the source electrode of PMOS pipe, the base of PNP pipe of power supply end electricity connects respectively, power supply end still connects ground in proper order through fifth resistance, third resistance, and third resistance still connects between the base and the emitter of NPN pipe, the collector of NPN pipe electricity connects the gate of PMOS pipe, and first resistance connects between the gate and the drain of PMOS pipe, and the drain of PMOS pipe still electricity connects the emitter of PNP pipe, the emitter of PNP pipe still electricity connects load unit, and the collector of PNP pipe still connects ground through second resistance, and the base of PNP pipe still connects ground through fourth resistance, the utility model aims at providing a low voltage drop, low -power consumption's fast self -discharging circuit.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit technology, and in particular to a self-discharge circuit and electronic device. Background Technology

[0002] In electronic circuit systems, the electrical energy provided by energy storage components (such as capacitors and batteries) sometimes needs to be released rapidly to ensure the safe and stable operation of the system or to meet specific operational requirements. For example, when batteries are plugged in or removed, electronic devices are shut down, or malfunctions occur, residual electrical energy may damage other components of the equipment or affect subsequent maintenance operations, thus requiring rapid discharge.

[0003] Currently, some self-discharge circuits use a simple single-resistor discharge method. Although the structure is simple, the discharge speed is difficult to control precisely, and heat is easily generated during the discharge process, causing thermal interference to surrounding electronic components and affecting their performance and lifespan.

[0004] Some self-discharge circuits employ a diode-transistor discharge scheme, which also presents the following significant problems: Diodes exhibit a certain voltage differential, typically between 0.3V and 0.7V. For some low-power products (such as electronic products powered by dry cell batteries), extremely low voltages are often required to maintain normal operation. In this situation, the internal resistance of the power supply module is relatively high, and the voltage drop also increases accordingly. The voltage drop of the diode further exacerbates this problem, leading to a severe deterioration in the product's load-carrying capacity, affecting the normal performance of the equipment, and failing to meet the needs of actual use.

[0005] The above content is only used to help understand the technical solution of this utility model and does not represent an admission that the above content is prior art. Utility Model Content

[0006] This invention proposes a self-discharge circuit and electronic device, aiming to provide a fast self-discharge circuit with low voltage drop and low power consumption.

[0007] To achieve the above objectives, this utility model proposes a self-discharge circuit, comprising: a power supply terminal, a PMOS transistor, a PNP transistor, an NPN transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a load unit; wherein, the power supply terminal is electrically connected to the source of the PMOS transistor and the base of the PNP transistor respectively, and the power supply terminal is also grounded in sequence through the fifth resistor and the third resistor, and the third resistor is also connected between the base and emitter of the NPN transistor; The collector of the NPN transistor is electrically connected to the gate of the PMOS transistor. The first resistor is connected between the gate and drain of the PMOS transistor. The drain of the PMOS transistor is also electrically connected to the emitter of the PNP transistor. The emitter of the PNP transistor is also electrically connected to the load unit, the collector of the PNP transistor is grounded through a second resistor, and the base of the PNP transistor is grounded through a fourth resistor.

[0008] Optionally, the load unit includes a load capacitor and a load resistor connected in parallel to ground.

[0009] Optionally, the first resistor is an adjustable resistor.

[0010] Optionally, the second resistor is an adjustable resistor.

[0011] This invention further proposes an electronic device, including the self-discharge circuit described above.

[0012] Optionally, the electronic device further includes a power supply module, which is electrically connected to the power supply terminal of the self-discharge circuit.

[0013] Optionally, the power supply module includes a battery compartment for pluggable batteries.

[0014] Optionally, the pluggable battery is a dry cell battery.

[0015] The beneficial effects of this utility model's technical solution are as follows: A PMOS transistor is used for unidirectional conduction and unidirectional cutoff, and a PNP transistor acts as a fast discharge switch when the power supply is turned off, allowing the load unit to discharge rapidly through the relevant resistor; simultaneously, an NPN transistor turns off the PMOS transistor when the power supply is turned off, preventing current backflow. This achieves both the requirement for rapid discharge and an ultra-low power consumption design, while also ensuring zero voltage drop in the power supply path (the voltage drop is negligible when using a PMOS transistor with low on-resistance, equivalent to zero voltage drop). Attached Figure Description

[0016] Figure 1 This is a schematic diagram of an embodiment of the self-discharge circuit of this utility model.

[0017] Explanation of reference numerals in the attached figures: R5: Fifth resistor RL: Load resistance CL: Load capacitance Q1: PMOS transistor Q2: PNP pipe Q3: NPN transistor Vin: Power supply end VL: Load terminal voltage GND: Ground wire The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0018] The solutions in the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this utility model.

[0019] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this utility model are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0020] It should also be noted that when a component is described as "fixed to" or "set on" another component, it can be directly on the other component or there may be an intervening component present. When a component is described as "connected to" another component, it can be directly connected to the other component or there may be an intervening component present.

[0021] Furthermore, descriptions involving terms such as "first" and "second" in this utility model are for descriptive purposes only (e.g., to distinguish identical or similar elements) and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include at least one of those features. Additionally, technical solutions from different embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If a combination of technical solutions is contradictory or impossible to implement, such a combination should be considered nonexistent and not within the scope of protection claimed by this utility model.

[0022] This utility model proposes a self-discharge circuit, referring to... Figure 1 The self-discharge circuit includes: a power supply terminal Vin, a PMOS transistor Q1, a PNP transistor Q2, an NPN transistor Q3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a load unit; wherein, the power supply terminal Vin is electrically connected to the source of the PMOS transistor Q1 and the base of the PNP transistor Q2, and the power supply terminal Vin is also grounded in sequence through the fifth resistor R5 and the third resistor R3, and the third resistor R3 is also connected between the base and the emitter of the NPN transistor Q3; The collector of NPN transistor Q3 is electrically connected to the gate of PMOS transistor Q1. The first resistor R1 is connected between the gate and drain of PMOS transistor Q1. The drain of PMOS transistor Q1 is also electrically connected to the emitter of PNP transistor Q2. The emitter of PNP transistor Q2 is also electrically connected to the load unit, the collector of PNP transistor Q2 is also grounded through the second resistor R2, and the base of PNP transistor Q2 is also grounded through the fourth resistor R4.

[0023] In this embodiment, the power supply terminal Vin is the power input section of the entire circuit, providing electrical energy to the circuit. It includes the following connection points: (1) Directly electrically connected to the source of PMOS transistor Q1.

[0024] (2) Connect to the base of PNP transistor Q2 (i.e., PNP triode) to provide a bias voltage to the base of PNP transistor Q2.

[0025] (3) After passing through the fifth resistor R5 and the third resistor R3 in sequence, it is grounded (i.e., connected to the wire GND).

[0026] In this circuit, the base of an NPN transistor Q3 is connected between the fifth resistor R5 and the third resistor R3. Simultaneously, the third resistor R3 is also connected between the base and emitter of the NPN transistor Q3, providing a bias voltage to the base. This connection forms a voltage divider circuit used to control the operating state of the NPN transistor Q3. Therefore, the values ​​of the fifth resistor R5 and the third resistor R3 only need to be set according to the specifications of the selected NPN transistor Q3 model and the normal power supply voltage at the Vin terminal, so that the fifth resistor R5 and the third resistor R3 can control the NPN transistor Q3 to turn on or off depending on whether Vin is powered on or off.

[0027] Meanwhile, the collector of NPN transistor Q3 is electrically connected to the gate of PMOS transistor Q1. The on / off state of NPN transistor Q3 affects the gate voltage of PMOS transistor Q1, thereby controlling the on / off state of PMOS transistor Q1. When NPN transistor Q3 is on, it pulls down the gate voltage of PMOS transistor Q1, causing PMOS transistor Q1 to conduct; when NPN transistor Q3 is off, PMOS transistor Q1 is also turned off accordingly.

[0028] The third resistor R3, the fifth resistor R5, and the NPN transistor Q3 form the control unit of the PMOS transistor Q1. When there is a voltage input at the power supply terminal Vin, the NPN transistor Q3 will naturally turn on, and the PMOS transistor Q1 will turn on accordingly. When there is no voltage input at the power supply terminal Vin, the NPN transistor Q3 will naturally turn off, and the PMOS transistor Q1 will turn off accordingly.

[0029] The first resistor R1 is connected between the gate and drain of the PMOS transistor Q1. R1 allows adjustment of the low-power current. When the circuit is in different operating states, R1 affects the current distribution, thus adjusting the low-power current. When Q1 is in the off state, R1 limits the leakage current from the gate to the drain; when Q1 is in the on state, it also affects the current in the circuit, allowing the circuit to minimize power consumption while meeting functional requirements.

[0030] Because in low-power mode, the current in the circuit needs to be as small as possible. The presence of the first resistor R1 increases the equivalent resistance of the circuit, which reduces the current to some extent, thereby reducing power consumption. By properly selecting the value of the first resistor R1, the power consumption performance of the circuit can be optimized, enabling the circuit to operate with low power in different operating scenarios.

[0031] The drain of PMOS transistor Q1 is electrically connected to the load cell. When PMOS transistor Q1 is turned on, the power supply terminal Vin provides power to the load cell. At this time, the input voltage equals the load terminal voltage VL, and there is no voltage drop in the circuit. Therefore, the design specifications of the relevant load devices in the load cell only need to ensure that the load terminal voltage VL is equal to the input voltage when the power supply terminal Vin can provide the corresponding input voltage through PMOS transistor Q1.

[0032] Since the power supply terminal Vin is also connected to the base of the PNP transistor Q2, and the base of the PNP transistor Q2 is grounded through the fourth resistor R4, the fourth resistor R4 also serves as a voltage divider and current limiter, providing a suitable bias voltage to the base of the PNP transistor Q2 to ensure that the PNP transistor Q2 can operate normally. (That is, the value of the fourth resistor R4 only needs to be set according to the specifications of the selected PNP transistor Q2 model and the normal power supply voltage of the power supply terminal Vin, so that the fourth resistor R4 can control the PNP transistor Q2 to conduct or cut off when the power supply terminal Vin is not powered.) In addition, the collector of the PNP transistor Q2 is also grounded through the second resistor R2.

[0033] Thus, when there is voltage input at the power supply terminal Vin, the PNP transistor Q2 will naturally be cut off, and the circuit will not discharge. When there is no voltage input at the power supply terminal Vin, the NPN transistor Q3 will naturally be turned on, and the load unit can then discharge quickly through the second resistor R2. Furthermore, the smaller the resistance value of the second resistor R2, the faster the load unit discharges.

[0034] In addition, the power supply terminal Vin is also used to connect to the power supply module of related electronic devices. While obtaining power input, it can provide load protection for related components of electronic devices through the load unit.

[0035] The self-discharge circuit works as follows: When there is voltage input at the power supply terminal Vin, NPN transistor Q3 is turned on, PNP transistor Q2 is turned off, and PMOS transistor Q1 is turned on. The load unit stores energy and makes the load terminal voltage VL equal to the power supply terminal Vin voltage, and provides load protection for the relevant device modules of the electronic equipment connected to the power supply terminal Vin. At this time, the load unit does not pass through the second resistor R2.

[0036] When the power supply Vin is de-energized, NPN transistor Q3 is turned off, and PMOS transistor Q1 is also turned off to prevent reverse current flow. At this time, PNP transistor Q2 is turned on, and the load unit discharges quickly through the second resistor R2. This achieves the requirement of rapid discharge, enables ultra-low power consumption design, and ensures no voltage drop in the power supply path (the voltage drop of PMOS transistor Q1 with low on-resistance is negligible).

[0037] In one embodiment, a PMOS transistor Q1 serves as a unidirectional conduction and cutoff switch, and a PNP transistor Q2 acts as a fast discharge switch when the power supply terminal Vin is de-energized, enabling the load unit to discharge rapidly through a relevant resistor. Simultaneously, an NPN transistor Q3 turns off the PMOS transistor Q1 when the power supply terminal Vin is de-energized, preventing current backflow. This achieves both the requirement for rapid discharge and an ultra-low power consumption design, while also ensuring zero voltage drop in the power supply path (the voltage drop of the PMOS transistor Q1, with its low on-resistance, is negligible, equivalent to zero voltage drop).

[0038] In one embodiment, based on the above embodiment, the load unit is provided with a load capacitor CL and a load resistor RL connected in parallel to ground.

[0039] In this embodiment, the load unit plays an important role in the self-discharge circuit. It has a load capacitor CL and a load resistor RL connected in parallel to ground (that is, the two branches of the load unit are grounded simultaneously through the load capacitor CL and the load resistor RL respectively). The two work together to ensure the stable operation of the circuit and the realization of specific functions.

[0040] When Vin is powered normally, the load capacitor CL charges and stores energy, while the load resistor RL limits current and divides voltage to ensure stable circuit operation. When Vin is de-energized, the energy stored in the load capacitor CL can be released through the load resistor RL and other discharge paths, enabling rapid discharge of the load unit. Simultaneously, the presence of the load resistor RL controls the magnitude of the discharge current, preventing excessive current surges during discharge and protecting circuit components.

[0041] In summary, the load capacitor CL and load resistor RL in the load unit, connected to ground in parallel, jointly achieve functions such as energy storage, voltage stabilization, current limiting, and voltage division, providing an important guarantee for the normal operation of the self-discharge circuit and the stable operation of electronic equipment.

[0042] The design specifications for the load capacitor CL and the load resistor RL are such that the load voltage VL can be equal to the input voltage when the power supply terminal Vin can provide the corresponding input voltage through the PMOS transistor Q1.

[0043] In one embodiment, based on the above embodiment, the first resistor R1 is an adjustable resistor. By adjusting the resistance value of the first resistor R1, the magnitude of the low-power current can be adjusted. Thus, in practical applications, the resistance value of the first resistor R1 can be flexibly adjusted according to different working scenarios and requirements.

[0044] In one embodiment, based on the above embodiment, the second resistor R2 is an adjustable resistor. By adjusting the resistance value of the second resistor R2, the discharge speed can be adjusted, and the smaller the resistance value of the second resistor R2, the faster the discharge speed. The adjustable second resistor R2 brings more flexibility and advantages to the design and application of the self-discharge circuit, enabling precise control of the discharge speed of the load unit according to specific needs, thereby improving the performance and practicality of the entire circuit.

[0045] This utility model further proposes an electronic device, which includes a self-discharge circuit. The specific structure of the self-discharge circuit is as described in the above embodiments. Since this electronic device adopts all the technical solutions of all the above embodiments, it has at least all the technical effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0046] Optionally, the electronic device further includes a power supply module, which is electrically connected to the power supply terminal Vin of the self-discharge circuit.

[0047] Optionally, the power supply module includes a battery compartment for a pluggable battery. This way, when the battery is removed from the compartment, the power supply terminal Vin is de-energized, allowing the load unit to discharge quickly through the second resistor R2.

[0048] Optionally, the pluggable battery is a dry cell battery. This self-discharge circuit is particularly suitable for low-power devices (i.e., low-power supply products).

[0049] The adjustable first resistor R1 in the self-discharge circuit can be adjusted according to the actual power consumption of low-power devices to ensure that the current is kept at a low level during normal operation, thereby further reducing power consumption. For example, some small wireless sensor devices have extremely low power; by adjusting the first resistor R1, the power of the dry cell battery can be fully utilized, extending the battery's lifespan.

[0050] Low-power devices have relatively little stored energy in their load cells after the battery is removed. The rapid discharge function achieved by the self-discharge circuit through the second resistor R2 is very suitable for low-power devices. Because the load cells have little energy, rapid discharge can be completed in a short time without damaging the device. At the same time, the adjustable second resistor R2 can be flexibly adjusted according to the specific requirements of the low-power device, ensuring that the device can quickly and stably resume operation after the battery is replaced.

[0051] Furthermore, this self-discharge circuit avoids the problems caused by diode differential voltage. Its structure, comprised of a load capacitor CL, an adjustable first resistor R1, and an adjustable second resistor R2, better adapts to the needs of low-power products. The load capacitor CL stores energy during power supply and provides energy support during power fluctuations or interruptions, ensuring circuit stability. The adjustable first resistor R1 can be adjusted according to the power supply characteristics of the dry cell battery and the power consumption requirements of the device, reducing the overall power consumption of the circuit and minimizing the voltage drop across the internal resistance of the power supply module. The adjustable second resistor R2 allows for flexible control of the discharge rate of the load unit, enabling the device to respond quickly and stably during battery replacements and other situations.

[0052] The above description is only a part or preferred embodiment of this utility model. Neither the text nor the drawings should limit the scope of protection of this utility model. All equivalent structural transformations made using the content of this utility model specification and drawings under the overall concept of this utility model, or direct / indirect applications in other related technical fields, are included within the scope of protection of this utility model.

Claims

1. A self-discharge circuit, characterized in that, include: The system includes a power supply terminal, a PMOS transistor, a PNP transistor, an NPN transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a load unit. The power supply terminal is electrically connected to the source of the PMOS transistor and the base of the PNP transistor. The power supply terminal is also grounded via the fifth resistor and the third resistor. The third resistor is also connected between the base and emitter of the NPN transistor. The collector of the NPN transistor is electrically connected to the gate of the PMOS transistor. The first resistor is connected between the gate and drain of the PMOS transistor. The drain of the PMOS transistor is also electrically connected to the emitter of the PNP transistor. The emitter of the PNP transistor is also electrically connected to the load unit, the collector of the PNP transistor is grounded through a second resistor, and the base of the PNP transistor is grounded through a fourth resistor.

2. The self-discharge circuit as described in claim 1, characterized in that, The load unit is equipped with a load capacitor and a load resistor connected in parallel to ground.

3. The self-discharge circuit as described in claim 1, characterized in that, The first resistor is an adjustable resistor.

4. The self-discharge circuit as described in claim 1, characterized in that, The second resistor is an adjustable resistor.

5. An electronic device, characterized in that, Includes the self-discharge circuit as described in any one of claims 1-4.

6. The electronic device as claimed in claim 5, characterized in that, The electronic device also includes a power supply module, which is electrically connected to the power supply terminal of the self-discharge circuit.

7. The electronic device as claimed in claim 6, characterized in that, The power supply module is equipped with a battery compartment for pluggable batteries.

8. The electronic device as claimed in claim 7, characterized in that, The pluggable battery is a dry cell battery.

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