Bidirectional dc-dc conversion circuit and energy storage device

Abstract

The utility model provides a kind of bidirectional DCDC conversion circuit and energy storage equipment, wherein, bidirectional DCDC conversion circuit includes: control chip;PWM drive circuit, PWM drive circuit includes first sub drive circuit and second sub drive circuit, the input end of first sub drive circuit and the input end of second sub drive circuit are electrically connected with control chip respectively;Power conversion circuit, power conversion circuit includes: first switch tube, second switch tube, third switch tube and fourth switch tube, the gate of first switch tube and the first output end of first sub drive circuit are connected, the gate of second switch tube and the second output end of first sub drive circuit are connected, the gate of third switch tube and the first output end of second sub drive circuit are connected, the gate of fourth switch tube and the second output end of second sub drive circuit are connected.The utility model sets four switch tubes, to reduce loss relative to diode in relevant technology, and then improve overall system efficiency.

Description

Technical Field

[0001] This utility model relates to the field of power electronics technology, and more specifically, to a bidirectional DC-DC converter circuit and an energy storage device. Background Technology

[0002] In related technologies, bidirectional DC-DC (Direct Current to Direct Current Converter) conversion circuits use diodes instead of MOS (Metal-Oxide-Semiconductor Field-Effect Transistors) due to the lack of MCU (Microcontroller Unit) resources. However, for the same current, the losses of diodes are much greater than those of MOS transistors, resulting in lower overall efficiency in related technologies. Utility Model Content

[0003] The present invention aims to solve the technical problems existing in the prior art or related technologies.

[0004] Therefore, the first aspect of this utility model proposes a bidirectional DC-DC converter circuit.

[0005] The second aspect of this utility model proposes an energy storage device.

[0006] In view of the above, according to the first aspect of the present invention, a bidirectional DC-DC converter circuit is proposed, wherein the bidirectional DC-DC converter circuit includes: a control chip; a PWM drive circuit, the PWM drive circuit including a first sub-drive circuit and a second sub-drive circuit, the input terminals of the first sub-drive circuit and the second sub-drive circuit being electrically connected to the control chip respectively; and a power conversion circuit, the power conversion circuit including: a first switch, a second switch, a third switch and a fourth switch, the gate of the first switch being connected to the first output terminal of the first sub-drive circuit, the gate of the second switch being connected to the second output terminal of the first sub-drive circuit, the gate of the third switch being connected to the first output terminal of the second sub-drive circuit, and the gate of the fourth switch being connected to the second output terminal of the second sub-drive circuit.

[0007] The bidirectional DC-DC converter circuit provided by this utility model mainly includes: a control chip, a PWM (Pulse Width Modulation) drive circuit, and a power conversion circuit. The control chip is responsible for the loop control, logic control, external communication, and detection and sampling of external signals for the entire circuit. The control chip also has a protection function, capable of making corresponding protection and output decisions based on input signal detection and judgment. The control chip can be an MCU (Microcontroller Unit). The PWM drive circuit has a first sub-drive circuit and a second sub-drive circuit. The input terminals of the first and second sub-drive circuits are respectively connected to the control chip. The first sub-drive circuit has a first output terminal and a second output terminal. The first output terminal of the first sub-drive circuit is connected to the gate of the first switch in the power conversion circuit, and the second output terminal of the first sub-drive circuit is connected to the gate of the second switch in the power conversion circuit. The second sub-driver circuit has a first output terminal and a second output terminal. The first output terminal of the second sub-driver circuit is connected to the gate of the third switch in the power conversion circuit, and the second output terminal of the second sub-driver circuit is connected to the gate of the fourth switch in the power conversion circuit. This allows the PWM drive circuit to output a PWM signal to control the opening and closing of the first, second, third, and fourth switches. The source of the first switch is connected to the drain of the second switch, and the source of the third switch is connected to the drain of the fourth switch. By setting a first, second, third, and fourth switching transistor in the power conversion circuit, and connecting the gates of the first and second switching transistors to the output of the first sub-driving circuit of the PWM drive circuit, and the gates of the third and fourth switching transistors to the output of the second sub-driving circuit of the PWM drive circuit, and connecting the inputs of the first and second sub-driving circuits to the control chip, the MCU (Microcontroller Unit) resources are maximized. Furthermore, the use of four switching transistors in the power conversion circuit reduces losses compared to diodes in related technologies, thereby improving the overall system efficiency.

[0008] In some technical solutions, optionally, the control chip includes: a first high-frequency pulse output pin, which is connected to the third input terminal of the first sub-driving circuit and the third input terminal of the second sub-driving circuit respectively; a second high-frequency pulse output pin, which is connected to the seventh input terminal of the first sub-driving circuit and the seventh input terminal of the second sub-driving circuit respectively; a boost enable pin, which is connected to the second and sixth input terminals of the first sub-driving circuit respectively, and is also connected to the fourth and eighth input terminals of the second sub-driving circuit respectively; a buck enable pin, which is connected to the fourth and eighth input terminals of the first sub-driving circuit respectively, and is also connected to the second and sixth input terminals of the second sub-driving circuit respectively; a first-level output pin, which is connected to the first input terminal of the first sub-driving circuit and the first input terminal of the second sub-driving circuit respectively; and a second-level output pin, which is connected to the fifth input terminal of the first sub-driving circuit and the fifth input terminal of the second sub-driving circuit respectively.

[0009] In some technical solutions, optionally, the first sub-driving circuit includes: a first driving branch, the first input terminal of the first driving branch being connected to a first level output pin, the second input terminal of the first driving branch being connected to a boost enable pin, the third input terminal of the first driving branch being connected to a first high-frequency pulse output pin, the fourth input terminal of the first driving branch being connected to a buck enable pin, and the output terminal of the first driving branch being connected to a first switching transistor; and a second driving branch, the first input terminal of the second driving branch being connected to a second level output pin, the second input terminal of the second driving branch being connected to a boost enable pin, the third input terminal of the second driving branch being connected to a second high-frequency pulse output pin, the fourth input terminal of the second driving branch being connected to a buck enable pin, and the output terminal of the second driving branch being connected to a second switching transistor.

[0010] In some technical solutions, optionally, the second sub-driving circuit includes: a third driving branch, wherein the first input terminal of the third driving branch is connected to a first level output pin, the second input terminal of the third driving branch is connected to a buck enable pin, the third input terminal of the third driving branch is connected to a first high-frequency pulse output pin, the fourth input terminal of the third driving branch is connected to a boost enable pin, and the output terminal of the third driving branch is connected to a third switching transistor; and a fourth driving branch, wherein the first input terminal of the fourth driving branch is connected to a second level output pin, the second input terminal of the fourth driving branch is connected to a buck enable pin, the third input terminal of the fourth driving branch is connected to a second high-frequency pulse output pin, the fourth input terminal of the fourth driving branch is connected to a boost enable pin, and the output terminal of the fourth driving branch is connected to a fourth switching transistor.

[0011] In some technical solutions, optionally, the first driving branch includes: a first AND gate circuit, the first input terminal of the first AND gate circuit being connected to a first level output pin, and the second input terminal of the first AND gate circuit being connected to a boost enable pin; a first diode, the anode of the first diode being connected to the output terminal of the first AND gate circuit, and the cathode of the first diode being connected to the gate of the first switching transistor; a second AND gate circuit, the first input terminal of the second AND gate circuit being connected to a first high-frequency pulse output pin, and the second input terminal of the second AND gate circuit being connected to a buck enable pin; and a second diode, the anode of the second diode being connected to the output terminal of the second AND gate circuit, and the cathode of the second diode being connected to the gate of the first switching transistor.

[0012] In some technical solutions, optionally, the second driving branch includes: a third AND gate circuit, the first input terminal of which is connected to the second level output pin, and the second input terminal of which is connected to the boost enable pin; a third diode, the anode of which is connected to the output terminal of the third AND gate circuit, and the cathode of which is connected to the gate of the second switching transistor; a fourth AND gate circuit, the first input terminal of which is connected to the second high-frequency pulse output pin, and the second input terminal of which is connected to the buck enable pin; and a fourth diode, the anode of which is connected to the output terminal of the fourth AND gate circuit, and the cathode of which is connected to the gate of the second switching transistor.

[0013] In some technical solutions, optionally, the third driving branch includes: a fifth AND gate circuit, the first input terminal of which is connected to the first level output pin, and the second input terminal of which is connected to the buck enable pin; a fifth diode, the anode of which is connected to the output terminal of the fifth AND gate circuit, and the cathode of which is connected to the gate of the third switching transistor; a sixth AND gate circuit, the first input terminal of which is connected to the first high-frequency pulse output pin, and the second input terminal of which is connected to the boost enable pin; and a sixth diode, the anode of which is connected to the output terminal of the sixth AND gate circuit, and the cathode of which is connected to the gate of the third switching transistor.

[0014] In some technical solutions, optionally, the fourth driving branch includes: a seventh AND gate circuit, the first input terminal of which is connected to the second level output pin, and the second input terminal of which is connected to the buck enable pin; a seventh diode, the anode of which is connected to the output terminal of the seventh AND gate circuit, and the cathode of which is connected to the gate of the fourth switch; an eighth AND gate circuit, the first input terminal of which is connected to the second high-frequency pulse output pin, and the second input terminal of which is connected to the boost enable pin; and an eighth diode, the anode of which is connected to the output terminal of the eighth AND gate circuit, and the cathode of which is connected to the gate of the fourth switch.

[0015] In some technical solutions, the power conversion circuit may optionally include: a first capacitor, the first end of which is connected to the drain of the first switching transistor, and the second end of which is connected to the source of the second switching transistor; a first inductor, the first end of which is connected to the source of the first switching transistor and the drain of the second switching transistor, and the second end of which is connected to the source of the third switching transistor and the drain of the fourth switching transistor; and a second capacitor, the first end of which is connected to the drain of the third switching transistor, and the second end of which is connected to the source of the fourth switching transistor.

[0016] According to a second aspect of the present invention, an energy storage device is proposed, comprising a bidirectional DC-DC converter circuit as described in any of the above claims.

[0017] The energy storage device provided by this utility model includes a bidirectional DC-DC converter circuit as described above, which can achieve the technical effects of any of the above technical solutions, and will not be described in detail here.

[0018] Additional aspects and advantages of this invention will become apparent in the following description or may be learned by practice of this invention. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 A schematic diagram of the bidirectional DC-DC converter circuit of the related technology is shown; Figure 2 A schematic diagram of the structure of a bidirectional DC-DC converter circuit according to an embodiment of the present invention is shown; Figure 3 This diagram shows a schematic of the control chip in a bidirectional DC-DC converter circuit according to an embodiment of the present invention. Figure 4 This diagram shows a schematic of the PWM drive circuit in a bidirectional DC-DC converter circuit according to an embodiment of the present invention. Figure 5 This diagram shows a schematic of the power conversion circuit in a bidirectional DC-DC converter circuit according to an embodiment of the present invention. Figure 6 A schematic diagram of the structure of an energy storage device according to an embodiment of the present invention is shown.

[0020] in, Figures 1 to 6 The correspondence between the reference numerals and component names in the attached drawings is as follows: 100' Bidirectional DC-DC converter circuit, Q1' First switch, Q2' Second switch, D1' First diode, D2' Second diode, C1' First capacitor, C2' Second capacitor, L1' First inductor, 10 Energy storage device, 100 Bidirectional DC-DC converter circuit, 102 Control chip, 104 PWM drive circuit, 1042 First sub-drive circuit, 1044 Second sub-drive circuit, 106 Power conversion circuit, Q1 First switch, Q2 Second switch, Q3 Third switch, Q4 Fourth switch, 1022 First high-frequency pulse output pin, 1024 Second high-frequency pulse output pin, 1026 Boost enable pin, 1028 Buck enable pin, 1 030 First level output pin, 1032 Second level output pin, 1046 First drive branch, 1048 Second drive branch, 1050 Third drive branch, 1052 Fourth drive branch, U1A First AND gate circuit, D1 First diode, U1B Second AND gate circuit, D2 Second diode, U1C Third AND gate circuit, D3 Third diode, U1D Fourth AND gate circuit, D4 Fourth diode, U2A Fifth AND gate circuit, D5 Fifth diode, U2B Sixth AND gate circuit, D6 Sixth diode, U2C Seventh AND gate circuit, D7 Seventh diode, U2D Eighth AND gate circuit, D8 Eighth diode, C1 First capacitor, C2 Second capacitor, L1 First inductor. Detailed Implementation

[0021] To better understand the above-mentioned objectives, features, and advantages of this utility model, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments of this utility model and the features thereof can be combined with each other.

[0022] Many specific details are set forth in the following description in order to provide a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0023] Figure 1 A schematic diagram of the structure of a bidirectional DC-DC converter circuit of the relevant technology is shown, such as... Figure 1As shown, the bidirectional DC-DC converter circuit 100' includes: a first switch Q1', a second switch Q2', a first diode D1', a second diode D2', a first capacitor C1', a second capacitor C2', and a first inductor L1'. The source of the first switch Q1' is connected to the cathode of the first diode D1', the drain of the first switch Q1' is connected to the first terminal of the first capacitor C1', and the anode of the first diode D1' is connected to the second terminal of the first capacitor C1'. The first terminal of the first inductor L1' is connected to both the source of the first switch Q1' and the cathode of the first diode D1', and the second terminal of the first inductor L1' is connected to both the anode of the second diode D2' and the drain of the second switch Q2'. The first terminal of the second capacitor C2' is connected to the cathode of the second diode D2', and the second terminal of the second capacitor C2' is connected to the source of the second switch Q2'. The gates of the first switch Q1' and the second switch Q2' are connected to the MCU. However, in related technologies, although using diodes to replace MOSFETs reduces the demand for MCU resources, the losses of diodes are much greater than those of MOSFETs. Therefore, the overall system efficiency will decrease.

[0024] like Figure 2 , Figure 3 , Figure 4 as well as Figure 5 As shown, this utility model proposes a bidirectional DC-DC converter circuit 100, which includes: a control chip 102; a PWM drive circuit 104, which includes a first sub-drive circuit 1042 and a second sub-drive circuit 1044, the input terminals of the first sub-drive circuit 1042 and the second sub-drive circuit 1044 being electrically connected to the control chip 102 respectively; and a power conversion circuit 106, which includes: a first switch Q1, a second switch Q2, a third switch Q3, and a fourth switch Q4, the gate of the first switch Q1 being connected to the first output terminal of the first sub-drive circuit 1042, the gate of the second switch Q2 being connected to the second output terminal of the first sub-drive circuit 1042, the gate of the third switch Q3 being connected to the first output terminal of the second sub-drive circuit 1044, and the gate of the fourth switch Q4 being connected to the second output terminal of the second sub-drive circuit 1044.

[0025] The bidirectional DC-DC converter circuit 100 provided by this utility model mainly includes: a control chip 102, a PWM (Pulse Width Modulation) drive circuit, and a power conversion circuit 106. The control chip 102 is responsible for the loop control, logic control, external communication, and detection and sampling of external signals for the entire circuit. The control chip 102 also has a protection function; it can perform corresponding protection and output actions based on the input signal detection and judgment. The control chip 102 can be an MCU (Microcontroller Unit). The PWM drive circuit 104 has a first sub-drive circuit 1042 and a second sub-drive circuit 1044. The input terminals of the first sub-drive circuit 1042 and the second sub-drive circuit 1044 are respectively connected to the control chip 102. The first sub-drive circuit 1042 has a first output terminal and a second output terminal. The first output terminal of the first sub-drive circuit 1042 is connected to the gate of the first switch Q1 in the power conversion circuit 106, and the second output terminal of the first sub-drive circuit 1042 is connected to the gate of the second switch Q2 in the power conversion circuit 106. The second sub-drive circuit 1044 has a first output terminal and a second output terminal. The first output terminal of the second sub-drive circuit 1044 is connected to the gate of the third switch Q3 in the power conversion circuit 106, and the second output terminal of the second sub-drive circuit 1044 is connected to the gate of the fourth switch Q4 in the power conversion circuit 106. Thus, the PWM drive circuit 104 can output a PWM signal to control the switching on and off of the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4. The source of the first switch Q1 is connected to the drain of the second switch Q2, and the source of the third switch Q3 is connected to the drain of the fourth switch Q4. By setting a first switch Q1, a second switch Q2, a third switch Q3, and a fourth switch Q4 in the power conversion circuit 106, and connecting the gates of the first switch Q1 and the second switch Q2 to the output of the first sub-drive circuit 1042 of the PWM drive circuit 104, and connecting the gates of the third switch Q3 and the fourth switch Q4 to the output of the second sub-drive circuit 1044 of the PWM drive circuit 104, and connecting the inputs of the first sub-drive circuit 1042 and the second sub-drive circuit 1044 to the control chip 102, the MCU (Microcontroller Unit) resources are maximized. At the same time, since four switches are set in the power conversion circuit (106), the losses are reduced compared to diodes in related technologies, thereby improving the overall system efficiency.

[0026] In some embodiments, optionally, such as Figure 3, Figure 4 as well as Figure 5 As shown, the control chip 102 includes: a first high-frequency pulse output pin 1022, which is connected to the third input terminal of the first sub-drive circuit 1042 and the third input terminal of the second sub-drive circuit 1044; a second high-frequency pulse output pin 1024, which is connected to the seventh input terminal of the first sub-drive circuit 1042 and the seventh input terminal of the second sub-drive circuit 1044; and a boost enable pin 1026, which is connected to the second and sixth input terminals of the first sub-drive circuit 1042 and the fourth input terminal of the second sub-drive circuit 1044. The first input is connected to the fourth input and the eighth input; the buck enable pin 1028 is connected to the fourth input and the eighth input of the first sub-drive circuit 1042, and is also connected to the second input and the sixth input of the second sub-drive circuit 1044; the first level output pin 1030 is connected to the first input of the first sub-drive circuit 1042 and the first input of the second sub-drive circuit 1044; the second level output pin 1032 is connected to the fifth input of the first sub-drive circuit 1042 and the fifth input of the second sub-drive circuit 1044.

[0027] In this embodiment, the control chip 102 includes: a first high-frequency pulse output pin 1022, a second high-frequency pulse output pin 1024, a boost enable pin 1026, a buck enable pin 1028, a first level output pin 1030, and a second level output pin 1032. The first high-frequency pulse output pin 1022 is connected to the third input terminal of the first sub-driving circuit 1042 and the third input terminal of the second sub-driving circuit 1044, respectively. The second high-frequency pulse output pin 1024 is connected to the seventh input terminal of the first sub-driving circuit 1042 and the seventh input terminal of the second sub-driving circuit 1044, respectively. The first high-frequency pulse output pin 1022 and the second high-frequency pulse output pin 1024 can output high-frequency pulse square wave signals, and the high-frequency pulse square wave signal output by the first high-frequency pulse output pin 1022 is complementary to the high-frequency pulse square wave signal output by the second high-frequency pulse output pin 1024. The boost enable pin 1026 is connected to the second input terminal and the sixth input terminal of the first sub-drive circuit 1042, respectively. The boost enable pin 1026 is also connected to the fourth input terminal and the eighth input terminal of the second sub-drive circuit 1044, respectively. The boost enable pin 1026 can output a high-level signal when the bidirectional DC-DC converter circuit 100 is operating in boost mode, and output a low-level signal when the bidirectional DC-DC converter circuit 100 is operating in buck mode. The buck enable pin 1028 is connected to the fourth and eighth input terminals of the first sub-drive circuit 1042, respectively. The buck enable pin 1028 is also connected to the second and sixth input terminals of the second sub-drive circuit 1044, respectively. The buck enable pin 1028 can output a high-level signal when the bidirectional DC-DC converter circuit 100 is operating in buck mode, and output a low-level signal when the bidirectional DC-DC converter circuit 100 is operating in boost mode. The first level output pin 1030 is connected to the first input terminal of the first sub-driving circuit 1042 and the first input terminal of the second sub-driving circuit 1044, respectively. The second level output pin 1032 is connected to the fifth input terminal of the first sub-driving circuit 1042 and the fifth input terminal of the second sub-driving circuit 1044, respectively. When the control chip 102 is powered on, the first level output pin 1030 outputs a high-level signal and the second level output pin 1032 outputs a low-level signal. When the control chip 102 is powered off, the second level output pin 1032 outputs a high-level signal and the first level output pin 1030 outputs a low-level signal.Simultaneously, the first, second, third, and fourth input terminals of the first sub-driving circuit 1042 are connected to its first output terminal. Based on the outputs of the first level output pin 1030, the boost enable pin 1026, the first high-frequency pulse output pin 1022, and the buck enable pin 1028, a corresponding PWM signal is output to the first switching transistor Q1, thereby controlling Q1 to operate. Similarly, based on the outputs of the second level output pin 1032, the boost enable pin 1026, the second high-frequency pulse output pin 1024, and the buck enable pin 1028, a corresponding PWM signal is output to the second switching transistor Q2, thereby controlling Q2 to operate. Similarly, based on the outputs of the first level output pin 1030, the buck enable pin 1028, the first high-frequency pulse output pin 1022, and the boost enable pin 1026, a corresponding PWM signal is output to the third switching transistor Q3, thereby controlling Q3 to operate. The fourth switch Q4 can be controlled by outputting the corresponding PWM signal based on the outputs of the second-level output pin 1032, the buck enable pin 1028, the first high-frequency pulse output pin 1022, and the boost enable pin 1026. This invention utilizes the first high-frequency pulse output pin 1022, the second high-frequency pulse output pin 1024, the boost enable pin 1026, the buck enable pin 1028, the first-level output pin 1030, and the second-level output pin 1032, respectively, connected to different input terminals of the first sub-drive circuit 1042 and the second sub-drive circuit 1044, thereby precisely controlling the circuit's operating mode and the specific state of each switch. This invention uses only two high-frequency PWM channels and four ordinary I / O channels to control the entire bidirectional DC-DC circuit, thus reducing the demand for peripheral resources and configuration requirements of the control chip 102, and lowering the device cost of the control chip 102.

[0028] In some embodiments, optionally, such as Figure 3 , Figure 4 as well as Figure 5As shown, the first sub-driving circuit 1042 includes: a first driving branch 1046, the first input terminal of the first driving branch 1046 being connected to a first level output pin 1030, the second input terminal of the first driving branch 1046 being connected to a boost enable pin 1026, the third input terminal of the first driving branch 1046 being connected to a first high-frequency pulse output pin 1022, the fourth input terminal of the first driving branch 1046 being connected to a buck enable pin 1028, and the output terminal of the first driving branch 1046 being connected to a first high-frequency pulse output pin 1022. The switching transistor Q1 is connected; the second driving branch 1048 has its first input terminal connected to the second level output pin 1032, its second input terminal connected to the boost enable pin 1026, its third input terminal connected to the second high-frequency pulse output pin 1024, its fourth input terminal connected to the buck enable pin 1028, and its output terminal connected to the second switching transistor Q2.

[0029] In this embodiment, the first sub-driving circuit 1042 includes a first driving branch 1046 and a second driving branch 1048. The first driving branch 1046 has a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, and an output terminal. The first input terminal of the first driving branch 1046 is connected to a first level output pin 1030, the second input terminal is connected to a boost enable pin 1026, the third input terminal is connected to a first high-frequency pulse output pin 1022, the fourth input terminal is connected to a buck enable pin 1028, and the output terminal is connected to the gate of the first switching transistor Q1. Therefore, the first switching transistor Q1 can be controlled according to the output signals of the first level output pin 1030, the boost enable pin 1026, the first high-frequency pulse output pin 1022, and the buck enable pin 1028. The second drive branch 1048 has a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, and an output terminal. The first input terminal of the second drive branch 1048 is connected to the second level output pin 1032, the second input terminal is connected to the boost enable pin 1026, the third input terminal is connected to the second high-frequency pulse output pin 1024, the fourth input terminal is connected to the buck enable pin 1028, and the output terminal is connected to the gate of the second switch Q2. Therefore, the second switch Q2 can be controlled according to the output signals of the second level output pin 1032, the boost enable pin 1026, the second high-frequency pulse output pin 1024, and the buck enable pin 1028. This invention achieves precise and independent dynamic control of the first switch Q1 and the second switch Q2 by setting the first drive branch 1046 and the second drive branch 1048, ensuring the efficient execution of the PWM multiplexing function.

[0030] In some embodiments, optionally, such as Figure 3 , Figure 4 as well as Figure 5As shown, the second sub-driving circuit 1044 includes: a third driving branch 1050, the first input terminal of the third driving branch 1050 being connected to the first level output pin 1030, the second input terminal of the third driving branch 1050 being connected to the buck enable pin 1028, the third input terminal of the third driving branch 1050 being connected to the first high-frequency pulse output pin 1022, the fourth input terminal of the third driving branch 1050 being connected to the boost enable pin 1026, and the output terminal of the third driving branch 1050 being connected to the third... The switching transistor Q3 is connected; the fourth drive branch 1052 has its first input terminal connected to the second level output pin 1032, its second input terminal connected to the buck enable pin 1028, its third input terminal connected to the second high-frequency pulse output pin 1024, its fourth input terminal connected to the boost enable pin 1026, and its output terminal connected to the fourth switching transistor Q4.

[0031] In this embodiment, the second sub-driving circuit 1044 includes a third driving branch 1050 and a fourth driving branch 1052. The third driving branch 1050 has a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, and an output terminal. The first input terminal of the third driving branch 1050 is connected to a first level output pin 1030, the second input terminal is connected to a buck enable pin 1028, the third input terminal is connected to a first high-frequency pulse output pin 1022, the fourth input terminal is connected to a boost enable pin 1026, and the output terminal is connected to the gate of the third switching transistor Q3. Therefore, the third switching transistor Q3 can be controlled according to the output signals of the first level output pin 1030, the buck enable pin 1028, the first high-frequency pulse output pin 1022, and the boost enable pin 1026. The fourth drive branch 1052 has a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, and an output terminal. The first input terminal of the fourth drive branch 1052 is connected to the second-level output pin 1032, the second input terminal is connected to the buck enable pin 1028, the third input terminal is connected to the second high-frequency pulse output pin 1024, the fourth input terminal is connected to the boost enable pin 1026, and the output terminal is connected to the gate of the fourth switch Q4. Therefore, the fourth switch Q4 can be controlled according to the output signals of the second-level output pin 1032, the buck enable pin 1028, the second high-frequency pulse output pin 1024, and the boost enable pin 1026. This invention achieves precise and independent dynamic control of the third switch Q3 and the fourth switch Q4 by setting the third drive branch 1050 and the fourth drive branch 1052, thus ensuring the efficient execution of the PWM multiplexing function.

[0032] In some embodiments, optionally, such as Figure 3 , Figure 4 as well as Figure 5As shown, the first driving branch 1046 includes: a first AND gate circuit U1A, the first input terminal of the first AND gate circuit U1A is connected to the first level output pin 1030, and the second input terminal of the first AND gate circuit U1A is connected to the boost enable pin 1026; a first diode D1, the anode of the first diode D1 is connected to the output terminal of the first AND gate circuit U1A, and the cathode of the first diode D1 is connected to the gate of the first switching transistor Q1; a second AND gate circuit U1B, the first input terminal of the second AND gate circuit U1B is connected to the first high-frequency pulse output pin, and the second input terminal of the second AND gate circuit U1B is connected to the buck enable pin 1028; and a second diode D2, the anode of the second diode D2 is connected to the output terminal of the second AND gate circuit U1B, and the cathode of the second diode D2 is connected to the gate of the first switching transistor Q1.

[0033] In this embodiment, the first driving branch 1046 includes: a first AND gate U1A, a first diode D1, a second AND gate U1B, and a second diode D2. The first input terminal of the first AND gate U1A is connected to the first level output pin 1030, the second input terminal of the first AND gate U1A is connected to the boost enable pin 1026, the anode of the first diode D1 is connected to the output terminal of the first AND gate U1A, and the cathode of the first diode D1 is connected to the gate of the first switching transistor Q1. When the first level output pin 1030 outputs a high-level signal and the boost enable pin 1026 also outputs a high-level signal, the output terminal of the first AND gate U1A outputs a high-level signal. The first diode D1 serves as unidirectional isolation. The first input terminal of the second AND gate U1B is connected to the first high-frequency pulse output pin, and the second input terminal of the second AND gate U1B is connected to the buck enable pin 1028. The output terminal of the second AND gate U1B is connected to the anode of the second diode D2, and the cathode of the second diode D2 is connected to the gate of the first switching transistor Q1. When the first high-frequency pulse output pin outputs a high-level signal and the buck enable pin 1028 outputs a high-level signal, the output terminal of the second AND gate U1B outputs a high-level signal. The second diode D2 acts as a unidirectional isolation. This invention realizes the dynamic switching of two control signals for the first switching transistor Q1. The first drive branch 1046 constitutes a high-efficiency two-to-one switch. In boost mode, the first level output pin 1030 of the control chip 102 outputs a high-level signal, and the boost enable pin 1026 also outputs a high-level signal. Consequently, the first AND gate U1A outputs a high-level signal, thereby controlling the first switching transistor Q1 to be in the normally open state. In buck mode, the buck enable pin 1028 of the control chip 102 outputs a high level, and the second level output pin 1032 outputs a high-frequency square wave signal. This, in turn, outputs a high-frequency square wave signal through the second AND gate circuit, thereby controlling the first switching transistor Q1 to be in a high-frequency switching state. This invention shares the same gate drive port of the switching transistor across two different control modes. Through the mutually exclusive enable signals of the boost enable pin 1026 and the buck enable pin 1028, signal path switching is automatically and reliably completed at the hardware level, eliminating the need for the MCU to generate additional PWM signals or perform complex switching judgments, thus achieving true drive multiplexing.

[0034] In some embodiments, optionally, such as Figure 3 , Figure 4 as well as Figure 5As shown, the second drive branch 1048 includes: a third AND gate U1C, the first input terminal of which is connected to the second level output pin 1032, and the second input terminal of which is connected to the boost enable pin 1026; a third diode D3, the anode of which is connected to the output terminal of the third AND gate U1C, and the cathode of which is connected to the gate of the second switch Q2; a fourth AND gate U1D, the first input terminal of which is connected to the second high-frequency pulse output pin 1024, and the second input terminal of which is connected to the buck enable pin 1028; and a fourth diode D4, the anode of which is connected to the output terminal of the fourth AND gate U1D, and the cathode of which is connected to the gate of the second switch Q2.

[0035] In this embodiment, the second driving branch 1048 includes: a third AND gate U1C, a third diode D3, a fourth AND gate U1D, and a fourth diode D4. The first input terminal of the third AND gate U1C is connected to the second level output pin 1032, the second input terminal of the third AND gate U1C is connected to the boost enable pin 1026, the output terminal of the third AND gate U1C is connected to the anode of the third diode D3, and the cathode of the third diode D3 is connected to the gate of the second switch Q2. When the second level output pin 1032 outputs a high-level signal and the boost enable pin 1026 outputs a high-level signal, the output terminal of the third AND gate U1C outputs a high-level signal, thereby controlling the gate of the second switch Q2 to be in a high-level state. The third diode D3 provides unidirectional isolation. The first input terminal of the fourth AND gate U1D is connected to the second high-frequency pulse output pin 1024, the second input terminal of the fourth AND gate U1D is connected to the buck enable pin 1028, the output terminal of the fourth AND gate U1D is connected to the anode of the fourth diode D4, and the cathode of the fourth diode D4 is connected to the gate of the second switch Q2. When the second high-frequency pulse output pin 1024 outputs a high-level signal and the buck enable pin 1028 outputs a high-level signal, the output terminal of the fourth AND gate U1D outputs a high-level signal, thereby making the gate of the second switch Q2 high-level. The fourth diode D4 plays a unidirectional isolation role. This utility model realizes the dynamic switching of the two control signals of the second switch Q2. The second drive branch 1048 constitutes a high-efficiency two-to-one switch. In boost mode, the second level output pin 1032 of the control chip 102 outputs a low-level signal, thereby making the third AND gate continuously output a low-level signal, thus controlling the second switch Q2 to be in the normally off state. In buck mode, the buck enable pin 1028 of the control chip 102 outputs a high level, and the second high-frequency pulse output pin 1024 outputs a high-frequency square wave signal. This, in turn, outputs a high-frequency square wave signal through the fourth AND gate U1D, thereby controlling the second switch Q2 to be in a high-frequency switching state. In this invention, the two signals driving the second switch Q2 are mutually exclusive signals output from the boost enable pin 1026 and the buck enable pin 1028, ensuring that the normally off path and the PWM switching path will never be simultaneously turned on. By having the first switch Q1 and the second switch Q2 operate simultaneously as a complementary switch pair in buck mode, this invention ensures that high-frequency pulse signals from the same control chip 102 pin can be safely transmitted to the second switch Q2, forming a strict complementary relationship with the drive signal of the first switch Q1. This fundamentally eliminates the risk of burning out devices due to simultaneous conduction of the first and second switches Q1 caused by incorrect drive signals, greatly improving system reliability.

[0036] In some embodiments, optionally, such as Figure 3, Figure 4 as well as Figure 5 As shown, the third drive branch 1050 includes: a fifth AND gate U2A, the first input terminal of which is connected to the first level output pin 1030, and the second input terminal of which is connected to the buck enable pin 1028; a fifth diode D5, the anode of which is connected to the output terminal of the fifth AND gate U2A, and the cathode of which is connected to the gate of the third switch Q3; a sixth AND gate U2B, the first input terminal of which is connected to the first high-frequency pulse output pin 1022, and the second input terminal of which is connected to the boost enable pin 1026; and a sixth diode D6, the anode of which is connected to the output terminal of the sixth AND gate U2B, and the cathode of which is connected to the gate of the third switch Q3.

[0037] In this embodiment, the third driving branch 1050 includes a fifth AND gate U2A, a fifth diode D5, a sixth AND gate U2B, and a sixth diode D6. The first input terminal of the fifth AND gate U2A is connected to the first level output pin 1030, the second input terminal of the fifth AND gate U2A is connected to the buck enable pin 1028, the output terminal of the fifth AND gate U2A is connected to the anode of the fifth diode D5, and the cathode of the fifth diode D5 is connected to the gate of the third switch Q3. When the first level output pin 1030 outputs a high-level signal and the buck enable pin 1028 outputs a high-level signal, the output terminal of the fifth AND gate U2A outputs a high-level signal, thus putting the gate of the third switch Q3 at a high level. The fifth diode D5 provides unidirectional isolation. The first input terminal of the sixth AND gate U2B is connected to the first high-frequency pulse output pin 1022, the second input terminal of the sixth AND gate U2B is connected to the boost enable pin 1026, the output terminal of the sixth AND gate U2B is connected to the anode of the sixth diode D6, and the cathode of the sixth diode D6 is connected to the gate of the third switch Q3. When the first high-frequency pulse output pin 1022 outputs a high-level signal and the boost enable pin 1026 outputs a high-level signal, the sixth AND gate U2B outputs a high-level signal, thus keeping the gate of the third switch Q3 in a high-level state. This invention achieves dynamic switching between two control signals for the third switch Q3. The third drive branch 1050 constitutes a highly efficient two-to-one switch. In buck mode, the first level output pin 1030 of the control chip 102 outputs a high-level signal, and the buck enable pin 1028 also outputs a high-level signal. Consequently, the fifth AND gate U2A outputs a high-level signal, thereby controlling the third switch Q3 to be in a normally open state. In boost mode, the boost enable pin 1026 of the control chip 102 outputs a high level, the first high-frequency pulse output pin 1022 outputs a high-frequency square wave signal, and then the sixth AND gate circuit U2B outputs a high-frequency square wave signal, thereby controlling the third switch Q3 to be in a high-frequency switching state. This invention shares the gate drive port of the same switch in two different control modes. Through the mutually exclusive enable signals of the boost enable pin 1026 and the buck enable pin 1028, the signal path switching is automatically and reliably completed at the hardware level, without the need for the MCU to generate additional PWM signals or perform complex switching judgments, thus achieving true drive multiplexing.

[0038] In some embodiments, optionally, such as Figure 3 , Figure 4 as well as Figure 5As shown, the fourth drive branch 1052 includes: a seventh AND gate U2C, the first input terminal of which is connected to the second level output pin 1032, and the second input terminal of which is connected to the buck enable pin 1028; a seventh diode D7, the anode of which is connected to the output terminal of the seventh AND gate U2C, and the cathode of which is connected to the gate of the fourth switch Q4; an eighth AND gate U2D, the first input terminal of which is connected to the second high-frequency pulse output pin 1024, and the second input terminal of which is connected to the boost enable pin 1026; and an eighth diode D8, the anode of which is connected to the output terminal of the eighth AND gate U2D, and the cathode of which is connected to the gate of the fourth switch Q4.

[0039] In this embodiment, the fourth driving branch 1052 includes: a seventh AND gate U2C, a seventh diode D7, an eighth AND gate U2D, and an eighth diode D8. The first input terminal of the seventh AND gate U2C is connected to the second-level output pin 1032, the second input terminal of the seventh AND gate U2C is connected to the buck enable pin 1028, the output terminal of the seventh AND gate U2C is connected to the anode of the seventh diode D7, and the cathode of the seventh diode D7 is connected to the gate of the fourth switching transistor Q4. When the second-level output pin 1032 outputs a high-level signal and the buck enable pin 1028 outputs a high-level signal, the output terminal of the seventh AND gate U2C outputs a high-level signal. The seventh diode D7 serves as unidirectional isolation. The first input terminal of the eighth AND gate U2D is connected to the second high-frequency pulse output pin 1024, the second input terminal of the eighth AND gate U2D is connected to the boost enable pin 1026, the output terminal of the eighth AND gate U2D is connected to the anode of the eighth diode D8, and the cathode of the eighth diode D8 is connected to the gate of the fourth switch Q4. When the second high-frequency pulse output pin 1024 outputs a high-level signal and the boost enable pin 1026 outputs a high-level signal, the output terminal of the eighth diode D8 outputs a high-level signal, thus the eighth diode D8 provides unidirectional isolation. This invention achieves dynamic switching between two control signals for the fourth switch Q4. The fourth drive branch 1052 constitutes a highly efficient two-to-one switch. In boost mode, the second level output pin 1032 of the control chip 102 outputs a low-level signal, thereby causing the seventh AND gate U2C to continuously output a low-level signal, thus controlling the fourth switch Q4 to be in a normally off state. In boost mode, the boost enable pin 1026 of the control chip 102 outputs a high level, and the second high-frequency pulse output pin 1024 outputs a high-frequency square wave signal. This, in turn, outputs a high-frequency square wave signal through the eighth AND gate U2D, thereby controlling the fourth switch Q4 to be in a high-frequency switching state. In this invention, the two signals driving the fourth switch Q4 are mutually exclusive signals output from the boost enable pin 1026 and the buck enable pin 1028, ensuring that the normally off path and the PWM switching path will never be turned on simultaneously. By having the third switch Q3 and the fourth switch Q4 operate simultaneously as a complementary switch pair in boost mode, this invention ensures that high-frequency pulse signals from the same control chip 102 pin can be safely transmitted to the fourth switch Q4, forming a strict complementary relationship with the drive signal of the third switch Q3. This fundamentally eliminates the risk of burning out devices due to simultaneous conduction of the third switch Q3 and the fourth switch Q4 caused by incorrect drive signals, greatly improving system reliability.

[0040] In some embodiments, optionally, such as Figure 5As shown, the power conversion circuit 106 further includes: a first capacitor C1, the first end of which is connected to the drain of the first switching transistor Q1, and the second end of which is connected to the source of the second switching transistor Q2; a first inductor L1, the first end of which is connected to the source of the first switching transistor Q1 and the drain of the second switching transistor Q2, and the second end of which is connected to the source of the third switching transistor Q3 and the drain of the fourth switching transistor Q4; and a second capacitor C2, the first end of which is connected to the drain of the third switching transistor Q3, and the second end of which is connected to the source of the fourth switching transistor Q4.

[0041] In this embodiment, the power conversion circuit 106 further includes a first capacitor C1, a first inductor L1, and a second capacitor C2. The first terminal of the first capacitor C1 is connected to the drain of the first switching transistor Q1, and the second terminal of the first capacitor C1 is connected to the source of the second switching transistor Q2. The first terminal of the first inductor L1 is connected to the source of the first switching transistor Q1 and the drain of the second switching transistor Q2, and the second terminal of the first inductor L1 is connected to the source of the third switching transistor Q3 and the drain of the fourth switching transistor Q4. The first terminal of the second capacitor C2 is connected to the drain of the third switching transistor Q3, and the second terminal of the second capacitor C2 is connected to the source of the fourth switching transistor Q4. This invention clarifies the specific connection relationships of the first capacitor C1, the first inductor L1, the second capacitor C2, and the four switching transistors. By setting the first inductor L1, it ensures that the first inductor L1 is located at the center of the energy path in both operating modes, providing an optimal physical path for efficient bidirectional energy flow. By setting the first capacitor C1 and the second capacitor C2 on the input and output sides of the circuit respectively, the ripple current generated by the high-frequency operation of the switching transistor is filtered out, effectively improving the quality of input and output power.

[0042] For example, when the bidirectional DC-DC converter circuit 100 operates in BOOST mode, the boost enable pin 1026 of the control chip 102 outputs a high-level signal, the buck enable pin 1028 outputs a low-level signal, the first level output pin 1030 outputs a high-level signal, and the second level output pin 1032 outputs a low-level signal; the first high-frequency pulse output pin 1022 and the second high-frequency pulse output pin 1024 respectively output high-frequency pulse square wave signals; after the output pin signals pass through the first AND gate circuit U1A and the second AND gate circuit U1B, the first drive branch 1046 outputs a high-level signal, and the first switch Q1 is always on; the output pin signals After passing through the third AND gate U1C and the fourth AND gate U1D, the second drive branch 1048 outputs a low-level signal, and the second switch Q2 remains off. After passing through the fifth AND gate U2A and the sixth AND gate U2B, the third drive branch 1050 outputs a high-frequency pulse square wave signal, and the third switch Q3 is in a high-frequency switching state. After passing through the seventh AND gate U2C and the eighth AND gate U2D, the fourth drive branch 1052 outputs a high-frequency pulse square wave signal, and the fourth switch Q4 is in a high-frequency switching state. The signals output by the third drive branch 1050 and the fourth drive branch 1052 are complementary signals and will not switch simultaneously. That is, when the fourth switch Q4 is on and the third switch Q3 is off, the inductor stores energy; when the third switch Q3 is on and the fourth switch Q4 is off, the inductor releases energy.

[0043] When the bidirectional DC-DC converter circuit 100 operates in BUCK mode, the boost enable pin 1026 of the control chip 102 outputs a low-level signal, the buck enable pin 1028 outputs a high-level signal, the first level output pin 1030 outputs a high-level signal, and the second level output pin 1032 outputs a low-level signal; the first high-frequency pulse output pin 1022 and the second high-frequency pulse output pin 1024 respectively output high-frequency pulse square wave signals; after the output pin signals pass through the fifth AND gate circuit U2A and the sixth AND gate circuit U2B, the third drive branch 1050 outputs a high-level signal, and the third switch Q3 is always on; the output pin signals pass through... After passing through the seventh and eighth AND gates, the fourth drive branch 1052 outputs a low-level signal, and the fourth switch Q4 is always off. The output pin signal, after passing through the first AND gate U1A and the second AND gate U1B, outputs a high-frequency pulse square wave signal in the first drive branch 1046, and the first switch Q1 is in a high-frequency switching state. After passing through the third AND gate U1C and the fourth AND gate U1D, the second drive branch 1048 outputs a high-frequency pulse square wave signal, and the second switch Q2 is in a high-frequency switching state. The signals output by the first drive branch 1046 and the second drive branch 1048 are complementary signals and will not switch simultaneously. That is, when the first switch Q1 is on and the second switch Q2 is off, the inductor stores energy; when the first switch Q1 is off and the second switch Q2 is on, the inductor releases energy.

[0044] like Figure 6 As shown, this utility model proposes an energy storage device 10, including a bidirectional DC-DC converter circuit 100 as described above.

[0045] The energy storage device 10 provided by this utility model includes a bidirectional DC-DC converter circuit 100 as described above, which can achieve the technical effects of any of the above embodiments, and will not be described again here.

[0046] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance, unless otherwise expressly specified and limited. The terms "connection," "installation," and "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0047] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0048] The above are merely preferred embodiments of this utility model and are not intended to limit the scope of this utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A bidirectional DC-DC converter circuit, characterized in that, include: Control chip; A PWM driving circuit, comprising a first sub-driving circuit and a second sub-driving circuit, wherein the input terminals of the first sub-driving circuit and the second sub-driving circuit are electrically connected to the control chip, respectively. A power conversion circuit includes a first switch, a second switch, a third switch, and a fourth switch. The gate of the first switch is connected to the first output terminal of the first sub-driving circuit. The gate of the second switch is connected to the second output terminal of the first sub-driving circuit. The gate of the third switch is connected to the first output terminal of the second sub-driving circuit. The gate of the fourth switch is connected to the second output terminal of the second sub-driving circuit.

2. The bidirectional DC-DC converter circuit according to claim 1, characterized in that, The control chip includes: The first high-frequency pulse output pin is connected to the third input terminal of the first sub-driving circuit and the third input terminal of the second sub-driving circuit, respectively. The second high-frequency pulse output pin is connected to the seventh input terminal of the first sub-driving circuit and the seventh input terminal of the second sub-driving circuit, respectively. A boost enable pin is connected to the second and sixth input terminals of the first sub-driving circuit, and is also connected to the fourth and eighth input terminals of the second sub-driving circuit. A buck enable pin is connected to the fourth and eighth input terminals of the first sub-driving circuit, and is also connected to the second and sixth input terminals of the second sub-driving circuit. The first level output pin is connected to the first input terminal of the first sub-driving circuit and the first input terminal of the second sub-driving circuit, respectively. The second level output pin is connected to the fifth input terminal of the first sub-driving circuit and the fifth input terminal of the second sub-driving circuit, respectively.

3. The bidirectional DC-DC converter circuit according to claim 2, characterized in that, The first sub-driving circuit includes: The first driving branch has a first input terminal connected to the first level output pin, a second input terminal connected to the boost enable pin, a third input terminal connected to the first high-frequency pulse output pin, a fourth input terminal connected to the buck enable pin, and an output terminal connected to the first switching transistor. The second driving branch has a first input terminal connected to the second level output pin, a second input terminal connected to the boost enable pin, a third input terminal connected to the second high-frequency pulse output pin, a fourth input terminal connected to the buck enable pin, and an output terminal connected to the second switching transistor.

4. The bidirectional DC-DC converter circuit according to claim 3, characterized in that, The second sub-driving circuit includes: The third driving branch has a first input terminal connected to the first level output pin, a second input terminal connected to the buck enable pin, a third input terminal connected to the first high-frequency pulse output pin, a fourth input terminal connected to the boost enable pin, and an output terminal connected to the third switching transistor. The fourth driving branch has a first input terminal connected to the second level output pin, a second input terminal connected to the buck enable pin, a third input terminal connected to the second high-frequency pulse output pin, a fourth input terminal connected to the boost enable pin, and an output terminal connected to the fourth switching transistor.

5. The bidirectional DC-DC converter circuit according to claim 3, characterized in that, The first driving branch includes: The first AND gate circuit has its first input terminal connected to the first level output pin, and its second input terminal connected to the boost enable pin. The first diode has its anode connected to the output terminal of the first AND gate circuit, and its cathode connected to the gate of the first switching transistor. The second AND gate circuit has its first input terminal connected to the first high-frequency pulse output pin, and its second input terminal connected to the buck enable pin. The second diode has its anode connected to the output terminal of the second AND gate circuit, and its cathode connected to the gate of the first switching transistor.

6. The bidirectional DC-DC converter circuit according to claim 3, characterized in that, The second drive branch includes: The third AND gate circuit has its first input terminal connected to the second level output pin and its second input terminal connected to the boost enable pin. The third diode, the positive terminal of which is connected to the output terminal of the third AND gate circuit, and the negative terminal of which is connected to the gate of the second switching transistor; The fourth AND gate circuit has its first input terminal connected to the second high-frequency pulse output pin and its second input terminal connected to the buck enable pin. The fourth diode has its anode connected to the output terminal of the fourth AND gate circuit, and its cathode connected to the gate of the second switching transistor.

7. The bidirectional DC-DC converter circuit according to claim 4, characterized in that, The third drive branch includes: The fifth AND gate circuit has its first input terminal connected to the first level output pin and its second input terminal connected to the buck enable pin. The fifth diode has its anode connected to the output terminal of the fifth AND gate circuit, and its cathode connected to the gate of the third switch. The sixth AND gate circuit has its first input terminal connected to the first high-frequency pulse output pin and its second input terminal connected to the boost enable pin. The sixth diode has its anode connected to the output terminal of the sixth AND gate circuit, and its cathode connected to the gate of the third switching transistor.

8. The bidirectional DC-DC converter circuit according to claim 4, characterized in that, The fourth drive branch includes: The seventh AND gate circuit has its first input terminal connected to the second level output pin and its second input terminal connected to the buck enable pin. The seventh diode has its anode connected to the output terminal of the seventh AND gate circuit, and its cathode connected to the gate of the fourth switch. The eighth AND gate circuit, wherein the first input terminal of the eighth AND gate circuit is connected to the second high-frequency pulse output pin, and the second input terminal of the eighth AND gate circuit is connected to the boost enable pin; The eighth diode has its anode connected to the output terminal of the eighth AND gate circuit, and its cathode connected to the gate of the fourth switch.

9. The bidirectional DC-DC converter circuit according to claim 4, characterized in that, The power conversion circuit further includes: A first capacitor, wherein a first terminal of the first capacitor is connected to the drain of the first switching transistor, and a second terminal of the first capacitor is connected to the source of the second switching transistor; The first inductor has its first end connected to the source of the first switching transistor and the drain of the second switching transistor, and its second end connected to the source of the third switching transistor and the drain of the fourth switching transistor. The second capacitor has its first terminal connected to the drain of the third switching transistor and its second terminal connected to the source of the fourth switching transistor.

10. An energy storage device, characterized in that, include: The bidirectional DC-DC converter circuit as described in any one of claims 1 to 9.

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