Switching circuit, chip, and electronic device

Abstract

Embodiments of the present application provide a switching circuit, a chip and an electronic device, the switching circuit comprising: a first transistor and a second transistor, a first end of the first transistor being configured to be connected to a power supply, a second end of the first transistor being connected to a second end of the second transistor, and a first end of the second transistor being configured to be connected to an output interface; and an overcurrent limiting module, the overcurrent limiting module being connected to a control end of the first transistor, the overcurrent limiting module being connected to the second end of the first transistor, and the overcurrent limiting module being connected to a control end of the second transistor. The overcurrent limiting module can increase the impedance of the second transistor when the current of the first transistor is greater than a set threshold, thereby avoiding the phenomenon that the current of the first transistor and the second transistor is too large and damages the first transistor and the second transistor.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a switching circuit, chip, and electronic device. Background Technology

[0002] Currently, two switching transistors are connected in series between the battery module and the charging / discharging interface. By controlling the gate voltage of these two switching transistors, the charging and / or discharging of the battery module can be managed. However, during the battery module's discharge process, if the charging / discharging interface is connected to a low potential or even directly shorted to ground, it may cause a very large current to be generated, thereby damaging the switching transistors. Utility Model Content

[0003] In view of the above problems, embodiments of this application provide a switching circuit, a chip, and an electronic device to solve the above technical problems.

[0004] In a first aspect, embodiments of this application provide a switching circuit, including: A first transistor and a second transistor, wherein the first terminal of the first transistor is used to connect to a power supply, the second terminal of the first transistor is connected to the second terminal of the second transistor, and the first terminal of the second transistor is used to connect to an output interface. An overcurrent limiting module is connected to the control terminal of the first transistor, the second terminal of the first transistor, and the control terminal of the second transistor. Specifically, when the current of the first transistor is greater than a set threshold, the overcurrent limiting module changes the control terminal voltage of the second transistor in response to the current flowing through the first transistor, so as to reduce the current flowing through the first transistor and the second transistor.

[0005] Secondly, embodiments of this application also provide a chip including the aforementioned switching circuit.

[0006] Thirdly, embodiments of this application also provide an electronic device, including the aforementioned chip or switching circuit.

[0007] In the embodiments of this application, the overcurrent limiting module of this application can change the control terminal voltage of the second transistor in response to the current flowing through the first transistor, thereby increasing the impedance of the second transistor or even directly turning off the second transistor when the current of the first transistor is greater than a set threshold, ultimately avoiding the phenomenon that the first transistor and the second transistor are damaged due to excessive current.

[0008] These or other aspects of this application will become more apparent from the description of the following embodiments. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This diagram illustrates a scenario where a laptop computer discharges via a Type-C interface in the relevant art.

[0011] Figure 2 This diagram illustrates a scenario where a car charges and discharges via a PACK interface in the relevant technology.

[0012] Figure 3 A schematic diagram of a switching circuit in an embodiment of this application is shown.

[0013] Figure 4 Another schematic diagram of the switching circuit in an embodiment of this application is shown.

[0014] Figure 5 Another schematic diagram of the switching circuit in an embodiment of this application is shown.

[0015] Figure 6 Another schematic diagram of the switching circuit in an embodiment of this application is shown.

[0016] Figure 7 Another schematic diagram of the switching circuit in an embodiment of this application is shown.

[0017] Figure 8 Another schematic diagram of the switching circuit in an embodiment of this application is shown.

[0018] Figure 9 Another schematic diagram of the switching circuit in an embodiment of this application is shown.

[0019] Figure 10 Another schematic diagram of the switching circuit in an embodiment of this application is shown.

[0020] Figure 11 A schematic diagram of a current comparison unit in an embodiment of this application is shown.

[0021] Figure 12 Another schematic diagram of the current comparison unit in an embodiment of this application is shown.

[0022] Figure 13 Another schematic diagram of the current comparison unit in an embodiment of this application is shown.

[0023] Figure 14 Another schematic diagram of the current comparison unit in an embodiment of this application is shown.

[0024] Figure 15 Another schematic diagram of the current comparison unit in an embodiment of this application is shown.

[0025] Among them, 10 is the overcurrent limiting module, 11 is the current mirror unit, 12 is the standard current unit, 13 is the current comparison unit, 131 is the current amplification subunit, 132 is the level signal output subunit, 133 is the gate control subunit, and 20 is the switch control module. Power supply voltage VBUS, output interface voltage VOUT, first transistor M1, second transistor M2, mirror current IP, standard current I0, third transistor M3, fourth transistor M4, fifth transistor M5, sixth transistor M6, seventh transistor M7, first current source Ia, second current source Ib, reference resistor Rf, first resistor R1, first adjustable resistor Rx, second adjustable resistor Ry, first operational amplifier OP1, mirror amplification current IP', standard amplification current I0', level signal Vt, first transistor Q1, second transistor Q2, first mirror transistor MP1, second mirror transistor MP2, first bias transistor MN1, second bias transistor MN2, first bias voltage VB1, second bias voltage VB2, first sub-transistor Mn1, second sub-transistor Mn2, third sub-transistor Mn3. Detailed Implementation

[0026] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0027] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0028] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0029] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0030] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0031] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0032] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0033] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0034] In the circuit structure provided by the embodiments of this application, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0035] Currently, two switching transistors are connected in series between the battery module and the charging / discharging interface. By controlling the gate voltage of these two switching transistors, the charging and / or discharging of the battery module can be managed.

[0036] For example, taking a laptop discharging externally through a switching circuit as an example, see [link / reference]. Figure 1 , Figure 1 The diagram illustrates a scenario where a laptop computer discharges via a Type-C interface. The laptop's battery BAT is stepped down by a buck circuit BUCK to output a 5V voltage. When switching transistors M01 and M02 are turned on, the battery can discharge via the Type-C interface, thereby powering electronic devices connected to the Type-C interface.

[0037] For example, taking the charging and discharging of a car battery as an example, see [link to relevant documentation]. Figure 2 , Figure 2 The diagram illustrates a scenario where a car charges and discharges via a PACK interface in the relevant technology. When switching transistors M01 and M02 are turned on, if a charging device (such as a charging gun) is connected to the PACK interface, the car battery BAT can be charged. If an electrical device is connected to the PACK interface, the car battery BAT can supply power to the electrical device.

[0038] However, during the battery module discharge process, if the charging / discharging interface is connected to a low potential or even directly shorted to ground, it may cause a very large current to be generated, thereby damaging the switching transistors M01 and M02. Therefore, this application provides a switching circuit, a chip, and an electronic device, which are described in detail below.

[0039] First, refer to Figure 3 , Figure 3 A schematic diagram of a switching circuit in an embodiment of this application is shown, wherein the switching circuit includes a first transistor M1, a second transistor M2, and an overcurrent limiting module 10.

[0040] Specifically, the first terminal of the first transistor M1 is used to connect to the power supply (the voltage of the power supply is referred to as VBUS in the attached figure), the second terminal of the first transistor M1 is connected to the second terminal of the second transistor M2, and the first terminal of the second transistor M2 is used to connect to the output interface (the voltage of the output interface is referred to as VOUT in the attached figure). For example, the power supply may be, but is not limited to, a battery inside an electronic device or a battery inside a new energy vehicle, and the output interface may be, but is not limited to, a Type-C interface or a USB interface of an electronic device or a charging and discharging interface of a new energy vehicle.

[0041] The first transistor M1 and the second transistor M2 can control whether the power supply discharges or charges. For example, when the first transistor M1 and the second transistor M2 are turned on at the same time and the output interface is connected to the electrical device, the power supply can output a discharge voltage through the output interface to drive the electrical device connected to the output interface to work normally. When the output interface is connected to an external power supply for charging, the charging voltage input to the output interface can charge the power supply after the first transistor M1 and the second transistor M2 are turned on at the same time.

[0042] For example, the first transistor M1 and the second transistor M2 can be, but are not limited to, transistors with switching functions such as MOS transistors and IGBT transistors.

[0043] It should be noted that, in the embodiments of this application, the control terminal of each transistor refers to the gate of the transistor, the first terminal of each transistor is one of the source and drain, and the second terminal of each transistor is the other of the source and drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first and second terminals of the transistors in the embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal is the source and the second terminal is the drain; for example, when the transistor is an N-type transistor, the first terminal is the source and the second terminal is the drain.

[0044] The overcurrent limiting module 10 is connected to the control terminal of the first transistor M1, the second terminal of the first transistor M1, and the control terminal of the second transistor M2. The overcurrent limiting module 10 can change the control terminal voltage of the second transistor M2 according to the current of the first transistor M1 to avoid damage to the first transistor M1 and the second transistor M2 due to excessive current flowing through them.

[0045] In some embodiments of this application, the overcurrent limiting module 10 can directly obtain the current of the first transistor M1, and control the control terminal voltage of the second transistor M2 by determining whether the current of the first transistor M1 is greater than a set threshold. In some embodiments of this application, the overcurrent limiting module 10 can mirror the current of the first transistor M1 proportionally. For example, the overcurrent limiting module 10 can mirror the current of the first transistor M1 at a ratio of 1:k (k is greater than 1) and generate a mirrored current. If the mirrored current is greater than 1 / k of the set threshold, it indicates that the current of the first transistor M1 is greater than the set threshold. Therefore, the control terminal voltage of the second transistor M2 can be controlled to reduce the current flowing through the first transistor M1 and the second transistor M2.

[0046] In this embodiment of the application, when the current of the first transistor M1 is greater than a set threshold, the overcurrent limiting module 10 changes the control terminal voltage of the second transistor M2 in response to the current flowing through the first transistor M1, so as to reduce the current flowing through the first transistor M1 and the second transistor M2.

[0047] For example, taking the first transistor M1 and the second transistor M2 as high-level conducting transistors (e.g., NMOS transistors), when the current of the first transistor M1 is greater than a set threshold, the overcurrent limiting module 10 can reduce the control terminal voltage of the second transistor M2 in response to the current flowing through the first transistor M1, thereby increasing the impedance of the second transistor M2 and reducing the current flowing through the first transistor M1 and the second transistor M2.

[0048] For example, if the first transistor M1 and the second transistor M2 are low-level conducting transistors (e.g., PMOS transistors), when the current of the first transistor M1 is greater than a set threshold, the overcurrent limiting module 10 can increase the control terminal voltage of the second transistor M2 in response to the current flowing through the first transistor M1, thereby increasing the impedance of the second transistor M2 and reducing the current flowing through the first transistor M1 and the second transistor M2.

[0049] As can be seen, the overcurrent limiting module 10 of this application can change the control terminal voltage of the second transistor M2 in response to the current flowing through the first transistor M1. Thus, when the current of the first transistor M1 is greater than a set threshold, the impedance of the second transistor M2 can be increased or even the second transistor M2 can be directly turned off, ultimately avoiding the phenomenon that the current of the first transistor M1 and the second transistor M2 is too large and thus damaged.

[0050] It should be noted that the overcurrent limiting module 10 of this application only changes the control terminal voltage of the second transistor M2 when the current of the first transistor M1 is greater than a set threshold. In other cases, the control terminal voltages of the first transistor M1 and the second transistor M2 are controlled by other circuit modules, for example, see [reference needed]. Figure 4 , Figure 4The diagram shows another schematic of the switching circuit in an embodiment of this application. The switching circuit may further include a switch control module 20. The switch control module 20 draws power from the power supply and controls the control terminal voltages of the first transistor M1 and the second transistor M2 to achieve conduction and cutoff control of the first transistor M1 and the second transistor M2. For example, taking the first transistor M1 and the second transistor M2 as high-level conducting transistors (e.g., NMOS transistors), when the switch control module 20 pulls up the control terminal voltages of the first transistor M1 and the second transistor M2, making the control terminal voltages of the first transistor M1 and the second transistor M2 greater than their source voltages, the first transistor M1 and the second transistor M2 can be turned on; when the switch control module 20 pulls down the control terminal voltages of the second transistor M2, making the control terminal voltages of the first transistor M1 and the second transistor M2 less than or equal to their source voltages, the first transistor M1 and the second transistor M2 can be turned off.

[0051] For example, the switch control module 20 may include circuits such as a charge pump and a current source. The charge pump boosts the power supply voltage VBUS, and the current source charges the control terminals of the first transistor M1 and the second transistor M2, ultimately charging the control terminals of the first transistor M1 and the second transistor M2 to the boosted voltage output by the charge pump, so that the first transistor M1 and the second transistor M2, which are low-level conducting transistors, are turned on.

[0052] In some embodiments of this application, the source-drain withstand voltage of the first transistor M1 is greater than that of the second transistor M2. For example, the source-drain withstand voltage of the first transistor M1 can be 24V, and the source-drain withstand voltage of the second transistor M2 can be 7V. When the output interface voltage VOUT is greater than the power supply voltage VBUS, the body diode of the second transistor M2 is turned on, and the first transistor M1 acts as a turn-off transistor and can be normally turned off without damage when the voltage difference between the output interface voltage VOUT and the power supply voltage VBUS is less than 24V. When the power supply voltage VBUS is greater than the output interface voltage VOUT, the body diode of the first transistor M1 is turned on, and the second transistor M2 acts as a turn-off transistor and can be normally turned off without damage when the voltage difference between the power supply voltage VBUS and the output interface voltage VOUT is less than 7V.

[0053] It should be noted that the switching circuit of this application typically results in an output interface voltage VOUT greater than the power supply voltage VBUS. For example, if the output interface is a Type-C interface, the power supply output voltage to the Type-C interface is fixed at 5V, while the Type-C interface may experience a voltage of 20V during charging. Therefore, under normal circumstances... Figure 4In the corresponding embodiment, the source-drain withstand voltage of the first transistor M1 is greater than that of the second transistor M2, so as to avoid the phenomenon that the first transistor M1 and the second transistor M2 are damaged due to the output interface voltage VOUT being too high.

[0054] Meanwhile, since the source-drain withstand voltage of the first transistor M1 is greater than that of the second transistor M2, the size (e.g., aspect ratio) of the first transistor M1 is usually larger than that of the second transistor M2, and the mismatch of the first transistor M1 is smaller than that of the second transistor M2. When the overcurrent limiting module 10 changes the control terminal voltage of the second transistor M2 in response to the current flowing through the first transistor M1, for example, when the overcurrent limiting module 10 mirrors the current of the first transistor M1 proportionally as mentioned later, the mirrored current IP generated by the overcurrent limiting module 10 has higher accuracy, which is beneficial for more accurately judging whether the current flowing through the first transistor M1 and the second transistor M2 exceeds the set threshold.

[0055] It is understood that those skilled in the art can select one of the first transistor M1 and the second transistor M2 as a high-voltage transistor and the other as a low-voltage transistor according to actual needs. For example, in the case where a high voltage is applied to the power supply side, then... Figure 4 In the corresponding embodiment, the second transistor M2 is a high-voltage transistor while the first transistor M1 is a low-voltage transistor.

[0056] In some embodiments of this application, such as an embodiment where the overcurrent limiting module 10 can mirror the current of the first transistor M1 proportionally, see [reference]. Figure 5 , Figure 5 Another schematic diagram of the switching circuit in an embodiment of this application is shown, wherein the overcurrent limiting module 10 includes a current mirror unit 11, a standard current unit 12, and a current comparison unit 13.

[0057] The current mirror unit 11 is connected to the control terminal of the first transistor M1 and the second terminal of the first transistor M1. The current mirror unit 11 can mirror the current of the first transistor M1 proportionally and output the mirrored current IP. For example, the mirrored current IP and the current of the first transistor M1 can satisfy the following relationship: IP=I_M1 / k Where I_M1 is the current of the first transistor M1, and k is the mirror coefficient of the current mirror unit 11 (k>1).

[0058] The standard current unit 12 can output a standard current I0 of standard magnitude. The current comparison unit 13 is connected to the standard current unit 12 to receive the standard current I0. The current comparison unit 13 is connected to the current mirror unit 11 to receive the mirror current IP. The current comparison unit 13 is connected to the control terminal of the second transistor M2. The current comparison unit 13 is used to control the control terminal voltage of the second transistor according to the mirror current IP and the standard current I0. For example, the current comparison unit 13 can compare the magnitude of the standard current I0 and the mirror current IP to determine whether the current of the first transistor M1 exceeds the set threshold and change the control terminal voltage of the second transistor M2.

[0059] For example, taking a threshold value as k times the standard current I0, and the current of the first transistor M1 as k times the mirror current IP (k is greater than 1), when the current of the first transistor M1 is greater than the threshold value, it can be known that: I_M1>Io (I_M1 / k=IP)>(Io / k=I0) Where I_M1 is the current of the first transistor M1, and Io is the set threshold.

[0060] It can be seen that when the current of the first transistor M1 is greater than the set threshold, the mirror current IP is also greater than the standard current I0. Therefore, the current comparison unit 13 can change the control terminal voltage of the second transistor M2. For example, when the second transistor M2 is an NMOS transistor, the current comparison unit 13 can reduce the control terminal voltage of the second transistor M2, thereby reducing the current flowing through the first transistor M1 and the second transistor M2 or directly turning off the second transistor M2, thus avoiding the phenomenon of overcurrent damage to the first transistor M1 and the second transistor M2.

[0061] As an exemplary embodiment of the current mirror unit 11, see [reference]. Figure 6 , Figure 6 Another schematic diagram of the switching circuit in an embodiment of this application is shown, wherein the current mirror unit 11 includes a third transistor M3; the second terminal of the third transistor M3 is connected to the second terminal of the first transistor M1, the control terminal of the third transistor M3 is connected to the control terminal of the first transistor M1, and the first terminal of the third transistor M3 is used to output the mirrored current IP.

[0062] It should be noted that, in Figure 6 In this configuration, the gate voltages of the third transistor M3 and the first transistor M1 are equal and interconnected, and the drain voltages of the third transistor M3 and the first transistor M1 are equal and interconnected. Therefore, the third transistor M3 and the first transistor M1 form a current mirror. At this time, the mirrored current IP output from the source of the third transistor M3 and the current of the first transistor M1 satisfy the following relationship:

[0063] in, The aspect ratio of the third transistor M3. The aspect ratio of the first transistor M1 is... It can be seen that the current of the first transistor M1 can be mirrored proportionally through the third transistor M3 and the mirrored current IP can be output so that the current comparison unit 13 can compare the magnitude of the mirrored current IP with the standard current I0.

[0064] Those skilled in the art will understand that the above embodiment is a relatively basic current mirror circuit in the art. Those skilled in the art can also use other current mirror circuits to mirror the current of the first transistor M1 and output the mirrored current IP, such as Wilson current mirror, low-voltage cascode current mirror, etc.

[0065] As an exemplary embodiment of a standard current unit 12, see [reference]. Figure 7 , Figure 7 Another schematic diagram of the switching circuit in an embodiment of this application is shown. The standard current unit 12 includes a first current source Ia. The magnitude of the current output by the first current source Ia is equal to the magnitude of the standard current I0. Then the current comparison unit 13 can compare the magnitude of the current output by the first current source Ia with the mirror current IP to determine whether the current of the first transistor M1 and the second transistor M2 exceeds the set threshold.

[0066] As another exemplary embodiment of the standard current unit 12, see [reference]. Figure 8 , Figure 8 Another schematic diagram of the switching circuit in an embodiment of this application is shown, wherein the standard current unit 12 further includes a reference resistor Rf, a first resistor R1, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6; the first end of the reference resistor Rf is connected to the first current source Ia, and the second end of the reference resistor Rf is connected to the ground terminal; the second end of the fourth transistor M4 is connected to the first end of the reference resistor Rf, the control terminal of the fourth transistor M4 is connected to the control terminal of the first transistor M1, and the first end of the fourth transistor M4 is connected to the first end of the fifth transistor M5; the first end of the first resistor R1 is connected to the power supply, and the second end of the first resistor R1 is connected to the second end of the fifth transistor M5; the control terminal of the fifth transistor M5 is connected to the control terminal of the first transistor M1, and the first end of the fifth transistor M5 is connected to the second end of the sixth transistor M6; the control terminal of the sixth transistor M6 is connected to the control terminal of the first transistor M1, and the second end of the sixth transistor M6 is used to output the standard current I0.

[0067] It should be noted that the voltage across the first terminal of the reference resistor Rf is clamped to a first set value. Taking the voltage across the first terminal of the reference resistor Rf being clamped to Vref*k0 (k0 is an adjustable coefficient) as an example, combined with... Figure 6 It can be seen that the current flowing through the first resistor R1 and the current flowing through the reference resistor Rf are respectively: I_R1=I_M6+I_M4 I_Rf=I_M4+Ia=Vref*k0 / Rf Wherein, I_R1 is the current flowing through the first resistor R1, I_M6 is the current flowing through the sixth transistor M6, I_M4 is the current flowing through the fourth transistor M4, I_Rf is the current flowing through the reference resistor Rf, and Ia is the current output by the first current source Ia.

[0068] By adjusting the voltage across the first terminal of the reference resistor Rf or by adjusting the value of the reference resistor Rf, the current through the reference resistor Rf can be changed to make I_Rf = I_R1 true. Therefore, according to the above formula, we know that: I_M6+I_M4=I_M4+Ia I_M6=Ia It can be seen that by adjusting the voltage at the first terminal of the reference resistor Rf or by adjusting the value of the reference resistor Rf, the standard current I0 output at the second terminal of the sixth transistor M6 can be made equal to the current output by the first current source Ia. Therefore, by adjusting the value of the current output by the first current source Ia, the value of the standard current I0 (i.e., the set threshold) can be changed, thereby making the set threshold corresponding to the overcurrent phenomenon of the switching circuit adjustable.

[0069] As an exemplary embodiment of clamping the first terminal voltage of the reference resistor Rf, see [reference]. Figure 9 , Figure 9 Another schematic diagram of the switching circuit in an embodiment of this application is shown, wherein the standard current unit 12 further includes a first adjustable resistor Rx, a second adjustable resistor Ry, a seventh transistor M7, and a first operational amplifier OP1; the first terminal of the first adjustable resistor Rx is connected to a reference voltage, the second terminal of the first adjustable resistor Rx is connected to the first terminal of the second adjustable resistor Ry, and the second terminal of the second adjustable resistor Ry is connected to a ground terminal; the second terminal of the seventh transistor M7 is connected to the first terminal of the reference resistor Rf, and the first terminal of the seventh transistor M7 is connected to the second terminal of the fourth transistor M4; the first input terminal of the first operational amplifier OP1 is connected to the first node m1 between the first adjustable resistor Rx and the second adjustable resistor Ry, the second input terminal of the first operational amplifier OP1 is connected to the first terminal of the reference resistor Rf, and the output terminal of the first operational amplifier OP1 is connected to the control terminal of the seventh transistor M7.

[0070] It should be noted that, according to the resistor voltage divider, the voltage at the first input terminal of the first operational amplifier OP1 is:

[0071] Where Vip1 is the voltage at the first input terminal of the first operational amplifier OP1.

[0072] Meanwhile, based on the virtual short and virtual open characteristics of operational amplifiers, the voltage at the second input terminal of the first operational amplifier OP1 is:

[0073] Vin1 is the voltage at the second input terminal of the first operational amplifier OP1.

[0074] Since the second input terminal of the first operational amplifier OP1 is connected to the first terminal of the reference resistor Rf, the voltage at the first terminal of the reference resistor Rf is clamped to... Since the resistances of the first adjustable resistor Rx and the second adjustable resistor Ry are adjustable, the standard current I0 output from the second terminal of the sixth transistor M6 can be made equal to the current output from the first current source Ia by adjusting the resistances of the first adjustable resistor Rx and the second adjustable resistor Ry.

[0075] In some embodiments of this application, see Figure 10 , Figure 10 Another schematic diagram of the switching circuit in an embodiment of this application is shown, wherein the current comparison unit 13 includes a current amplification subunit 131, a level signal output subunit 132, and a gate control subunit 133.

[0076] The current amplification subunit 131 is connected to the current mirror unit 11 to receive the mirror current IP. The current amplification subunit 131 can amplify the mirror current IP and output the mirror amplified current IP'. At the same time, the current amplification subunit 131 is connected to the standard current unit 12 to receive the standard current I0. The current amplification subunit 131 can amplify the standard current I0 and output the standard amplified current I0'.

[0077] The level signal output subunit 132 is connected to the current amplification subunit 131 to receive the mirror amplification current IP' and the standard amplification current I0'. The level signal output subunit 132 can compare the magnitudes of the mirror amplification current IP' and the standard amplification current I0' and output a level signal Vt. The gate control subunit 133 is connected to the level signal output subunit 132 and is also connected to the second transistor M2. The gate control subunit 133 can change the control terminal voltage of the second transistor M2 in response to the level signal Vt.

[0078] It should be noted that, in order to reduce the power consumption and heat of the overcurrent limiting module 10, the standard current I0 and the mirror current IP are usually much smaller than the current of the first transistor M1. The current amplification subunit 131 can appropriately amplify the mirror current IP and the standard current I0, thereby improving the signal-to-noise ratio of the mirror current IP and the standard current I0. This allows the level signal output subunit 132 to accurately determine whether the mirror current IP exceeds the standard current I0, and outputs a level signal Vt when the mirror current IP exceeds the standard current I0, causing the gate control subunit 133 to change the control terminal voltage of the second transistor M2.

[0079] As an exemplary embodiment of the current amplification subunit 131, see [reference]. Figure 11 , Figure 11 A schematic diagram of a current comparison unit 13 in an embodiment of this application is shown, wherein the current amplification subunit 131 includes a first transistor Q1 and a second transistor Q2; the first terminal of the first transistor Q1 is connected to a mirror current IP, the base of the first transistor Q1 is connected to a first base current, and the second terminal of the first transistor Q1 is used to output a mirror amplified current IP'; the first terminal of the second transistor Q2 is connected to a standard current I0, the base of the second transistor Q2 is connected to a second base current, and the second terminal of the second transistor Q2 is used to output a standard amplified current I0'.

[0080] It should be noted that the first transistor Q1 and the second transistor Q2 are NPN transistors. According to the formula for calculating the collector current of an NPN transistor, the mirror amplification current IP' and the standard amplification current I0' satisfy the following relationship: IP' = IP + IB1 I0'=I0+IB2 It can be seen that the second terminal of the first transistor Q1 can output the amplified mirror current IP', and the second terminal of the second transistor Q2 can output the amplified standard current I0', thus improving the signal-to-noise ratio of the standard current I0 and the mirror current IP.

[0081] As an exemplary embodiment of the level signal output subunit 132, see [reference]. Figure 12 , Figure 12Another schematic diagram of the current comparison unit 13 in this embodiment is shown, wherein the level signal output subunit 132 includes a first mirror transistor MP1, a second mirror transistor MP2, a first bias transistor MN1, and a second bias transistor MN2; the first terminal of the first mirror transistor MP1 is connected to the mirror amplification current IP', and the control terminal of the first mirror transistor MP1 is connected to the second terminal of the first mirror transistor MP1; the second terminal of the first bias transistor MN1 is connected to the second terminal of the first mirror transistor MP1, the first terminal of the first bias transistor MN1 is connected to the ground terminal, and the control terminal of the first bias transistor MN1 is connected to the first bias voltage VB1; the first terminal of the second mirror transistor MP2 is connected to the standard amplification current I0', and the control terminal of the second mirror transistor MP2 is connected to the control terminal of the first mirror transistor MP1; the second terminal of the second bias transistor MN2 is connected to the second terminal of the second mirror transistor MP2, the first terminal of the second bias transistor MN2 is connected to the ground terminal, and the control terminal of the second bias transistor MN2 is connected to the first bias voltage VB1; wherein, the second terminal of the second mirror transistor MP2 is used to output the level signal Vt.

[0082] It should be noted that the first mirror transistor MP1 and the second mirror transistor MP2 form a current mirror. The second mirror transistor MP2 will mirror the current of the first mirror transistor MP1. If the mirrored amplified current IP' is greater than the standard amplified current I0', the voltage at the second terminal of the second mirror transistor MP2 will be pulled high. Therefore, the second terminal of the second mirror transistor MP2 can output a high-level signal Vt to the gate control subunit 133, so that the gate control subunit 133 can change the control terminal voltage of the second transistor MP2 in response to the high-level signal Vt.

[0083] As an exemplary embodiment of the gate control subunit 133, see [reference]. Figure 13 , Figure 13 Another schematic diagram of the current comparison unit 13 in an embodiment of this application is shown, wherein the gate control subunit 133 includes a first sub-transistor Mn1, a second sub-transistor Mn2, and a second current source Ib; the second terminal of the first sub-transistor Mn1 is connected to a power supply, the control terminal of the first sub-transistor Mn1 is connected to a level signal Vt, and the first terminal of the first sub-transistor Mn1 is connected to the second current source Ib; the second terminal of the second sub-transistor Mn2 is connected to the control terminal of the second sub-transistor Mn2, the first terminal of the second sub-transistor Mn2 is connected to a ground terminal, and the control terminal of the second sub-transistor Mn2 is connected to the first terminal of the first sub-transistor Mn1.

[0084] For example, when the mirror amplification current IP' is greater than the standard amplification current I0', after the gate control subunit 133 receives the high-level signal Vt, the first sub-transistor Mn1 is turned on, and the control terminal voltage of the second sub-transistor Mn2 is pulled high and turned on. Since the second terminal of the second sub-transistor Mn2 is connected to the control terminal of the second transistor M2, the turned-on second sub-transistor Mn2 can pull down the gate voltage of the second transistor M2, causing the second transistor M2 to turn off (in this embodiment, the second transistor M2 is an NMOS transistor), thereby avoiding the phenomenon that the first transistor M1 and the second transistor M2 are damaged due to excessive current.

[0085] It is understood that the implementation of the gate control subunit 133 is not limited to this. For example, in some possible embodiments, the gate control subunit 133 may only include the second sub-transistor Mn2, and the control terminal of the second sub-transistor Mn2 is connected to the level signal output subunit 132 to output the level signal Vt.

[0086] In some embodiments of this application, see Figure 14 , Figure 14 Another schematic diagram of the current comparison unit 13 in an embodiment of this application is shown, wherein the gate control subunit 133 further includes a third sub-transistor Mn3; the second terminal of the third sub-transistor Mn3 is connected to the control terminal of the first sub-transistor Mn1, the first terminal of the third sub-transistor Mn3 is connected to the ground terminal, and the control terminal of the third sub-transistor Mn3 is connected to the first terminal of the first sub-transistor Mn1.

[0087] It should be noted that when the mirror amplification current IP' is greater than the standard amplification current I0', the gate control subunit 133 receives a high-level signal Vt, and after the first sub-transistor Mn1 is turned on, the control terminal voltage of the third sub-transistor Mn3 is also pulled high and turned on. Therefore, after the third sub-transistor Mn3 is turned on, it can pull down the control terminal voltage of the first sub-transistor Mn1, avoiding the phenomenon that the first sub-transistor Mn1 is in the on state for a long time, causing the second sub-transistor Mn2 to be turned on continuously, thus making it impossible to turn on the second sub-transistor M2 again.

[0088] It is worth noting that the above description of the switching circuit is intended to clearly illustrate the implementation and verification process of this application. Those skilled in the art can make equivalent modifications or further designs under the guidance of this application. For example, refer to... Figure 15 , Figure 15 This paper shows another schematic diagram of the current comparison unit 13 in an embodiment of this application. The level signal output subunit 132 may further include a PMOS transistor MP3, and the gate control subunit 133 may further include a fourth sub-transistor Mn4 controlled by an enable signal EN. The fourth sub-transistor Mn4 can control whether the overcurrent limiting module 10 is enabled. For example, see [reference needed]. Figure 15 The gate control subunit 133 may further include a fifth sub-transistor Mn5, a sixth sub-transistor Mp1, a seventh sub-transistor Mp2, and a third current source Ic. An indicator signal Vz can be output through the fifth sub-transistor Mn5, the sixth sub-transistor Mp1, the seventh sub-transistor Mp2, and the third current source Ic. The indicator signal Vz can indicate whether an overcurrent phenomenon has occurred in the switching circuit. For example, see [reference needed]. Figure 15 The level signal output subunit 132 may also include bias transistors MN3 and MN4 biased by the second bias voltage VB2, and resistors R01 and R02.

[0089] This application also provides a chip that includes the aforementioned switching circuit. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be, but is not limited to, a System on Chip (SOC) chip or a System in Package (SIP) chip. Since the chip of this application possesses the switching circuit described in the above embodiments, it has all the beneficial effects of the switching circuit in the above embodiments, which will not be repeated here.

[0090] This application also provides an electronic device, which includes a device body and a chip as described above disposed within the device body. The electronic device may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car center console screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0091] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A switching circuit, characterized in that, include: A first transistor and a second transistor, wherein a first terminal of the first transistor is used to connect to a power supply, a second terminal of the first transistor is connected to a second terminal of the second transistor, and a first terminal of the second transistor is used to connect to an output interface; An overcurrent limiting module is provided, wherein the overcurrent limiting module is connected to the control terminal of the first transistor, the overcurrent limiting module is connected to the second terminal of the first transistor, and the overcurrent limiting module is connected to the control terminal of the second transistor; When the current of the first transistor is greater than a set threshold, the overcurrent limiting module changes the control terminal voltage of the second transistor in response to the current flowing through the first transistor, so as to reduce the current flowing through the first transistor and the second transistor.

2. The switching circuit as described in claim 1, characterized in that, The overcurrent limiting module includes a current mirror unit, a standard current unit, and a current comparison unit. The current mirror unit is connected to the control terminal of the first transistor and the second terminal of the first transistor to mirror the current of the first transistor proportionally and output the mirrored current. The standard current unit for outputting standard current is connected to the current comparison unit, and the current mirror unit is connected to the current comparison unit; The current comparison unit is connected to the control terminal of the second transistor, and the current comparison unit is used to control the control terminal voltage of the second transistor according to the mirror current and the standard current.

3. The switching circuit as described in claim 2, characterized in that, The set threshold is k times the magnitude of the standard current, and the current magnitude of the first transistor is k times the mirror current, where k is greater than 1.

4. The switching circuit as described in claim 2, characterized in that, The current mirror unit includes a third transistor; The second terminal of the third transistor is connected to the second terminal of the first transistor, the control terminal of the third transistor is connected to the control terminal of the first transistor, and the first terminal of the third transistor is used to output the mirror current.

5. The switching circuit as described in claim 2, characterized in that, The standard current unit includes a first current source, the magnitude of which is equal to the magnitude of the standard current.

6. The switching circuit as described in claim 5, characterized in that, The standard current unit also includes a reference resistor, a first resistor, a fourth transistor, a fifth transistor, and a sixth transistor; The first end of the reference resistor is connected to the first current source, and the second end of the reference resistor is connected to the ground terminal; The second terminal of the fourth transistor is connected to the first terminal of the reference resistor, the control terminal of the fourth transistor is connected to the control terminal of the first transistor, and the first terminal of the fourth transistor is connected to the first terminal of the fifth transistor. The first end of the first resistor is connected to the power supply, and the second end of the first resistor is connected to the second end of the fifth transistor. The control terminal of the fifth transistor is connected to the control terminal of the first transistor, and the first terminal of the fifth transistor is connected to the second terminal of the sixth transistor; The control terminal of the sixth transistor is connected to the control terminal of the first transistor, and the second terminal of the sixth transistor is used to output the standard current. The voltage at the first terminal of the reference resistor is clamped to a first set value.

7. The switching circuit as described in claim 6, characterized in that, The standard current unit also includes a first adjustable resistor, a second adjustable resistor, a seventh transistor, and a first operational amplifier; The first terminal of the first adjustable resistor is connected to a reference voltage, the second terminal of the first adjustable resistor is connected to the first terminal of the second adjustable resistor, and the second terminal of the second adjustable resistor is connected to a ground terminal. The second terminal of the seventh transistor is connected to the first terminal of the reference resistor, and the first terminal of the seventh transistor is connected to the second terminal of the fourth transistor; The first input terminal of the first operational amplifier is connected to the first node between the first adjustable resistor and the second adjustable resistor, the second input terminal of the first operational amplifier is connected to the first end of the reference resistor, and the output terminal of the first operational amplifier is connected to the control terminal of the seventh transistor.

8. The switching circuit as described in claim 2, characterized in that, The current comparison unit includes a current amplification subunit, a level signal output subunit, and a gate control subunit. The current amplification subunit is connected to the current mirror unit to receive the mirror current and output the mirror amplified current; the current amplification subunit is connected to the standard current unit to receive the standard current and output the standard amplified current. The level signal output subunit is connected to the current amplification subunit to receive the mirror amplification current and the standard amplification current and output a level signal; The gate control subunit is connected to the level signal output subunit, and the gate control subunit is connected to the second transistor to change the control terminal voltage of the second transistor in response to the level signal.

9. The switching circuit as described in claim 8, characterized in that, The current amplification subunit includes a first transistor and a second transistor; The first terminal of the first transistor is connected to the mirror current, the base of the first transistor is connected to the first base current, and the second terminal of the first transistor is used to output the mirror amplified current. The first terminal of the second transistor is connected to the standard current, the base of the second transistor is connected to the second base current, and the second terminal of the second transistor is used to output the standard amplified current.

10. The switching circuit as described in claim 8, characterized in that, The level signal output subunit includes a first mirror transistor, a second mirror transistor, a first bias transistor, and a second bias transistor; The first terminal of the first mirror transistor is connected to the mirror amplification current, and the control terminal of the first mirror transistor is connected to the second terminal of the first mirror transistor. The second terminal of the first bias transistor is connected to the second terminal of the first mirror transistor, the first terminal of the first bias transistor is connected to the ground terminal, and the control terminal of the first bias transistor is connected to the first bias voltage. The first terminal of the second mirror transistor is connected to the standard amplified current, and the control terminal of the second mirror transistor is connected to the control terminal of the first mirror transistor. The second terminal of the second bias transistor is connected to the second terminal of the second mirror transistor, the first terminal of the second bias transistor is connected to the ground terminal, and the control terminal of the second bias transistor is connected to the first bias voltage. The second terminal of the second mirror transistor is used to output the level signal.

11. The switching circuit as described in claim 8, characterized in that, The gate control subunit includes a first sub-transistor, a second sub-transistor, and a second current source; The second terminal of the first sub-transistor is connected to a power source, the control terminal of the first sub-transistor is connected to a level signal, and the first terminal of the first sub-transistor is connected to the second current source. The second terminal of the second sub-transistor is connected to the control terminal of the second sub-transistor, the first terminal of the second sub-transistor is connected to the ground terminal, and the control terminal of the second sub-transistor is connected to the first terminal of the first sub-transistor.

12. The switching circuit as described in claim 11, characterized in that, The gate control subunit further includes a third sub-transistor; The second terminal of the third sub-transistor is connected to the control terminal of the first sub-transistor, the first terminal of the third sub-transistor is connected to the ground terminal, and the control terminal of the third sub-transistor is connected to the first terminal of the first sub-transistor.

13. The switching circuit according to any one of claims 1 to 12, characterized in that, The source-drain breakdown voltage of the first transistor is greater than that of the second transistor.

14. A chip, characterized in that, Includes the switching circuit described in any one of claims 1 to 13.

15. An electronic device, characterized in that, It includes a device body and a chip as described in claim 14 disposed on the device body.

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