A logic control circuit

Abstract

The utility model relates to the field of electronic information technology discloses a simple structure, high reliability and be applicable to logic control circuit of negative pressure monitoring, including the first switch circuit (101) for receiving a control signal, second switch circuit (102) and third switch circuit (103), its first end is coupled in the third end of second switch circuit (102), wherein, when the control signal of input is high level, the first switch circuit (101) is controlled to conduct, second switch circuit (102) is controlled to conduct, third switch circuit (103) is controlled to cut off, and its second end output is high level, when the control signal of input is low level, the first switch circuit (101) is controlled to cut off, second switch circuit (102) is controlled to cut off, third switch circuit (103) is controlled to cut off, and its second end output is low level.

Description

Technical Field

[0001] This utility model relates to the field of electronic information technology, and more specifically, to a logic control circuit. Background Technology

[0002] In recent years, with the rapid development of industrial automation, automotive electronics, communication equipment, and consumer electronics, higher requirements have been placed on the control accuracy, reliability, and power consumption of circuit systems. Especially in applications such as power management, level conversion, and status monitoring, traditional solutions typically use comparators or dedicated level conversion chips to detect and control high and low levels, which suffers from problems such as high cost, circuit complexity, slow response speed, and poor anti-interference capability.

[0003] For example, in negative voltage monitoring scenarios, traditional solutions are mostly designed for positive voltages and are difficult to directly adapt to negative voltage systems such as -40V. Furthermore, they lack effective isolation between small signals and large logic circuits, which can easily lead to interference or damage to the front-end control circuit and affect system stability.

[0004] Therefore, it is necessary to provide a logic control circuit that is simple in structure, low in cost, highly reliable, and suitable for negative pressure monitoring, in order to meet the needs of modern electronic systems for efficient, accurate, and low-power control. Utility Model Content

[0005] The technical problem to be solved by this utility model is that the above-mentioned traditional solutions in the prior art usually use comparators or dedicated level conversion chips to realize the detection and control of high and low levels, which have defects such as high cost, complex circuit, slow response speed and poor anti-interference ability. This utility model provides a logic control circuit that is simple in structure, highly reliable and suitable for negative pressure monitoring.

[0006] The technical solution adopted by this utility model to solve its technical problem is: to construct a logic control circuit, which has the following features: The first switching circuit is configured within the logic control circuit to receive a control signal; The second switching circuit has its first terminal connected to one terminal of the first switching circuit. The second terminal of the second switching circuit is connected to a power supply terminal. The third terminal of the second switching circuit is connected to one end of the controlled object; The third switching circuit has its first terminal coupled to the third terminal of the second switching circuit. The second terminal of the third switching circuit is connected to one terminal of the main controller. The third terminal of the third switching circuit is connected to the common terminal; When the input control signal is high, the first switch circuit is turned on, the second switch circuit is turned on, and the third switch circuit is turned off, with its second terminal outputting a high level. When the input control signal is low, the first switch circuit is controlled to be cut off, the second switch circuit is controlled to be cut off, and the third switch circuit is switched from being cut off to being turned on, with its second terminal outputting a low level.

[0007] In some embodiments, the first switching circuit includes at least a first transistor. The control signal is input to the base of the first transistor through the thirty-seventh resistor. The collector of the first transistor is connected to the first terminal of the second switching circuit. The emitter of the first transistor is connected to the -40V power supply terminal.

[0008] In some embodiments, the second switching circuit includes at least a second transistor. The base of the second transistor is connected to the collector of the first transistor through the twentieth resistor. The emitter of the second transistor is connected to one of the power supply terminals. The collector of the second transistor is connected to one end of the controlled object and the first end of the third switching circuit, respectively.

[0009] In some embodiments, the third switching circuit includes at least a third transistor. The base of the third transistor is connected to the collector of the second transistor through a first resistor. The collector of the third transistor is connected to one end of the main controller. The emitter of the third transistor is connected to the common terminal.

[0010] In some embodiments, the first switching circuit further includes a filter circuit, one end of which is connected to the emitter of the first transistor. The other end of the filter circuit is connected to the common terminal.

[0011] In some embodiments, the filter circuit includes a first capacitor and a second capacitor connected in parallel. One end of the first capacitor and one end of the second capacitor are connected to the emitter of the first transistor. The other end of the first capacitor and the second capacitor are connected to a common terminal.

[0012] In some embodiments, the resistance value of the thirty-seventh resistor is selected as 33K.

[0013] In some implementations, the resistance value of the twentieth resistor is selected as 47K.

[0014] In some implementations, the resistance value of the first resistor is selected as 10K.

[0015] In some embodiments, the first transistor and the third transistor are selected as NPN transistors. The second transistor is selected as a PNP type transistor.

[0016] The logic control circuit described in this utility model includes a first switch circuit, a second switch circuit, and a third switch circuit for receiving a control signal. The first terminal of the third switch circuit is coupled to the third terminal of the second switch circuit. When the input control signal is high, the first switch circuit is turned on, the second switch circuit is turned on, and the third switch circuit is turned off, with its second terminal outputting a high level. When the input control signal is low, the first switch circuit is turned off, the second switch circuit is turned off, and the third switch circuit switches from off to on, with its second terminal outputting a low level. Compared with existing technologies, the cooperation of the first and second switch circuits enables negative pressure monitoring, effectively monitoring the status of negative power supplies such as -40V, filling the gap in traditional positive pressure detection schemes. On the other hand, electrical isolation and anti-interference are achieved through the first and second switching circuits. That is, the front-end control signal and the back-end controlled power signal are effectively isolated through transistors, which enhances the anti-interference capability of the system. Attached Figure Description

[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings: Figure 1 This is a schematic diagram of an embodiment of the logic control circuit provided by this utility model. Detailed Implementation

[0018] To provide a clearer understanding of the technical features, objectives, and effects of this utility model, the specific embodiments of this utility model will now be described in detail with reference to the accompanying drawings.

[0019] like Figure 1 As shown, in the first embodiment of the logic control circuit of this utility model, the logic control circuit 10 includes a first switching circuit 101, a second switching circuit 102, and a third switching circuit 103. Among them, the first switch circuit 101, the second switch circuit 102 and the third switch circuit 103 all have the function of switching; Specifically, the first switching circuit 101 is configured within the logic control circuit to receive a control signal (corresponding to PA-T). The input control signal (corresponding to PA-T) is used to control the conduction state of the first switching circuit 101. When the input control signal (corresponding to PA-T) is high, the first switching circuit 101 is turned on. When the input control signal (corresponding to PA-T) is low, the first switching circuit 101 is turned off. Furthermore, the first terminal of the second switching circuit 102 is connected to one terminal of the first switching circuit 101. The second terminal of the second switching circuit 102 is connected to a power supply terminal (corresponding to +8V). The third terminal of the second switching circuit 102 is connected to one end of the controlled object (corresponding to PA-DSP); Furthermore, the first terminal of the third switching circuit 103 is coupled to the third terminal of the second switching circuit 102. The second terminal of the third switching circuit 103 is connected to one terminal of the main controller (corresponding to MCU-IO). The second terminal of the third switching circuit 103 is also connected to a power supply terminal (corresponding to +3.3V) through the third resistor R3. The third terminal of the third switching circuit 103 is connected to the common terminal; When the input control signal (corresponding to PA-T) is high, the first switch circuit 101 is turned on, the second switch circuit 102 is turned on, and the third switch circuit 103 is turned off. Its second terminal output is high, that is, the level signal of one terminal of the main controller (corresponding to MCU-IO) is high. When the input control signal (corresponding to PA-T) is low, the first switch circuit 101 is controlled to be cut off, the second switch circuit 102 is controlled to be cut off, and the third switch circuit 103 is switched from cut off to conduction. Its second terminal output is low, that is, the level signal of one terminal of the input main controller (corresponding to MCU-IO) is low.

[0020] Using this technical solution, through the cooperation of the first switching circuit 101 and the second switching circuit 102, negative pressure monitoring capability is achieved, effectively monitoring the status of negative power supplies such as -40V, filling the gap in traditional positive pressure detection solutions; On the other hand, electrical isolation and anti-interference are achieved through the first switching circuit 101 and the second switching circuit 102. That is, the front-end control signal and the back-end controlled power signal are effectively isolated through transistors, which enhances the anti-interference capability of the system. In some embodiments, the first switching circuit 101 includes at least a first transistor Q16, which is selected as an NPN transistor and has a switching function; Specifically, the control signal (corresponding to PA-T) is input to the base of the first transistor Q16 through the thirty-seventh resistor R137, wherein the resistance value of the thirty-seventh resistor R137 is selected as 33K.

[0021] The collector of the first transistor Q16 is connected to the first terminal of the second switching circuit 102. The emitter of the first transistor Q16 is connected to the -40V power supply.

[0022] By utilizing the conduction characteristics of NPN transistors under negative voltage, effective status monitoring of negative power supplies such as -40V is achieved, filling the gap in traditional positive voltage detection solutions.

[0023] In some embodiments, the second switching circuit 102 includes at least a second transistor Q13, which is selected as a PNP transistor and has a switching function; Specifically, the base of the second transistor Q13 is connected to the collector of the first transistor Q16 through the twentieth resistor R120, wherein the resistance of the twentieth resistor is selected as 47K. Specifically, the emitter of the second transistor Q13 is connected to a power supply terminal (corresponding to +8V). The collector of the second transistor Q13 is connected to one end of the controlled object (corresponding to PA-DSP) and the first end of the third switching circuit 103, respectively.

[0024] The control circuit consumes very little power when it is off, and by adjusting the resistance values ​​of the thirty-seventh resistor R137 and the twentieth resistor R120, it can be flexibly adapted to different control levels and power supply voltages, making it highly versatile. The control signal (PA-T) input at the front end is effectively isolated from the controlled power supply (-40V, +8V) at the back end through a transistor, which enhances the anti-interference capability of the control circuit.

[0025] In some embodiments, the third switching circuit 103 includes at least a third transistor Q1, which is selected as an NPN transistor and has a switching function; Specifically, the base of the third transistor Q1 is connected to the collector of the second transistor Q13 through the first resistor R1. The collector of the third transistor Q1 is connected to one end of the main controller (corresponding to MCU-IO), and the collector of the third transistor Q1 is also connected to a power supply terminal (corresponding to +3.3V) through the third resistor R3. The resistance values ​​of the first resistor R1 and the third resistor R3 are selected as 10K.

[0026] The emitter of the third transistor Q1 is connected to the common terminal.

[0027] Its working principle is as follows: The high level of the control signal (PA-T) is applied to the base of the first transistor Q16 through the 37th resistor R137. The emitter of the first transistor Q16 is connected to -40V. The base potential is higher than the emitter potential, which satisfies the NPN conduction condition. The first transistor Q16 is saturated and conducts. After conduction, the collector potential of the first transistor Q16 is pulled low. The emitter of the second transistor Q13 is connected to +8V, and the base is connected to the collector of the first transistor Q16 (approximately -40V) via the twentieth resistor R120.

[0028] At this time, the emitter potential (+8V) of the second transistor Q13 is much higher than the base potential, which satisfies the PNP conduction condition. The second transistor Q13 is saturated and conducts, outputting a normal positive voltage. The voltage is reduced by the first resistor R1 in the subsequent stage, which turns on the third transistor Q1, and the MCU-IO output is low. If the -40V is not working properly, the PA-DSP will be at a low level, and the MCU-IO feedback will be at a high level. When the control signal (PA-T) is low, the low level of PA-T makes the base potential of the first transistor Q16 close to 0V. In reality, because the base does not have sufficient forward bias (NPN requires VBE>0.7V to conduct), the first transistor Q16 is cut off. The base of the second transistor Q13 is connected to the potential via the twentieth resistor R120. Because the first transistor Q16 is cut off, the base of the second transistor Q13 cannot be pulled low enough to make VEB meet the conduction requirement. The second transistor Q13 is cut off. Since there is no high-level drive, the potential is pulled down to about 0V, that is, the PA-DSP outputs 0V. Then the third transistor Q1 is turned on, and the MCU-IO outputs a high level.

[0029] In some embodiments, the first switching circuit 101 further includes a filter circuit, one end of which is connected to the emitter of the first transistor Q16. The other end of the filter circuit is connected to the common terminal.

[0030] In some implementations, the filter circuit includes a first capacitor C1 and a second capacitor C2 connected in parallel. One end of the first capacitor C1 and the second capacitor C2 are connected to the emitter of the first transistor Q16. The other ends of the first capacitor C1 and the second capacitor C2 are connected to the common terminal.

[0031] Specifically, when the control signal (PA-T) is high: The high level is supplied to the base of the first transistor Q16 through the 37th resistor R137. Since the first transistor Q16 is an NPN transistor, its base potential (approximately the high level value) is much higher than its emitter potential (-40V), satisfying the conduction condition Vbe>0.7V, and the first transistor Q16 enters the saturation conduction state. After the first transistor Q16 is saturated and turned on, the potential of its collector (NodeA) is pulled down to near its emitter potential (about -40V). At this time, the emitter of the second transistor Q13 is connected to +8V, and its base is pulled down to about -40V through R120. The emitter junction is forward biased (Veb≈8V-(-40V)=48V>>0.7V), and the second transistor Q13 also enters the saturation conduction state. After the second transistor Q13 is turned on, its collector (Node B) outputs a high level close to +8V. This high level drives the third transistor Q1 (usually NPN type) to turn on through the first resistor R1, causing the logic output terminal (MCU-IO) to be pulled low to ground level (≈0V), that is, a low level signal is fed back to the MCU, indicating that the back-end circuit (-40V power supply) is working normally.

[0032] When the control signal (PA-T) is low (or the -40V power supply fails abnormally): A low level (≈0V) of PA-T is applied to the base of the first transistor Q16. At this time, the base potential (0V) of the first transistor Q16 is approximately 40V compared to its emitter potential (-40V), and theoretically it should conduct. However, in this application scenario, a low level of PA-T usually means that the front-end control logic intends to shut down the monitoring path, or that the potential is raised to near 0V due to an abnormality in the -40V power supply (such as an open circuit). At this point, the emitter of the first transistor Q16 no longer maintains -40V, and the first transistor Q16 is cut off because there is no effective forward bias. After the first transistor Q16 is turned off, its collector (Node A) is in a high-resistance state. There is no significant current in the second resistor R120, and the base potential of the second transistor Q13 is pulled up to its emitter potential (+8V). Since Veb≈0V of the second transistor Q13, the conduction condition is not met, and the second transistor Q13 is turned off. After the second transistor Q13 is turned off, there is no voltage output at the second output node (Node B), and the potential is approximately 0V. Therefore, the third transistor Q1 is cut off because there is no driving current at its base; The logic output terminal (MCU-IO) is pulled to a high level (e.g., 3.3V) through an internal or external pull-up resistor (not shown in the figure), which feeds back a high-level signal to the MCU. This indicates that the back-end circuit (-40V power supply) is malfunctioning or is in a closed state.

[0033] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A logic control circuit, characterized in that, have: The first switching circuit is configured within the logic control circuit to receive a control signal; The second switching circuit has its first terminal connected to one terminal of the first switching circuit. The second terminal of the second switching circuit is connected to a power supply terminal. The third terminal of the second switching circuit is connected to one end of the controlled object; The third switching circuit has its first terminal coupled to the third terminal of the second switching circuit. The second terminal of the third switching circuit is connected to one terminal of the main controller. The third terminal of the third switching circuit is connected to the common terminal; When the input control signal is high, the first switch circuit is turned on, the second switch circuit is turned on, and the third switch circuit is turned off, with its second terminal outputting a high level. When the input control signal is low, the first switch circuit is controlled to be cut off, the second switch circuit is controlled to be cut off, and the third switch circuit is switched from being cut off to being turned on, with its second terminal outputting a low level.

2. The logic control circuit according to claim 1, characterized in that, The first switching circuit includes at least a first transistor. The control signal is input to the base of the first transistor through the thirty-seventh resistor. The collector of the first transistor is connected to the first terminal of the second switching circuit. The emitter of the first transistor is connected to the -40V power supply terminal.

3. The logic control circuit according to claim 2, characterized in that, The second switching circuit includes at least a second transistor. The base of the second transistor is connected to the collector of the first transistor through the twentieth resistor. The emitter of the second transistor is connected to one of the power supply terminals. The collector of the second transistor is connected to one end of the controlled object and the first end of the third switching circuit, respectively.

4. The logic control circuit according to claim 3, characterized in that, The third switching circuit includes at least a third transistor. The base of the third transistor is connected to the collector of the second transistor through a first resistor. The collector of the third transistor is connected to one end of the main controller. The emitter of the third transistor is connected to the common terminal.

5. The logic control circuit according to claim 2, characterized in that, The first switching circuit further includes a filter circuit, one end of which is connected to the emitter of the first transistor. The other end of the filter circuit is connected to the common terminal.

6. The logic control circuit according to claim 5, characterized in that, The filter circuit includes a first capacitor and a second capacitor connected in parallel. One end of the first capacitor and one end of the second capacitor are connected to the emitter of the first transistor. The other end of the first capacitor and the second capacitor are connected to a common terminal.

7. The logic control circuit according to claim 2, characterized in that, The resistance value of the thirty-seventh resistor is selected as 33K.

8. The logic control circuit according to claim 3, characterized in that, The resistance value of the twentieth resistor is selected as 47K.

9. The logic control circuit according to claim 4, characterized in that, The resistance value of the first resistor is selected as 10K.

10. The logic control circuit according to claim 4, characterized in that, Both the first transistor and the third transistor are NPN type transistors. The second transistor is selected as a PNP type transistor.

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